drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49 #include <power/regulator.h>
  50 #include <thermal.h>
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  55 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  56         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  57 #define OMAP_HSMMC_USE_GPIO
  58 #else
  59 #undef OMAP_HSMMC_USE_GPIO
  60 #endif
  61
  62 /* common definitions for all OMAPs */
  63 #define SYSCTL_SRC      (1 << 25)
  64 #define SYSCTL_SRD      (1 << 26)
  65
  66 #ifdef CONFIG_IODELAY_RECALIBRATION
  67 struct omap_hsmmc_pinctrl_state {
  68         struct pad_conf_entry *padconf;
  69         int npads;
  70         struct iodelay_cfg_entry *iodelay;
  71         int niodelays;
  72 };
  73 #endif
  74
  75 struct omap_hsmmc_data {
  76         struct hsmmc *base_addr;
  77 #if !CONFIG_IS_ENABLED(DM_MMC)
  78         struct mmc_config cfg;
  79 #endif
  80         uint bus_width;
  81         uint clock;
  82         ushort last_cmd;
  83 #ifdef OMAP_HSMMC_USE_GPIO
  84 #if CONFIG_IS_ENABLED(DM_MMC)
  85         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  86         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  87 #else
  88         int cd_gpio;
  89         int wp_gpio;
  90 #endif
  91 #endif
  92 #if CONFIG_IS_ENABLED(DM_MMC)
  93         enum bus_mode mode;
  94 #endif
  95         u8 controller_flags;
  96 #ifdef CONFIG_MMC_OMAP_HS_ADMA
  97         struct omap_hsmmc_adma_desc *adma_desc_table;
  98         uint desc_slot;
  99 #endif
 100         const char *hw_rev;
 101         struct udevice *pbias_supply;
 102         uint signal_voltage;
 103 #ifdef CONFIG_IODELAY_RECALIBRATION
 104         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 113 #endif
 114 };
 115
 116 struct omap_mmc_of_data {
 117         u8 controller_flags;
 118 };
 119
 120 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 121 struct omap_hsmmc_adma_desc {
 122         u8 attr;
 123         u8 reserved;
 124         u16 len;
 125         u32 addr;
 126 };
 127
 128 #define ADMA_MAX_LEN    63488
 129
 130 /* Decriptor table defines */
 131 #define ADMA_DESC_ATTR_VALID            BIT(0)
 132 #define ADMA_DESC_ATTR_END              BIT(1)
 133 #define ADMA_DESC_ATTR_INT              BIT(2)
 134 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 135 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 136
 137 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 138 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 139 #endif
 140
 141 /* If we fail after 1 second wait, something is really bad */
 142 #define MAX_RETRY_MS    1000
 143 #define MMC_TIMEOUT_MS  20
 144
 145 /* DMA transfers can take a long time if a lot a data is transferred.
 146  * The timeout must take in account the amount of data. Let's assume
 147  * that the time will never exceed 333 ms per MB (in other word we assume
 148  * that the bandwidth is always above 3MB/s).
 149  */
 150 #define DMA_TIMEOUT_PER_MB      333
 151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 152 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 153 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 154 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 155
 156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 158                         unsigned int siz);
 159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 162
 163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 164 {
 165 #if CONFIG_IS_ENABLED(DM_MMC)
 166         return dev_get_priv(mmc->dev);
 167 #else
 168         return (struct omap_hsmmc_data *)mmc->priv;
 169 #endif
 170 }
 171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 172 {
 173 #if CONFIG_IS_ENABLED(DM_MMC)
 174         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 175         return &plat->cfg;
 176 #else
 177         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 178 #endif
 179 }
 180
 181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 182 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 183 {
 184         int ret;
 185
 186 #ifndef CONFIG_DM_GPIO
 187         if (!gpio_is_valid(gpio))
 188                 return -1;
 189 #endif
 190         ret = gpio_request(gpio, label);
 191         if (ret)
 192                 return ret;
 193
 194         ret = gpio_direction_input(gpio);
 195         if (ret)
 196                 return ret;
 197
 198         return gpio;
 199 }
 200 #endif
 201
 202 static unsigned char mmc_board_init(struct mmc *mmc)
 203 {
 204 #if defined(CONFIG_OMAP34XX)
 205         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 206         t2_t *t2_base = (t2_t *)T2_BASE;
 207         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 208         u32 pbias_lite;
 209 #ifdef CONFIG_MMC_OMAP36XX_PINS
 210         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 211 #endif
 212
 213         pbias_lite = readl(&t2_base->pbias_lite);
 214         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 215 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 216         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 217         pbias_lite &= ~PBIASLITEVMODE0;
 218 #endif
 219 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 220         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 221         pbias_lite &= ~PBIASLITEVMODE1;
 222 #endif
 223 #ifdef CONFIG_MMC_OMAP36XX_PINS
 224         if (get_cpu_family() == CPU_OMAP36XX) {
 225                 /* Disable extended drain IO before changing PBIAS */
 226                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 227                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 228         }
 229 #endif
 230         writel(pbias_lite, &t2_base->pbias_lite);
 231
 232         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 233                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 234                 &t2_base->pbias_lite);
 235
 236 #ifdef CONFIG_MMC_OMAP36XX_PINS
 237         if (get_cpu_family() == CPU_OMAP36XX)
 238                 /* Enable extended drain IO after changing PBIAS */
 239                 writel(wkup_ctrl |
 240                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 241                                 OMAP34XX_CTRL_WKUP_CTRL);
 242 #endif
 243         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 244                 &t2_base->devconf0);
 245
 246         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 247                 &t2_base->devconf1);
 248
 249         /* Change from default of 52MHz to 26MHz if necessary */
 250         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 251                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 252                         &t2_base->ctl_prog_io1);
 253
 254         writel(readl(&prcm_base->fclken1_core) |
 255                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 256                 &prcm_base->fclken1_core);
 257
 258         writel(readl(&prcm_base->iclken1_core) |
 259                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 260                 &prcm_base->iclken1_core);
 261 #endif
 262
 263 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 264         !CONFIG_IS_ENABLED(DM_REGULATOR)
 265         /* PBIAS config needed for MMC1 only */
 266         if (mmc_get_blk_desc(mmc)->devnum == 0)
 267                 vmmc_pbias_config(LDO_VOLT_3V0);
 268 #endif
 269
 270         return 0;
 271 }
 272
 273 void mmc_init_stream(struct hsmmc *mmc_base)
 274 {
 275         ulong start;
 276
 277         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 278
 279         writel(MMC_CMD0, &mmc_base->cmd);
 280         start = get_timer(0);
 281         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 282                 if (get_timer(0) - start > MAX_RETRY_MS) {
 283                         printf("%s: timedout waiting for cc!\n", __func__);
 284                         return;
 285                 }
 286         }
 287         writel(CC_MASK, &mmc_base->stat)
 288                 ;
 289         writel(MMC_CMD0, &mmc_base->cmd)
 290                 ;
 291         start = get_timer(0);
 292         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 293                 if (get_timer(0) - start > MAX_RETRY_MS) {
 294                         printf("%s: timedout waiting for cc2!\n", __func__);
 295                         return;
 296                 }
 297         }
 298         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 299 }
 300
 301 #if CONFIG_IS_ENABLED(DM_MMC)
 302 #ifdef CONFIG_IODELAY_RECALIBRATION
 303 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 304 {
 305         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 306         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 307
 308         switch (priv->mode) {
 309         case MMC_HS_200:
 310                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 311                 break;
 312         case UHS_SDR104:
 313                 pinctrl_state = priv->sdr104_pinctrl_state;
 314                 break;
 315         case UHS_SDR50:
 316                 pinctrl_state = priv->sdr50_pinctrl_state;
 317                 break;
 318         case UHS_DDR50:
 319                 pinctrl_state = priv->ddr50_pinctrl_state;
 320                 break;
 321         case UHS_SDR25:
 322                 pinctrl_state = priv->sdr25_pinctrl_state;
 323                 break;
 324         case UHS_SDR12:
 325                 pinctrl_state = priv->sdr12_pinctrl_state;
 326                 break;
 327         case SD_HS:
 328         case MMC_HS:
 329         case MMC_HS_52:
 330                 pinctrl_state = priv->hs_pinctrl_state;
 331                 break;
 332         case MMC_DDR_52:
 333                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 334         default:
 335                 pinctrl_state = priv->default_pinctrl_state;
 336                 break;
 337         }
 338
 339         if (!pinctrl_state)
 340                 pinctrl_state = priv->default_pinctrl_state;
 341
 342         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 343                 if (pinctrl_state->iodelay)
 344                         late_recalibrate_iodelay(pinctrl_state->padconf,
 345                                                  pinctrl_state->npads,
 346                                                  pinctrl_state->iodelay,
 347                                                  pinctrl_state->niodelays);
 348                 else
 349                         do_set_mux32((*ctrl)->control_padconf_core_base,
 350                                      pinctrl_state->padconf,
 351                                      pinctrl_state->npads);
 352         }
 353 }
 354 #endif
 355 static void omap_hsmmc_set_timing(struct mmc *mmc)
 356 {
 357         u32 val;
 358         struct hsmmc *mmc_base;
 359         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 360
 361         mmc_base = priv->base_addr;
 362
 363         omap_hsmmc_stop_clock(mmc_base);
 364         val = readl(&mmc_base->ac12);
 365         val &= ~AC12_UHSMC_MASK;
 366         priv->mode = mmc->selected_mode;
 367
 368         if (mmc_is_mode_ddr(priv->mode))
 369                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 370         else
 371                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 372
 373         switch (priv->mode) {
 374         case MMC_HS_200:
 375         case UHS_SDR104:
 376                 val |= AC12_UHSMC_SDR104;
 377                 break;
 378         case UHS_SDR50:
 379                 val |= AC12_UHSMC_SDR50;
 380                 break;
 381         case MMC_DDR_52:
 382         case UHS_DDR50:
 383                 val |= AC12_UHSMC_DDR50;
 384                 break;
 385         case SD_HS:
 386         case MMC_HS_52:
 387         case UHS_SDR25:
 388                 val |= AC12_UHSMC_SDR25;
 389                 break;
 390         case MMC_LEGACY:
 391         case MMC_HS:
 392         case SD_LEGACY:
 393         case UHS_SDR12:
 394                 val |= AC12_UHSMC_SDR12;
 395                 break;
 396         default:
 397                 val |= AC12_UHSMC_RES;
 398                 break;
 399         }
 400         writel(val, &mmc_base->ac12);
 401
 402 #ifdef CONFIG_IODELAY_RECALIBRATION
 403         omap_hsmmc_io_recalibrate(mmc);
 404 #endif
 405         omap_hsmmc_start_clock(mmc_base);
 406 }
 407
 408 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 409 {
 410         struct hsmmc *mmc_base;
 411         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 412         u32 hctl, ac12;
 413
 414         mmc_base = priv->base_addr;
 415
 416         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 417         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 418
 419         switch (signal_voltage) {
 420         case MMC_SIGNAL_VOLTAGE_330:
 421                 hctl |= SDVS_3V0;
 422                 break;
 423         case MMC_SIGNAL_VOLTAGE_180:
 424                 hctl |= SDVS_1V8;
 425                 ac12 |= AC12_V1V8_SIGEN;
 426                 break;
 427         }
 428
 429         writel(hctl, &mmc_base->hctl);
 430         writel(ac12, &mmc_base->ac12);
 431 }
 432
 433 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 434 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
 435 {
 436         int ret = -ETIMEDOUT;
 437         u32 con;
 438         bool dat0_high;
 439         bool target_dat0_high = !!state;
 440         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 441         struct hsmmc *mmc_base = priv->base_addr;
 442
 443         con = readl(&mmc_base->con);
 444         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 445
 446         timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
 447         while (timeout--)       {
 448                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 449                 if (dat0_high == target_dat0_high) {
 450                         ret = 0;
 451                         break;
 452                 }
 453                 udelay(10);
 454         }
 455         writel(con, &mmc_base->con);
 456
 457         return ret;
 458 }
 459 #endif
 460
 461 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 462 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 463 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 464 {
 465         int ret = 0;
 466         int uV = mV * 1000;
 467
 468         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 469
 470         if (!mmc->vqmmc_supply)
 471                 return 0;
 472
 473         /* Disable PBIAS */
 474         ret = regulator_set_enable(priv->pbias_supply, false);
 475         if (ret && ret != -ENOSYS)
 476                 return ret;
 477
 478         /* Turn off IO voltage */
 479         ret = regulator_set_enable(mmc->vqmmc_supply, false);
 480         if (ret && ret != -ENOSYS)
 481                 return ret;
 482         /* Program a new IO voltage value */
 483         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 484         if (ret)
 485                 return ret;
 486         /* Turn on IO voltage */
 487         ret = regulator_set_enable(mmc->vqmmc_supply, true);
 488         if (ret && ret != -ENOSYS)
 489                 return ret;
 490
 491         /* Program PBIAS voltage*/
 492         ret = regulator_set_value(priv->pbias_supply, uV);
 493         if (ret && ret != -ENOSYS)
 494                 return ret;
 495         /* Enable PBIAS */
 496         ret = regulator_set_enable(priv->pbias_supply, true);
 497         if (ret && ret != -ENOSYS)
 498                 return ret;
 499
 500         return 0;
 501 }
 502 #endif
 503
 504 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 505 {
 506         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 507         struct hsmmc *mmc_base = priv->base_addr;
 508         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 509         u32 capa_mask;
 510         __maybe_unused u8 palmas_ldo_volt;
 511         u32 val;
 512
 513         if (mv < 0)
 514                 return -EINVAL;
 515
 516         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 517                 /* Use 3.0V rather than 3.3V */
 518                 mv = 3000;
 519                 capa_mask = VS30_3V0SUP;
 520                 palmas_ldo_volt = LDO_VOLT_3V0;
 521         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 522                 capa_mask = VS18_1V8SUP;
 523                 palmas_ldo_volt = LDO_VOLT_1V8;
 524         } else {
 525                 return -EOPNOTSUPP;
 526         }
 527
 528         val = readl(&mmc_base->capa);
 529         if (!(val & capa_mask))
 530                 return -EOPNOTSUPP;
 531
 532         priv->signal_voltage = mmc->signal_voltage;
 533
 534         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 535
 536 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 537         return omap_hsmmc_set_io_regulator(mmc, mv);
 538 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 539         defined(CONFIG_PALMAS_POWER)
 540         if (mmc_get_blk_desc(mmc)->devnum == 0)
 541                 vmmc_pbias_config(palmas_ldo_volt);
 542         return 0;
 543 #else
 544         return 0;
 545 #endif
 546 }
 547 #endif
 548
 549 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 550 {
 551         struct hsmmc *mmc_base;
 552         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 553         u32 val;
 554
 555         mmc_base = priv->base_addr;
 556         val = readl(&mmc_base->capa);
 557
 558         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 559                 val |= (VS30_3V0SUP | VS18_1V8SUP);
 560         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 561                 val |= VS30_3V0SUP;
 562                 val &= ~VS18_1V8SUP;
 563         } else {
 564                 val |= VS18_1V8SUP;
 565                 val &= ~VS30_3V0SUP;
 566         }
 567
 568         writel(val, &mmc_base->capa);
 569
 570         return val;
 571 }
 572
 573 #ifdef MMC_SUPPORTS_TUNING
 574 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 575 {
 576         struct hsmmc *mmc_base;
 577         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 578         u32 val;
 579
 580         mmc_base = priv->base_addr;
 581         val = readl(&mmc_base->ac12);
 582         val &= ~(AC12_SCLK_SEL);
 583         writel(val, &mmc_base->ac12);
 584
 585         val = readl(&mmc_base->dll);
 586         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 587         writel(val, &mmc_base->dll);
 588 }
 589
 590 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 591 {
 592         int i;
 593         struct hsmmc *mmc_base;
 594         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 595         u32 val;
 596
 597         mmc_base = priv->base_addr;
 598         val = readl(&mmc_base->dll);
 599         val |= DLL_FORCE_VALUE;
 600         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 601         val |= (count << DLL_FORCE_SR_C_SHIFT);
 602         writel(val, &mmc_base->dll);
 603
 604         val |= DLL_CALIB;
 605         writel(val, &mmc_base->dll);
 606         for (i = 0; i < 1000; i++) {
 607                 if (readl(&mmc_base->dll) & DLL_CALIB)
 608                         break;
 609         }
 610         val &= ~DLL_CALIB;
 611         writel(val, &mmc_base->dll);
 612 }
 613
 614 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 615 {
 616         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 617         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 618         struct mmc *mmc = upriv->mmc;
 619         struct hsmmc *mmc_base;
 620         u32 val;
 621         u8 cur_match, prev_match = 0;
 622         int ret;
 623         u32 phase_delay = 0;
 624         u32 start_window = 0, max_window = 0;
 625         u32 length = 0, max_len = 0;
 626         bool single_point_failure = false;
 627         struct udevice *thermal_dev;
 628         int temperature;
 629         int i;
 630
 631         mmc_base = priv->base_addr;
 632         val = readl(&mmc_base->capa2);
 633
 634         /* clock tuning is not needed for upto 52MHz */
 635         if (!((mmc->selected_mode == MMC_HS_200) ||
 636               (mmc->selected_mode == UHS_SDR104) ||
 637               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 638                 return 0;
 639
 640         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 641         if (ret) {
 642                 printf("Couldn't get thermal device for tuning\n");
 643                 return ret;
 644         }
 645         ret = thermal_get_temp(thermal_dev, &temperature);
 646         if (ret) {
 647                 printf("Couldn't get temperature for tuning\n");
 648                 return ret;
 649         }
 650         val = readl(&mmc_base->dll);
 651         val |= DLL_SWT;
 652         writel(val, &mmc_base->dll);
 653
 654         /*
 655          * Stage 1: Search for a maximum pass window ignoring any
 656          * any single point failures. If the tuning value ends up
 657          * near it, move away from it in stage 2 below
 658          */
 659         while (phase_delay <= MAX_PHASE_DELAY) {
 660                 omap_hsmmc_set_dll(mmc, phase_delay);
 661
 662                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 663
 664                 if (cur_match) {
 665                         if (prev_match) {
 666                                 length++;
 667                         } else if (single_point_failure) {
 668                                 /* ignore single point failure */
 669                                 length++;
 670                                 single_point_failure = false;
 671                         } else {
 672                                 start_window = phase_delay;
 673                                 length = 1;
 674                         }
 675                 } else {
 676                         single_point_failure = prev_match;
 677                 }
 678
 679                 if (length > max_len) {
 680                         max_window = start_window;
 681                         max_len = length;
 682                 }
 683
 684                 prev_match = cur_match;
 685                 phase_delay += 4;
 686         }
 687
 688         if (!max_len) {
 689                 ret = -EIO;
 690                 goto tuning_error;
 691         }
 692
 693         val = readl(&mmc_base->ac12);
 694         if (!(val & AC12_SCLK_SEL)) {
 695                 ret = -EIO;
 696                 goto tuning_error;
 697         }
 698         /*
 699          * Assign tuning value as a ratio of maximum pass window based
 700          * on temperature
 701          */
 702         if (temperature < -20000)
 703                 phase_delay = min(max_window + 4 * max_len - 24,
 704                                   max_window +
 705                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 706         else if (temperature < 20000)
 707                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 708         else if (temperature < 40000)
 709                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 710         else if (temperature < 70000)
 711                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 712         else if (temperature < 90000)
 713                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 714         else if (temperature < 120000)
 715                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 716         else
 717                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 718
 719         /*
 720          * Stage 2: Search for a single point failure near the chosen tuning
 721          * value in two steps. First in the +3 to +10 range and then in the
 722          * +2 to -10 range. If found, move away from it in the appropriate
 723          * direction by the appropriate amount depending on the temperature.
 724          */
 725         for (i = 3; i <= 10; i++) {
 726                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 727                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 728                         if (temperature < 10000)
 729                                 phase_delay += i + 6;
 730                         else if (temperature < 20000)
 731                                 phase_delay += i - 12;
 732                         else if (temperature < 70000)
 733                                 phase_delay += i - 8;
 734                         else if (temperature < 90000)
 735                                 phase_delay += i - 6;
 736                         else
 737                                 phase_delay += i - 6;
 738
 739                         goto single_failure_found;
 740                 }
 741         }
 742
 743         for (i = 2; i >= -10; i--) {
 744                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 745                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 746                         if (temperature < 10000)
 747                                 phase_delay += i + 12;
 748                         else if (temperature < 20000)
 749                                 phase_delay += i + 8;
 750                         else if (temperature < 70000)
 751                                 phase_delay += i + 8;
 752                         else if (temperature < 90000)
 753                                 phase_delay += i + 10;
 754                         else
 755                                 phase_delay += i + 12;
 756
 757                         goto single_failure_found;
 758                 }
 759         }
 760
 761 single_failure_found:
 762
 763         omap_hsmmc_set_dll(mmc, phase_delay);
 764
 765         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 766         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 767
 768         return 0;
 769
 770 tuning_error:
 771
 772         omap_hsmmc_disable_tuning(mmc);
 773         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 774         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 775
 776         return ret;
 777 }
 778 #endif
 779
 780 static void omap_hsmmc_send_init_stream(struct udevice *dev)
 781 {
 782         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 783         struct hsmmc *mmc_base = priv->base_addr;
 784
 785         mmc_init_stream(mmc_base);
 786 }
 787 #endif
 788
 789 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 790 {
 791         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 792         struct hsmmc *mmc_base = priv->base_addr;
 793         u32 irq_mask = INT_EN_MASK;
 794
 795         /*
 796          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 797          * tuning procedure and DCRC should be disabled. But see occurences
 798          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 799          * interrupts occur along with BRR, so the data is actually in the
 800          * buffer. It has to be debugged why these interrutps occur
 801          */
 802         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 803                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 804
 805         writel(irq_mask, &mmc_base->ie);
 806 }
 807
 808 static int omap_hsmmc_init_setup(struct mmc *mmc)
 809 {
 810         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 811         struct hsmmc *mmc_base;
 812         unsigned int reg_val;
 813         unsigned int dsor;
 814         ulong start;
 815
 816         mmc_base = priv->base_addr;
 817         mmc_board_init(mmc);
 818
 819         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 820                 &mmc_base->sysconfig);
 821         start = get_timer(0);
 822         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 823                 if (get_timer(0) - start > MAX_RETRY_MS) {
 824                         printf("%s: timedout waiting for cc2!\n", __func__);
 825                         return -ETIMEDOUT;
 826                 }
 827         }
 828         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 829         start = get_timer(0);
 830         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 831                 if (get_timer(0) - start > MAX_RETRY_MS) {
 832                         printf("%s: timedout waiting for softresetall!\n",
 833                                 __func__);
 834                         return -ETIMEDOUT;
 835                 }
 836         }
 837 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 838         reg_val = readl(&mmc_base->hl_hwinfo);
 839         if (reg_val & MADMA_EN)
 840                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 841 #endif
 842
 843 #if CONFIG_IS_ENABLED(DM_MMC)
 844         reg_val = omap_hsmmc_set_capabilities(mmc);
 845         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ?
 846                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 847 #else
 848         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 849         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 850                 &mmc_base->capa);
 851 #endif
 852
 853         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 854
 855         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 856                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 857                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 858
 859         dsor = 240;
 860         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 861                 (ICE_STOP | DTO_15THDTO));
 862         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 863                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 864         start = get_timer(0);
 865         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 866                 if (get_timer(0) - start > MAX_RETRY_MS) {
 867                         printf("%s: timedout waiting for ics!\n", __func__);
 868                         return -ETIMEDOUT;
 869                 }
 870         }
 871         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 872
 873         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 874
 875         mmc_enable_irq(mmc, NULL);
 876
 877 #if !CONFIG_IS_ENABLED(DM_MMC)
 878         mmc_init_stream(mmc_base);
 879 #endif
 880
 881         return 0;
 882 }
 883
 884 /*
 885  * MMC controller internal finite state machine reset
 886  *
 887  * Used to reset command or data internal state machines, using respectively
 888  * SRC or SRD bit of SYSCTL register
 889  */
 890 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 891 {
 892         ulong start;
 893
 894         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 895
 896         /*
 897          * CMD(DAT) lines reset procedures are slightly different
 898          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 899          * According to OMAP3 TRM:
 900          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 901          * returns to 0x0.
 902          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 903          * procedure steps must be as follows:
 904          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 905          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 906          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 907          * 3. Wait until the SRC (SRD) bit returns to 0x0
 908          *    (reset procedure is completed).
 909          */
 910 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 911         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 912         if (!(readl(&mmc_base->sysctl) & bit)) {
 913                 start = get_timer(0);
 914                 while (!(readl(&mmc_base->sysctl) & bit)) {
 915                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 916                                 return;
 917                 }
 918         }
 919 #endif
 920         start = get_timer(0);
 921         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 922                 if (get_timer(0) - start > MAX_RETRY_MS) {
 923                         printf("%s: timedout waiting for sysctl %x to clear\n",
 924                                 __func__, bit);
 925                         return;
 926                 }
 927         }
 928 }
 929
 930 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 931 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 932 {
 933         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 934         struct omap_hsmmc_adma_desc *desc;
 935         u8 attr;
 936
 937         desc = &priv->adma_desc_table[priv->desc_slot];
 938
 939         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 940         if (!end)
 941                 priv->desc_slot++;
 942         else
 943                 attr |= ADMA_DESC_ATTR_END;
 944
 945         desc->len = len;
 946         desc->addr = (u32)buf;
 947         desc->reserved = 0;
 948         desc->attr = attr;
 949 }
 950
 951 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 952                                           struct mmc_data *data)
 953 {
 954         uint total_len = data->blocksize * data->blocks;
 955         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 956         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 957         int i = desc_count;
 958         char *buf;
 959
 960         priv->desc_slot = 0;
 961         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 962                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 963                                 sizeof(struct omap_hsmmc_adma_desc));
 964
 965         if (data->flags & MMC_DATA_READ)
 966                 buf = data->dest;
 967         else
 968                 buf = (char *)data->src;
 969
 970         while (--i) {
 971                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 972                 buf += ADMA_MAX_LEN;
 973                 total_len -= ADMA_MAX_LEN;
 974         }
 975
 976         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 977
 978         flush_dcache_range((long)priv->adma_desc_table,
 979                            (long)priv->adma_desc_table +
 980                            ROUND(desc_count *
 981                            sizeof(struct omap_hsmmc_adma_desc),
 982                            ARCH_DMA_MINALIGN));
 983 }
 984
 985 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 986 {
 987         struct hsmmc *mmc_base;
 988         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 989         u32 val;
 990         char *buf;
 991
 992         mmc_base = priv->base_addr;
 993         omap_hsmmc_prepare_adma_table(mmc, data);
 994
 995         if (data->flags & MMC_DATA_READ)
 996                 buf = data->dest;
 997         else
 998                 buf = (char *)data->src;
 999
1000         val = readl(&mmc_base->hctl);
1001         val |= DMA_SELECT;
1002         writel(val, &mmc_base->hctl);
1003
1004         val = readl(&mmc_base->con);
1005         val |= DMA_MASTER;
1006         writel(val, &mmc_base->con);
1007
1008         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1009
1010         flush_dcache_range((u32)buf,
1011                            (u32)buf +
1012                            ROUND(data->blocksize * data->blocks,
1013                                  ARCH_DMA_MINALIGN));
1014 }
1015
1016 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1017 {
1018         struct hsmmc *mmc_base;
1019         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1020         u32 val;
1021
1022         mmc_base = priv->base_addr;
1023
1024         val = readl(&mmc_base->con);
1025         val &= ~DMA_MASTER;
1026         writel(val, &mmc_base->con);
1027
1028         val = readl(&mmc_base->hctl);
1029         val &= ~DMA_SELECT;
1030         writel(val, &mmc_base->hctl);
1031
1032         kfree(priv->adma_desc_table);
1033 }
1034 #else
1035 #define omap_hsmmc_adma_desc
1036 #define omap_hsmmc_prepare_adma_table
1037 #define omap_hsmmc_prepare_data
1038 #define omap_hsmmc_dma_cleanup
1039 #endif
1040
1041 #if !CONFIG_IS_ENABLED(DM_MMC)
1042 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1043                         struct mmc_data *data)
1044 {
1045         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1046 #else
1047 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1048                         struct mmc_data *data)
1049 {
1050         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1051         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1052         struct mmc *mmc = upriv->mmc;
1053 #endif
1054         struct hsmmc *mmc_base;
1055         unsigned int flags, mmc_stat;
1056         ulong start;
1057         priv->last_cmd = cmd->cmdidx;
1058
1059         mmc_base = priv->base_addr;
1060
1061         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1062                 return 0;
1063
1064         start = get_timer(0);
1065         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1066                 if (get_timer(0) - start > MAX_RETRY_MS) {
1067                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1068                                         __func__);
1069                         return -ETIMEDOUT;
1070                 }
1071         }
1072         writel(0xFFFFFFFF, &mmc_base->stat);
1073         start = get_timer(0);
1074         while (readl(&mmc_base->stat)) {
1075                 if (get_timer(0) - start > MAX_RETRY_MS) {
1076                         printf("%s: timedout waiting for STAT (%x) to clear\n",
1077                                 __func__, readl(&mmc_base->stat));
1078                         return -ETIMEDOUT;
1079                 }
1080         }
1081         /*
1082          * CMDREG
1083          * CMDIDX[13:8] : Command index
1084          * DATAPRNT[5]  : Data Present Select
1085          * ENCMDIDX[4]  : Command Index Check Enable
1086          * ENCMDCRC[3]  : Command CRC Check Enable
1087          * RSPTYP[1:0]
1088          *      00 = No Response
1089          *      01 = Length 136
1090          *      10 = Length 48
1091          *      11 = Length 48 Check busy after response
1092          */
1093         /* Delay added before checking the status of frq change
1094          * retry not supported by mmc.c(core file)
1095          */
1096         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1097                 udelay(50000); /* wait 50 ms */
1098
1099         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1100                 flags = 0;
1101         else if (cmd->resp_type & MMC_RSP_136)
1102                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1103         else if (cmd->resp_type & MMC_RSP_BUSY)
1104                 flags = RSP_TYPE_LGHT48B;
1105         else
1106                 flags = RSP_TYPE_LGHT48;
1107
1108         /* enable default flags */
1109         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1110                         MSBS_SGLEBLK);
1111         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1112
1113         if (cmd->resp_type & MMC_RSP_CRC)
1114                 flags |= CCCE_CHECK;
1115         if (cmd->resp_type & MMC_RSP_OPCODE)
1116                 flags |= CICE_CHECK;
1117
1118         if (data) {
1119                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1120                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1121                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1122                         data->blocksize = 512;
1123                         writel(data->blocksize | (data->blocks << 16),
1124                                                         &mmc_base->blk);
1125                 } else
1126                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1127
1128                 if (data->flags & MMC_DATA_READ)
1129                         flags |= (DP_DATA | DDIR_READ);
1130                 else
1131                         flags |= (DP_DATA | DDIR_WRITE);
1132
1133 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1134                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1135                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1136                         omap_hsmmc_prepare_data(mmc, data);
1137                         flags |= DE_ENABLE;
1138                 }
1139 #endif
1140         }
1141
1142         mmc_enable_irq(mmc, cmd);
1143
1144         writel(cmd->cmdarg, &mmc_base->arg);
1145         udelay(20);             /* To fix "No status update" error on eMMC */
1146         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1147
1148         start = get_timer(0);
1149         do {
1150                 mmc_stat = readl(&mmc_base->stat);
1151                 if (get_timer(start) > MAX_RETRY_MS) {
1152                         printf("%s : timeout: No status update\n", __func__);
1153                         return -ETIMEDOUT;
1154                 }
1155         } while (!mmc_stat);
1156
1157         if ((mmc_stat & IE_CTO) != 0) {
1158                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1159                 return -ETIMEDOUT;
1160         } else if ((mmc_stat & ERRI_MASK) != 0)
1161                 return -1;
1162
1163         if (mmc_stat & CC_MASK) {
1164                 writel(CC_MASK, &mmc_base->stat);
1165                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1166                         if (cmd->resp_type & MMC_RSP_136) {
1167                                 /* response type 2 */
1168                                 cmd->response[3] = readl(&mmc_base->rsp10);
1169                                 cmd->response[2] = readl(&mmc_base->rsp32);
1170                                 cmd->response[1] = readl(&mmc_base->rsp54);
1171                                 cmd->response[0] = readl(&mmc_base->rsp76);
1172                         } else
1173                                 /* response types 1, 1b, 3, 4, 5, 6 */
1174                                 cmd->response[0] = readl(&mmc_base->rsp10);
1175                 }
1176         }
1177
1178 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1179         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1180             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1181                 u32 sz_mb, timeout;
1182
1183                 if (mmc_stat & IE_ADMAE) {
1184                         omap_hsmmc_dma_cleanup(mmc);
1185                         return -EIO;
1186                 }
1187
1188                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1189                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1190                 if (timeout < MAX_RETRY_MS)
1191                         timeout = MAX_RETRY_MS;
1192
1193                 start = get_timer(0);
1194                 do {
1195                         mmc_stat = readl(&mmc_base->stat);
1196                         if (mmc_stat & TC_MASK) {
1197                                 writel(readl(&mmc_base->stat) | TC_MASK,
1198                                        &mmc_base->stat);
1199                                 break;
1200                         }
1201                         if (get_timer(start) > timeout) {
1202                                 printf("%s : DMA timeout: No status update\n",
1203                                        __func__);
1204                                 return -ETIMEDOUT;
1205                         }
1206                 } while (1);
1207
1208                 omap_hsmmc_dma_cleanup(mmc);
1209                 return 0;
1210         }
1211 #endif
1212
1213         if (data && (data->flags & MMC_DATA_READ)) {
1214                 mmc_read_data(mmc_base, data->dest,
1215                                 data->blocksize * data->blocks);
1216         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1217                 mmc_write_data(mmc_base, data->src,
1218                                 data->blocksize * data->blocks);
1219         }
1220         return 0;
1221 }
1222
1223 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1224 {
1225         unsigned int *output_buf = (unsigned int *)buf;
1226         unsigned int mmc_stat;
1227         unsigned int count;
1228
1229         /*
1230          * Start Polled Read
1231          */
1232         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1233         count /= 4;
1234
1235         while (size) {
1236                 ulong start = get_timer(0);
1237                 do {
1238                         mmc_stat = readl(&mmc_base->stat);
1239                         if (get_timer(0) - start > MAX_RETRY_MS) {
1240                                 printf("%s: timedout waiting for status!\n",
1241                                                 __func__);
1242                                 return -ETIMEDOUT;
1243                         }
1244                 } while (mmc_stat == 0);
1245
1246                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1247                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1248
1249                 if ((mmc_stat & ERRI_MASK) != 0)
1250                         return 1;
1251
1252                 if (mmc_stat & BRR_MASK) {
1253                         unsigned int k;
1254
1255                         writel(readl(&mmc_base->stat) | BRR_MASK,
1256                                 &mmc_base->stat);
1257                         for (k = 0; k < count; k++) {
1258                                 *output_buf = readl(&mmc_base->data);
1259                                 output_buf++;
1260                         }
1261                         size -= (count*4);
1262                 }
1263
1264                 if (mmc_stat & BWR_MASK)
1265                         writel(readl(&mmc_base->stat) | BWR_MASK,
1266                                 &mmc_base->stat);
1267
1268                 if (mmc_stat & TC_MASK) {
1269                         writel(readl(&mmc_base->stat) | TC_MASK,
1270                                 &mmc_base->stat);
1271                         break;
1272                 }
1273         }
1274         return 0;
1275 }
1276
1277 #if CONFIG_IS_ENABLED(MMC_WRITE)
1278 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1279                           unsigned int size)
1280 {
1281         unsigned int *input_buf = (unsigned int *)buf;
1282         unsigned int mmc_stat;
1283         unsigned int count;
1284
1285         /*
1286          * Start Polled Write
1287          */
1288         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1289         count /= 4;
1290
1291         while (size) {
1292                 ulong start = get_timer(0);
1293                 do {
1294                         mmc_stat = readl(&mmc_base->stat);
1295                         if (get_timer(0) - start > MAX_RETRY_MS) {
1296                                 printf("%s: timedout waiting for status!\n",
1297                                                 __func__);
1298                                 return -ETIMEDOUT;
1299                         }
1300                 } while (mmc_stat == 0);
1301
1302                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1303                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1304
1305                 if ((mmc_stat & ERRI_MASK) != 0)
1306                         return 1;
1307
1308                 if (mmc_stat & BWR_MASK) {
1309                         unsigned int k;
1310
1311                         writel(readl(&mmc_base->stat) | BWR_MASK,
1312                                         &mmc_base->stat);
1313                         for (k = 0; k < count; k++) {
1314                                 writel(*input_buf, &mmc_base->data);
1315                                 input_buf++;
1316                         }
1317                         size -= (count*4);
1318                 }
1319
1320                 if (mmc_stat & BRR_MASK)
1321                         writel(readl(&mmc_base->stat) | BRR_MASK,
1322                                 &mmc_base->stat);
1323
1324                 if (mmc_stat & TC_MASK) {
1325                         writel(readl(&mmc_base->stat) | TC_MASK,
1326                                 &mmc_base->stat);
1327                         break;
1328                 }
1329         }
1330         return 0;
1331 }
1332 #else
1333 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1334                           unsigned int size)
1335 {
1336         return -ENOTSUPP;
1337 }
1338 #endif
1339 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1340 {
1341         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1342 }
1343
1344 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1345 {
1346         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1347 }
1348
1349 static void omap_hsmmc_set_clock(struct mmc *mmc)
1350 {
1351         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1352         struct hsmmc *mmc_base;
1353         unsigned int dsor = 0;
1354         ulong start;
1355
1356         mmc_base = priv->base_addr;
1357         omap_hsmmc_stop_clock(mmc_base);
1358
1359         /* TODO: Is setting DTO required here? */
1360         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1361                     (ICE_STOP | DTO_15THDTO));
1362
1363         if (mmc->clock != 0) {
1364                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1365                 if (dsor > CLKD_MAX)
1366                         dsor = CLKD_MAX;
1367         } else {
1368                 dsor = CLKD_MAX;
1369         }
1370
1371         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1372                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1373
1374         start = get_timer(0);
1375         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1376                 if (get_timer(0) - start > MAX_RETRY_MS) {
1377                         printf("%s: timedout waiting for ics!\n", __func__);
1378                         return;
1379                 }
1380         }
1381
1382         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1383         mmc->clock = priv->clock;
1384         omap_hsmmc_start_clock(mmc_base);
1385 }
1386
1387 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1388 {
1389         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1390         struct hsmmc *mmc_base;
1391
1392         mmc_base = priv->base_addr;
1393         /* configue bus width */
1394         switch (mmc->bus_width) {
1395         case 8:
1396                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1397                         &mmc_base->con);
1398                 break;
1399
1400         case 4:
1401                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1402                         &mmc_base->con);
1403                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1404                         &mmc_base->hctl);
1405                 break;
1406
1407         case 1:
1408         default:
1409                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1410                         &mmc_base->con);
1411                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1412                         &mmc_base->hctl);
1413                 break;
1414         }
1415
1416         priv->bus_width = mmc->bus_width;
1417 }
1418
1419 #if !CONFIG_IS_ENABLED(DM_MMC)
1420 static int omap_hsmmc_set_ios(struct mmc *mmc)
1421 {
1422         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1423 #else
1424 static int omap_hsmmc_set_ios(struct udevice *dev)
1425 {
1426         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1427         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1428         struct mmc *mmc = upriv->mmc;
1429 #endif
1430         struct hsmmc *mmc_base = priv->base_addr;
1431         int ret = 0;
1432
1433         if (priv->bus_width != mmc->bus_width)
1434                 omap_hsmmc_set_bus_width(mmc);
1435
1436         if (priv->clock != mmc->clock)
1437                 omap_hsmmc_set_clock(mmc);
1438
1439         if (mmc->clk_disable)
1440                 omap_hsmmc_stop_clock(mmc_base);
1441         else
1442                 omap_hsmmc_start_clock(mmc_base);
1443
1444 #if CONFIG_IS_ENABLED(DM_MMC)
1445         if (priv->mode != mmc->selected_mode)
1446                 omap_hsmmc_set_timing(mmc);
1447
1448 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1449         if (priv->signal_voltage != mmc->signal_voltage)
1450                 ret = omap_hsmmc_set_signal_voltage(mmc);
1451 #endif
1452 #endif
1453         return ret;
1454 }
1455
1456 #ifdef OMAP_HSMMC_USE_GPIO
1457 #if CONFIG_IS_ENABLED(DM_MMC)
1458 static int omap_hsmmc_getcd(struct udevice *dev)
1459 {
1460         int value = -1;
1461 #if CONFIG_IS_ENABLED(DM_GPIO)
1462         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1463         value = dm_gpio_get_value(&priv->cd_gpio);
1464 #endif
1465         /* if no CD return as 1 */
1466         if (value < 0)
1467                 return 1;
1468
1469         return value;
1470 }
1471
1472 static int omap_hsmmc_getwp(struct udevice *dev)
1473 {
1474         int value = 0;
1475 #if CONFIG_IS_ENABLED(DM_GPIO)
1476         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1477         value = dm_gpio_get_value(&priv->wp_gpio);
1478 #endif
1479         /* if no WP return as 0 */
1480         if (value < 0)
1481                 return 0;
1482         return value;
1483 }
1484 #else
1485 static int omap_hsmmc_getcd(struct mmc *mmc)
1486 {
1487         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1488         int cd_gpio;
1489
1490         /* if no CD return as 1 */
1491         cd_gpio = priv->cd_gpio;
1492         if (cd_gpio < 0)
1493                 return 1;
1494
1495         /* NOTE: assumes card detect signal is active-low */
1496         return !gpio_get_value(cd_gpio);
1497 }
1498
1499 static int omap_hsmmc_getwp(struct mmc *mmc)
1500 {
1501         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1502         int wp_gpio;
1503
1504         /* if no WP return as 0 */
1505         wp_gpio = priv->wp_gpio;
1506         if (wp_gpio < 0)
1507                 return 0;
1508
1509         /* NOTE: assumes write protect signal is active-high */
1510         return gpio_get_value(wp_gpio);
1511 }
1512 #endif
1513 #endif
1514
1515 #if CONFIG_IS_ENABLED(DM_MMC)
1516 static const struct dm_mmc_ops omap_hsmmc_ops = {
1517         .send_cmd       = omap_hsmmc_send_cmd,
1518         .set_ios        = omap_hsmmc_set_ios,
1519 #ifdef OMAP_HSMMC_USE_GPIO
1520         .get_cd         = omap_hsmmc_getcd,
1521         .get_wp         = omap_hsmmc_getwp,
1522 #endif
1523 #ifdef MMC_SUPPORTS_TUNING
1524         .execute_tuning = omap_hsmmc_execute_tuning,
1525 #endif
1526         .send_init_stream       = omap_hsmmc_send_init_stream,
1527 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1528         .wait_dat0      = omap_hsmmc_wait_dat0,
1529 #endif
1530 };
1531 #else
1532 static const struct mmc_ops omap_hsmmc_ops = {
1533         .send_cmd       = omap_hsmmc_send_cmd,
1534         .set_ios        = omap_hsmmc_set_ios,
1535         .init           = omap_hsmmc_init_setup,
1536 #ifdef OMAP_HSMMC_USE_GPIO
1537         .getcd          = omap_hsmmc_getcd,
1538         .getwp          = omap_hsmmc_getwp,
1539 #endif
1540 };
1541 #endif
1542
1543 #if !CONFIG_IS_ENABLED(DM_MMC)
1544 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1545                 int wp_gpio)
1546 {
1547         struct mmc *mmc;
1548         struct omap_hsmmc_data *priv;
1549         struct mmc_config *cfg;
1550         uint host_caps_val;
1551
1552         priv = calloc(1, sizeof(*priv));
1553         if (priv == NULL)
1554                 return -1;
1555
1556         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1557
1558         switch (dev_index) {
1559         case 0:
1560                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1561                 break;
1562 #ifdef OMAP_HSMMC2_BASE
1563         case 1:
1564                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1565 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1566         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1567         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1568                 defined(CONFIG_HSMMC2_8BIT)
1569                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1570                 host_caps_val |= MMC_MODE_8BIT;
1571 #endif
1572                 break;
1573 #endif
1574 #ifdef OMAP_HSMMC3_BASE
1575         case 2:
1576                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1577 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1578                 /* Enable 8-bit interface for eMMC on DRA7XX */
1579                 host_caps_val |= MMC_MODE_8BIT;
1580 #endif
1581                 break;
1582 #endif
1583         default:
1584                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1585                 return 1;
1586         }
1587 #ifdef OMAP_HSMMC_USE_GPIO
1588         /* on error gpio values are set to -1, which is what we want */
1589         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1590         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1591 #endif
1592
1593         cfg = &priv->cfg;
1594
1595         cfg->name = "OMAP SD/MMC";
1596         cfg->ops = &omap_hsmmc_ops;
1597
1598         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1599         cfg->host_caps = host_caps_val & ~host_caps_mask;
1600
1601         cfg->f_min = 400000;
1602
1603         if (f_max != 0)
1604                 cfg->f_max = f_max;
1605         else {
1606                 if (cfg->host_caps & MMC_MODE_HS) {
1607                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1608                                 cfg->f_max = 52000000;
1609                         else
1610                                 cfg->f_max = 26000000;
1611                 } else
1612                         cfg->f_max = 20000000;
1613         }
1614
1615         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1616
1617 #if defined(CONFIG_OMAP34XX)
1618         /*
1619          * Silicon revs 2.1 and older do not support multiblock transfers.
1620          */
1621         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1622                 cfg->b_max = 1;
1623 #endif
1624
1625         mmc = mmc_create(cfg, priv);
1626         if (mmc == NULL)
1627                 return -1;
1628
1629         return 0;
1630 }
1631 #else
1632
1633 #ifdef CONFIG_IODELAY_RECALIBRATION
1634 static struct pad_conf_entry *
1635 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1636 {
1637         int index = 0;
1638         struct pad_conf_entry *padconf;
1639
1640         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1641         if (!padconf) {
1642                 debug("failed to allocate memory\n");
1643                 return 0;
1644         }
1645
1646         while (index < count) {
1647                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1648                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1649                 index++;
1650         }
1651
1652         return padconf;
1653 }
1654
1655 static struct iodelay_cfg_entry *
1656 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1657 {
1658         int index = 0;
1659         struct iodelay_cfg_entry *iodelay;
1660
1661         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1662         if (!iodelay) {
1663                 debug("failed to allocate memory\n");
1664                 return 0;
1665         }
1666
1667         while (index < count) {
1668                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1669                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1670                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1671                 index++;
1672         }
1673
1674         return iodelay;
1675 }
1676
1677 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1678                                                    const char *name, int *len)
1679 {
1680         const void *fdt = gd->fdt_blob;
1681         int offset;
1682         const fdt32_t *pinctrl;
1683
1684         offset = fdt_node_offset_by_phandle(fdt, phandle);
1685         if (offset < 0) {
1686                 debug("failed to get pinctrl node %s.\n",
1687                       fdt_strerror(offset));
1688                 return 0;
1689         }
1690
1691         pinctrl = fdt_getprop(fdt, offset, name, len);
1692         if (!pinctrl) {
1693                 debug("failed to get property %s\n", name);
1694                 return 0;
1695         }
1696
1697         return pinctrl;
1698 }
1699
1700 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1701                                                 char *prop_name)
1702 {
1703         const void *fdt = gd->fdt_blob;
1704         const __be32 *phandle;
1705         int node = dev_of_offset(mmc->dev);
1706
1707         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1708         if (!phandle) {
1709                 debug("failed to get property %s\n", prop_name);
1710                 return 0;
1711         }
1712
1713         return fdt32_to_cpu(*phandle);
1714 }
1715
1716 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1717                                                char *prop_name)
1718 {
1719         const void *fdt = gd->fdt_blob;
1720         const __be32 *phandle;
1721         int len;
1722         int count;
1723         int node = dev_of_offset(mmc->dev);
1724
1725         phandle = fdt_getprop(fdt, node, prop_name, &len);
1726         if (!phandle) {
1727                 debug("failed to get property %s\n", prop_name);
1728                 return 0;
1729         }
1730
1731         /* No manual mode iodelay values if count < 2 */
1732         count = len / sizeof(*phandle);
1733         if (count < 2)
1734                 return 0;
1735
1736         return fdt32_to_cpu(*(phandle + 1));
1737 }
1738
1739 static struct pad_conf_entry *
1740 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1741 {
1742         int len;
1743         int count;
1744         struct pad_conf_entry *padconf;
1745         u32 phandle;
1746         const fdt32_t *pinctrl;
1747
1748         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1749         if (!phandle)
1750                 return ERR_PTR(-EINVAL);
1751
1752         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1753                                                &len);
1754         if (!pinctrl)
1755                 return ERR_PTR(-EINVAL);
1756
1757         count = (len / sizeof(*pinctrl)) / 2;
1758         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1759         if (!padconf)
1760                 return ERR_PTR(-EINVAL);
1761
1762         *npads = count;
1763
1764         return padconf;
1765 }
1766
1767 static struct iodelay_cfg_entry *
1768 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1769 {
1770         int len;
1771         int count;
1772         struct iodelay_cfg_entry *iodelay;
1773         u32 phandle;
1774         const fdt32_t *pinctrl;
1775
1776         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1777         /* Not all modes have manual mode iodelay values. So its not fatal */
1778         if (!phandle)
1779                 return 0;
1780
1781         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1782                                                &len);
1783         if (!pinctrl)
1784                 return ERR_PTR(-EINVAL);
1785
1786         count = (len / sizeof(*pinctrl)) / 3;
1787         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1788         if (!iodelay)
1789                 return ERR_PTR(-EINVAL);
1790
1791         *niodelay = count;
1792
1793         return iodelay;
1794 }
1795
1796 static struct omap_hsmmc_pinctrl_state *
1797 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1798 {
1799         int index;
1800         int npads = 0;
1801         int niodelays = 0;
1802         const void *fdt = gd->fdt_blob;
1803         int node = dev_of_offset(mmc->dev);
1804         char prop_name[11];
1805         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1806
1807         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1808                          malloc(sizeof(*pinctrl_state));
1809         if (!pinctrl_state) {
1810                 debug("failed to allocate memory\n");
1811                 return 0;
1812         }
1813
1814         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1815         if (index < 0) {
1816                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1817                 goto err_pinctrl_state;
1818         }
1819
1820         sprintf(prop_name, "pinctrl-%d", index);
1821
1822         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1823                                                          &npads);
1824         if (IS_ERR(pinctrl_state->padconf))
1825                 goto err_pinctrl_state;
1826         pinctrl_state->npads = npads;
1827
1828         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1829                                                         &niodelays);
1830         if (IS_ERR(pinctrl_state->iodelay))
1831                 goto err_padconf;
1832         pinctrl_state->niodelays = niodelays;
1833
1834         return pinctrl_state;
1835
1836 err_padconf:
1837         kfree(pinctrl_state->padconf);
1838
1839 err_pinctrl_state:
1840         kfree(pinctrl_state);
1841         return 0;
1842 }
1843
1844 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1845         do {                                                            \
1846                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1847                 char str[20];                                           \
1848                 if (!(cfg->host_caps & capmask))                        \
1849                         break;                                          \
1850                                                                         \
1851                 if (priv->hw_rev) {                                     \
1852                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1853                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1854                 }                                                       \
1855                                                                         \
1856                 if (!s)                                                 \
1857                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1858                                                                         \
1859                 if (!s && !optional) {                                  \
1860                         debug("%s: no pinctrl for %s\n",                \
1861                               mmc->dev->name, #mode);                   \
1862                         cfg->host_caps &= ~(capmask);                   \
1863                 } else {                                                \
1864                         priv->mode##_pinctrl_state = s;                 \
1865                 }                                                       \
1866         } while (0)
1867
1868 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1869 {
1870         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1871         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1872         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1873
1874         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1875                 return 0;
1876
1877         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1878         if (!default_pinctrl) {
1879                 printf("no pinctrl state for default mode\n");
1880                 return -EINVAL;
1881         }
1882
1883         priv->default_pinctrl_state = default_pinctrl;
1884
1885         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1886         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1887         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1888         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1889         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1890
1891         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1892         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1893         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1894
1895         return 0;
1896 }
1897 #endif
1898
1899 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1900 #ifdef CONFIG_OMAP54XX
1901 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1902 {
1903         return NULL;
1904 }
1905 #endif
1906
1907 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1908 {
1909         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1910         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1911
1912         struct mmc_config *cfg = &plat->cfg;
1913 #ifdef CONFIG_OMAP54XX
1914         const struct mmc_platform_fixups *fixups;
1915 #endif
1916         const void *fdt = gd->fdt_blob;
1917         int node = dev_of_offset(dev);
1918         int ret;
1919
1920         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1921                                       sizeof(struct hsmmc *),
1922                                       MAP_NOCACHE);
1923
1924         ret = mmc_of_parse(dev, cfg);
1925         if (ret < 0)
1926                 return ret;
1927
1928         if (!cfg->f_max)
1929                 cfg->f_max = 52000000;
1930         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1931         cfg->f_min = 400000;
1932         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1933         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1934         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1935                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1936         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1937                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1938         if (of_data)
1939                 plat->controller_flags |= of_data->controller_flags;
1940
1941 #ifdef CONFIG_OMAP54XX
1942         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1943         if (fixups) {
1944                 plat->hw_rev = fixups->hw_rev;
1945                 cfg->host_caps &= ~fixups->unsupported_caps;
1946                 cfg->f_max = fixups->max_freq;
1947         }
1948 #endif
1949
1950         return 0;
1951 }
1952 #endif
1953
1954 #ifdef CONFIG_BLK
1955
1956 static int omap_hsmmc_bind(struct udevice *dev)
1957 {
1958         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1959         plat->mmc = calloc(1, sizeof(struct mmc));
1960         return mmc_bind(dev, plat->mmc, &plat->cfg);
1961 }
1962 #endif
1963 static int omap_hsmmc_probe(struct udevice *dev)
1964 {
1965         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1966         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1967         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1968         struct mmc_config *cfg = &plat->cfg;
1969         struct mmc *mmc;
1970 #ifdef CONFIG_IODELAY_RECALIBRATION
1971         int ret;
1972 #endif
1973
1974         cfg->name = "OMAP SD/MMC";
1975         priv->base_addr = plat->base_addr;
1976         priv->controller_flags = plat->controller_flags;
1977         priv->hw_rev = plat->hw_rev;
1978
1979 #ifdef CONFIG_BLK
1980         mmc = plat->mmc;
1981 #else
1982         mmc = mmc_create(cfg, priv);
1983         if (mmc == NULL)
1984                 return -1;
1985 #endif
1986 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1987         device_get_supply_regulator(dev, "pbias-supply",
1988                                     &priv->pbias_supply);
1989 #endif
1990 #if defined(OMAP_HSMMC_USE_GPIO)
1991 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1992         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1993         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1994 #endif
1995 #endif
1996
1997         mmc->dev = dev;
1998         upriv->mmc = mmc;
1999
2000 #ifdef CONFIG_IODELAY_RECALIBRATION
2001         ret = omap_hsmmc_get_pinctrl_state(mmc);
2002         /*
2003          * disable high speed modes for the platforms that require IO delay
2004          * and for which we don't have this information
2005          */
2006         if ((ret < 0) &&
2007             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2008                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2009                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2010                                     UHS_CAPS);
2011         }
2012 #endif
2013
2014         return omap_hsmmc_init_setup(mmc);
2015 }
2016
2017 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2018
2019 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2020         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2021 };
2022
2023 static const struct udevice_id omap_hsmmc_ids[] = {
2024         { .compatible = "ti,omap3-hsmmc" },
2025         { .compatible = "ti,omap4-hsmmc" },
2026         { .compatible = "ti,am33xx-hsmmc" },
2027         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2028         { }
2029 };
2030 #endif
2031
2032 U_BOOT_DRIVER(omap_hsmmc) = {
2033         .name   = "omap_hsmmc",
2034         .id     = UCLASS_MMC,
2035 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2036         .of_match = omap_hsmmc_ids,
2037         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2038         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2039 #endif
2040 #ifdef CONFIG_BLK
2041         .bind = omap_hsmmc_bind,
2042 #endif
2043         .ops = &omap_hsmmc_ops,
2044         .probe  = omap_hsmmc_probe,
2045         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2046 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2047         .flags  = DM_FLAG_PRE_RELOC,
2048 #endif
2049 };
2050 #endif