drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <cpu_func.h>
  28 #include <malloc.h>
  29 #include <memalign.h>
  30 #include <mmc.h>
  31 #include <part.h>
  32 #include <i2c.h>
  33 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  34 #include <palmas.h>
  35 #endif
  36 #include <asm/cache.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/mmc_host_def.h>
  39 #ifdef CONFIG_OMAP54XX
  40 #include <asm/arch/mux_dra7xx.h>
  41 #include <asm/arch/dra7xx_iodelay.h>
  42 #endif
  43 #if !defined(CONFIG_SOC_KEYSTONE)
  44 #include <asm/gpio.h>
  45 #include <asm/arch/sys_proto.h>
  46 #endif
  47 #ifdef CONFIG_MMC_OMAP36XX_PINS
  48 #include <asm/arch/mux.h>
  49 #endif
  50 #include <dm.h>
  51 #include <dm/devres.h>
  52 #include <linux/err.h>
  53 #include <power/regulator.h>
  54 #include <thermal.h>
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  59 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  60         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  61 #define OMAP_HSMMC_USE_GPIO
  62 #else
  63 #undef OMAP_HSMMC_USE_GPIO
  64 #endif
  65
  66 /* common definitions for all OMAPs */
  67 #define SYSCTL_SRC      (1 << 25)
  68 #define SYSCTL_SRD      (1 << 26)
  69
  70 #ifdef CONFIG_IODELAY_RECALIBRATION
  71 struct omap_hsmmc_pinctrl_state {
  72         struct pad_conf_entry *padconf;
  73         int npads;
  74         struct iodelay_cfg_entry *iodelay;
  75         int niodelays;
  76 };
  77 #endif
  78
  79 struct omap_hsmmc_data {
  80         struct hsmmc *base_addr;
  81 #if !CONFIG_IS_ENABLED(DM_MMC)
  82         struct mmc_config cfg;
  83 #endif
  84         uint bus_width;
  85         uint clock;
  86         ushort last_cmd;
  87 #ifdef OMAP_HSMMC_USE_GPIO
  88 #if CONFIG_IS_ENABLED(DM_MMC)
  89         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  90         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  91 #else
  92         int cd_gpio;
  93         int wp_gpio;
  94 #endif
  95 #endif
  96 #if CONFIG_IS_ENABLED(DM_MMC)
  97         enum bus_mode mode;
  98 #endif
  99         u8 controller_flags;
 100 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 101         struct omap_hsmmc_adma_desc *adma_desc_table;
 102         uint desc_slot;
 103 #endif
 104         const char *hw_rev;
 105         struct udevice *pbias_supply;
 106         uint signal_voltage;
 107 #ifdef CONFIG_IODELAY_RECALIBRATION
 108         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 113         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 114         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 115         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 116         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 117 #endif
 118 };
 119
 120 struct omap_mmc_of_data {
 121         u8 controller_flags;
 122 };
 123
 124 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 125 struct omap_hsmmc_adma_desc {
 126         u8 attr;
 127         u8 reserved;
 128         u16 len;
 129         u32 addr;
 130 };
 131
 132 #define ADMA_MAX_LEN    63488
 133
 134 /* Decriptor table defines */
 135 #define ADMA_DESC_ATTR_VALID            BIT(0)
 136 #define ADMA_DESC_ATTR_END              BIT(1)
 137 #define ADMA_DESC_ATTR_INT              BIT(2)
 138 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 139 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 140
 141 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 142 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 143 #endif
 144
 145 /* If we fail after 1 second wait, something is really bad */
 146 #define MAX_RETRY_MS    1000
 147 #define MMC_TIMEOUT_MS  20
 148
 149 /* DMA transfers can take a long time if a lot a data is transferred.
 150  * The timeout must take in account the amount of data. Let's assume
 151  * that the time will never exceed 333 ms per MB (in other word we assume
 152  * that the bandwidth is always above 3MB/s).
 153  */
 154 #define DMA_TIMEOUT_PER_MB      333
 155 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 156 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 157 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 158 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 159
 160 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 161 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 162                         unsigned int siz);
 163 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 164 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 165 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 166
 167 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 168 {
 169 #if CONFIG_IS_ENABLED(DM_MMC)
 170         return dev_get_priv(mmc->dev);
 171 #else
 172         return (struct omap_hsmmc_data *)mmc->priv;
 173 #endif
 174 }
 175 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 176 {
 177 #if CONFIG_IS_ENABLED(DM_MMC)
 178         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 179         return &plat->cfg;
 180 #else
 181         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 182 #endif
 183 }
 184
 185 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 186 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 187 {
 188         int ret;
 189
 190 #if !CONFIG_IS_ENABLED(DM_GPIO)
 191         if (!gpio_is_valid(gpio))
 192                 return -1;
 193 #endif
 194         ret = gpio_request(gpio, label);
 195         if (ret)
 196                 return ret;
 197
 198         ret = gpio_direction_input(gpio);
 199         if (ret)
 200                 return ret;
 201
 202         return gpio;
 203 }
 204 #endif
 205
 206 static unsigned char mmc_board_init(struct mmc *mmc)
 207 {
 208 #if defined(CONFIG_OMAP34XX)
 209         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 210         t2_t *t2_base = (t2_t *)T2_BASE;
 211         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 212         u32 pbias_lite;
 213 #ifdef CONFIG_MMC_OMAP36XX_PINS
 214         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 215 #endif
 216
 217         pbias_lite = readl(&t2_base->pbias_lite);
 218         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 219 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 220         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 221         pbias_lite &= ~PBIASLITEVMODE0;
 222 #endif
 223 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 224         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 225         pbias_lite &= ~PBIASLITEVMODE1;
 226 #endif
 227 #ifdef CONFIG_MMC_OMAP36XX_PINS
 228         if (get_cpu_family() == CPU_OMAP36XX) {
 229                 /* Disable extended drain IO before changing PBIAS */
 230                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 231                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 232         }
 233 #endif
 234         writel(pbias_lite, &t2_base->pbias_lite);
 235
 236         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 237                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 238                 &t2_base->pbias_lite);
 239
 240 #ifdef CONFIG_MMC_OMAP36XX_PINS
 241         if (get_cpu_family() == CPU_OMAP36XX)
 242                 /* Enable extended drain IO after changing PBIAS */
 243                 writel(wkup_ctrl |
 244                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 245                                 OMAP34XX_CTRL_WKUP_CTRL);
 246 #endif
 247         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 248                 &t2_base->devconf0);
 249
 250         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 251                 &t2_base->devconf1);
 252
 253         /* Change from default of 52MHz to 26MHz if necessary */
 254         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 255                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 256                         &t2_base->ctl_prog_io1);
 257
 258         writel(readl(&prcm_base->fclken1_core) |
 259                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 260                 &prcm_base->fclken1_core);
 261
 262         writel(readl(&prcm_base->iclken1_core) |
 263                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 264                 &prcm_base->iclken1_core);
 265 #endif
 266
 267 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 268         !CONFIG_IS_ENABLED(DM_REGULATOR)
 269         /* PBIAS config needed for MMC1 only */
 270         if (mmc_get_blk_desc(mmc)->devnum == 0)
 271                 vmmc_pbias_config(LDO_VOLT_3V3);
 272 #endif
 273
 274         return 0;
 275 }
 276
 277 void mmc_init_stream(struct hsmmc *mmc_base)
 278 {
 279         ulong start;
 280
 281         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 282
 283         writel(MMC_CMD0, &mmc_base->cmd);
 284         start = get_timer(0);
 285         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 286                 if (get_timer(0) - start > MAX_RETRY_MS) {
 287                         printf("%s: timedout waiting for cc!\n", __func__);
 288                         return;
 289                 }
 290         }
 291         writel(CC_MASK, &mmc_base->stat)
 292                 ;
 293         writel(MMC_CMD0, &mmc_base->cmd)
 294                 ;
 295         start = get_timer(0);
 296         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 297                 if (get_timer(0) - start > MAX_RETRY_MS) {
 298                         printf("%s: timedout waiting for cc2!\n", __func__);
 299                         return;
 300                 }
 301         }
 302         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 303 }
 304
 305 #if CONFIG_IS_ENABLED(DM_MMC)
 306 #ifdef CONFIG_IODELAY_RECALIBRATION
 307 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 308 {
 309         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 310         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 311
 312         switch (priv->mode) {
 313         case MMC_HS_200:
 314                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 315                 break;
 316         case UHS_SDR104:
 317                 pinctrl_state = priv->sdr104_pinctrl_state;
 318                 break;
 319         case UHS_SDR50:
 320                 pinctrl_state = priv->sdr50_pinctrl_state;
 321                 break;
 322         case UHS_DDR50:
 323                 pinctrl_state = priv->ddr50_pinctrl_state;
 324                 break;
 325         case UHS_SDR25:
 326                 pinctrl_state = priv->sdr25_pinctrl_state;
 327                 break;
 328         case UHS_SDR12:
 329                 pinctrl_state = priv->sdr12_pinctrl_state;
 330                 break;
 331         case SD_HS:
 332         case MMC_HS:
 333         case MMC_HS_52:
 334                 pinctrl_state = priv->hs_pinctrl_state;
 335                 break;
 336         case MMC_DDR_52:
 337                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 338         default:
 339                 pinctrl_state = priv->default_pinctrl_state;
 340                 break;
 341         }
 342
 343         if (!pinctrl_state)
 344                 pinctrl_state = priv->default_pinctrl_state;
 345
 346         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 347                 if (pinctrl_state->iodelay)
 348                         late_recalibrate_iodelay(pinctrl_state->padconf,
 349                                                  pinctrl_state->npads,
 350                                                  pinctrl_state->iodelay,
 351                                                  pinctrl_state->niodelays);
 352                 else
 353                         do_set_mux32((*ctrl)->control_padconf_core_base,
 354                                      pinctrl_state->padconf,
 355                                      pinctrl_state->npads);
 356         }
 357 }
 358 #endif
 359 static void omap_hsmmc_set_timing(struct mmc *mmc)
 360 {
 361         u32 val;
 362         struct hsmmc *mmc_base;
 363         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 364
 365         mmc_base = priv->base_addr;
 366
 367         omap_hsmmc_stop_clock(mmc_base);
 368         val = readl(&mmc_base->ac12);
 369         val &= ~AC12_UHSMC_MASK;
 370         priv->mode = mmc->selected_mode;
 371
 372         if (mmc_is_mode_ddr(priv->mode))
 373                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 374         else
 375                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 376
 377         switch (priv->mode) {
 378         case MMC_HS_200:
 379         case UHS_SDR104:
 380                 val |= AC12_UHSMC_SDR104;
 381                 break;
 382         case UHS_SDR50:
 383                 val |= AC12_UHSMC_SDR50;
 384                 break;
 385         case MMC_DDR_52:
 386         case UHS_DDR50:
 387                 val |= AC12_UHSMC_DDR50;
 388                 break;
 389         case SD_HS:
 390         case MMC_HS_52:
 391         case UHS_SDR25:
 392                 val |= AC12_UHSMC_SDR25;
 393                 break;
 394         case MMC_LEGACY:
 395         case MMC_HS:
 396         case UHS_SDR12:
 397                 val |= AC12_UHSMC_SDR12;
 398                 break;
 399         default:
 400                 val |= AC12_UHSMC_RES;
 401                 break;
 402         }
 403         writel(val, &mmc_base->ac12);
 404
 405 #ifdef CONFIG_IODELAY_RECALIBRATION
 406         omap_hsmmc_io_recalibrate(mmc);
 407 #endif
 408         omap_hsmmc_start_clock(mmc_base);
 409 }
 410
 411 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 412 {
 413         struct hsmmc *mmc_base;
 414         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 415         u32 hctl, ac12;
 416
 417         mmc_base = priv->base_addr;
 418
 419         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 420         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 421
 422         switch (signal_voltage) {
 423         case MMC_SIGNAL_VOLTAGE_330:
 424                 hctl |= SDVS_3V3;
 425                 break;
 426         case MMC_SIGNAL_VOLTAGE_180:
 427                 hctl |= SDVS_1V8;
 428                 ac12 |= AC12_V1V8_SIGEN;
 429                 break;
 430         }
 431
 432         writel(hctl, &mmc_base->hctl);
 433         writel(ac12, &mmc_base->ac12);
 434 }
 435
 436 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 437 {
 438         int ret = -ETIMEDOUT;
 439         u32 con;
 440         bool dat0_high;
 441         bool target_dat0_high = !!state;
 442         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 443         struct hsmmc *mmc_base = priv->base_addr;
 444
 445         con = readl(&mmc_base->con);
 446         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 447
 448         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 449         while (timeout_us--) {
 450                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 451                 if (dat0_high == target_dat0_high) {
 452                         ret = 0;
 453                         break;
 454                 }
 455                 udelay(10);
 456         }
 457         writel(con, &mmc_base->con);
 458
 459         return ret;
 460 }
 461
 462 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 463 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 464 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 465 {
 466         int ret = 0;
 467         int uV = mV * 1000;
 468
 469         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 470
 471         if (!mmc->vqmmc_supply)
 472                 return 0;
 473
 474         /* Disable PBIAS */
 475         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 476         if (ret)
 477                 return ret;
 478
 479         /* Turn off IO voltage */
 480         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 481         if (ret)
 482                 return ret;
 483         /* Program a new IO voltage value */
 484         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 485         if (ret)
 486                 return ret;
 487         /* Turn on IO voltage */
 488         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 489         if (ret)
 490                 return ret;
 491
 492         /* Program PBIAS voltage*/
 493         ret = regulator_set_value(priv->pbias_supply, uV);
 494         if (ret && ret != -ENOSYS)
 495                 return ret;
 496         /* Enable PBIAS */
 497         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 498         if (ret)
 499                 return ret;
 500
 501         return 0;
 502 }
 503 #endif
 504
 505 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 506 {
 507         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 508         struct hsmmc *mmc_base = priv->base_addr;
 509         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 510         u32 capa_mask;
 511         __maybe_unused u8 palmas_ldo_volt;
 512         u32 val;
 513
 514         if (mv < 0)
 515                 return -EINVAL;
 516
 517         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 518                 mv = 3300;
 519                 capa_mask = VS33_3V3SUP;
 520                 palmas_ldo_volt = LDO_VOLT_3V3;
 521         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 522                 capa_mask = VS18_1V8SUP;
 523                 palmas_ldo_volt = LDO_VOLT_1V8;
 524         } else {
 525                 return -EOPNOTSUPP;
 526         }
 527
 528         val = readl(&mmc_base->capa);
 529         if (!(val & capa_mask))
 530                 return -EOPNOTSUPP;
 531
 532         priv->signal_voltage = mmc->signal_voltage;
 533
 534         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 535
 536 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 537         return omap_hsmmc_set_io_regulator(mmc, mv);
 538 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 539         defined(CONFIG_PALMAS_POWER)
 540         if (mmc_get_blk_desc(mmc)->devnum == 0)
 541                 vmmc_pbias_config(palmas_ldo_volt);
 542         return 0;
 543 #else
 544         return 0;
 545 #endif
 546 }
 547 #endif
 548
 549 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 550 {
 551         struct hsmmc *mmc_base;
 552         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 553         u32 val;
 554
 555         mmc_base = priv->base_addr;
 556         val = readl(&mmc_base->capa);
 557
 558         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 559                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 560         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 561                 val |= VS33_3V3SUP;
 562                 val &= ~VS18_1V8SUP;
 563         } else {
 564                 val |= VS18_1V8SUP;
 565                 val &= ~VS33_3V3SUP;
 566         }
 567
 568         writel(val, &mmc_base->capa);
 569
 570         return val;
 571 }
 572
 573 #ifdef MMC_SUPPORTS_TUNING
 574 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 575 {
 576         struct hsmmc *mmc_base;
 577         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 578         u32 val;
 579
 580         mmc_base = priv->base_addr;
 581         val = readl(&mmc_base->ac12);
 582         val &= ~(AC12_SCLK_SEL);
 583         writel(val, &mmc_base->ac12);
 584
 585         val = readl(&mmc_base->dll);
 586         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 587         writel(val, &mmc_base->dll);
 588 }
 589
 590 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 591 {
 592         int i;
 593         struct hsmmc *mmc_base;
 594         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 595         u32 val;
 596
 597         mmc_base = priv->base_addr;
 598         val = readl(&mmc_base->dll);
 599         val |= DLL_FORCE_VALUE;
 600         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 601         val |= (count << DLL_FORCE_SR_C_SHIFT);
 602         writel(val, &mmc_base->dll);
 603
 604         val |= DLL_CALIB;
 605         writel(val, &mmc_base->dll);
 606         for (i = 0; i < 1000; i++) {
 607                 if (readl(&mmc_base->dll) & DLL_CALIB)
 608                         break;
 609         }
 610         val &= ~DLL_CALIB;
 611         writel(val, &mmc_base->dll);
 612 }
 613
 614 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 615 {
 616         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 617         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 618         struct mmc *mmc = upriv->mmc;
 619         struct hsmmc *mmc_base;
 620         u32 val;
 621         u8 cur_match, prev_match = 0;
 622         int ret;
 623         u32 phase_delay = 0;
 624         u32 start_window = 0, max_window = 0;
 625         u32 length = 0, max_len = 0;
 626         bool single_point_failure = false;
 627         struct udevice *thermal_dev;
 628         int temperature;
 629         int i;
 630
 631         mmc_base = priv->base_addr;
 632         val = readl(&mmc_base->capa2);
 633
 634         /* clock tuning is not needed for upto 52MHz */
 635         if (!((mmc->selected_mode == MMC_HS_200) ||
 636               (mmc->selected_mode == UHS_SDR104) ||
 637               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 638                 return 0;
 639
 640         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 641         if (ret) {
 642                 printf("Couldn't get thermal device for tuning\n");
 643                 return ret;
 644         }
 645         ret = thermal_get_temp(thermal_dev, &temperature);
 646         if (ret) {
 647                 printf("Couldn't get temperature for tuning\n");
 648                 return ret;
 649         }
 650         val = readl(&mmc_base->dll);
 651         val |= DLL_SWT;
 652         writel(val, &mmc_base->dll);
 653
 654         /*
 655          * Stage 1: Search for a maximum pass window ignoring any
 656          * any single point failures. If the tuning value ends up
 657          * near it, move away from it in stage 2 below
 658          */
 659         while (phase_delay <= MAX_PHASE_DELAY) {
 660                 omap_hsmmc_set_dll(mmc, phase_delay);
 661
 662                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 663
 664                 if (cur_match) {
 665                         if (prev_match) {
 666                                 length++;
 667                         } else if (single_point_failure) {
 668                                 /* ignore single point failure */
 669                                 length++;
 670                                 single_point_failure = false;
 671                         } else {
 672                                 start_window = phase_delay;
 673                                 length = 1;
 674                         }
 675                 } else {
 676                         single_point_failure = prev_match;
 677                 }
 678
 679                 if (length > max_len) {
 680                         max_window = start_window;
 681                         max_len = length;
 682                 }
 683
 684                 prev_match = cur_match;
 685                 phase_delay += 4;
 686         }
 687
 688         if (!max_len) {
 689                 ret = -EIO;
 690                 goto tuning_error;
 691         }
 692
 693         val = readl(&mmc_base->ac12);
 694         if (!(val & AC12_SCLK_SEL)) {
 695                 ret = -EIO;
 696                 goto tuning_error;
 697         }
 698         /*
 699          * Assign tuning value as a ratio of maximum pass window based
 700          * on temperature
 701          */
 702         if (temperature < -20000)
 703                 phase_delay = min(max_window + 4 * max_len - 24,
 704                                   max_window +
 705                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 706         else if (temperature < 20000)
 707                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 708         else if (temperature < 40000)
 709                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 710         else if (temperature < 70000)
 711                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 712         else if (temperature < 90000)
 713                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 714         else if (temperature < 120000)
 715                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 716         else
 717                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 718
 719         /*
 720          * Stage 2: Search for a single point failure near the chosen tuning
 721          * value in two steps. First in the +3 to +10 range and then in the
 722          * +2 to -10 range. If found, move away from it in the appropriate
 723          * direction by the appropriate amount depending on the temperature.
 724          */
 725         for (i = 3; i <= 10; i++) {
 726                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 727                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 728                         if (temperature < 10000)
 729                                 phase_delay += i + 6;
 730                         else if (temperature < 20000)
 731                                 phase_delay += i - 12;
 732                         else if (temperature < 70000)
 733                                 phase_delay += i - 8;
 734                         else if (temperature < 90000)
 735                                 phase_delay += i - 6;
 736                         else
 737                                 phase_delay += i - 6;
 738
 739                         goto single_failure_found;
 740                 }
 741         }
 742
 743         for (i = 2; i >= -10; i--) {
 744                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 745                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 746                         if (temperature < 10000)
 747                                 phase_delay += i + 12;
 748                         else if (temperature < 20000)
 749                                 phase_delay += i + 8;
 750                         else if (temperature < 70000)
 751                                 phase_delay += i + 8;
 752                         else if (temperature < 90000)
 753                                 phase_delay += i + 10;
 754                         else
 755                                 phase_delay += i + 12;
 756
 757                         goto single_failure_found;
 758                 }
 759         }
 760
 761 single_failure_found:
 762
 763         omap_hsmmc_set_dll(mmc, phase_delay);
 764
 765         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 766         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 767
 768         return 0;
 769
 770 tuning_error:
 771
 772         omap_hsmmc_disable_tuning(mmc);
 773         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 774         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 775
 776         return ret;
 777 }
 778 #endif
 779 #endif
 780
 781 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 782 {
 783         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 784         struct hsmmc *mmc_base = priv->base_addr;
 785         u32 irq_mask = INT_EN_MASK;
 786
 787         /*
 788          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 789          * tuning procedure and DCRC should be disabled. But see occurences
 790          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 791          * interrupts occur along with BRR, so the data is actually in the
 792          * buffer. It has to be debugged why these interrutps occur
 793          */
 794         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 795                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 796
 797         writel(irq_mask, &mmc_base->ie);
 798 }
 799
 800 static int omap_hsmmc_init_setup(struct mmc *mmc)
 801 {
 802         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 803         struct hsmmc *mmc_base;
 804         unsigned int reg_val;
 805         unsigned int dsor;
 806         ulong start;
 807
 808         mmc_base = priv->base_addr;
 809         mmc_board_init(mmc);
 810
 811         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 812                 &mmc_base->sysconfig);
 813         start = get_timer(0);
 814         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 815                 if (get_timer(0) - start > MAX_RETRY_MS) {
 816                         printf("%s: timedout waiting for cc2!\n", __func__);
 817                         return -ETIMEDOUT;
 818                 }
 819         }
 820         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 821         start = get_timer(0);
 822         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 823                 if (get_timer(0) - start > MAX_RETRY_MS) {
 824                         printf("%s: timedout waiting for softresetall!\n",
 825                                 __func__);
 826                         return -ETIMEDOUT;
 827                 }
 828         }
 829 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 830         reg_val = readl(&mmc_base->hl_hwinfo);
 831         if (reg_val & MADMA_EN)
 832                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 833 #endif
 834
 835 #if CONFIG_IS_ENABLED(DM_MMC)
 836         reg_val = omap_hsmmc_set_capabilities(mmc);
 837         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 838                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 839 #else
 840         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 841         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 842                 &mmc_base->capa);
 843 #endif
 844
 845         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 846
 847         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 848                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 849                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 850
 851         dsor = 240;
 852         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 853                 (ICE_STOP | DTO_15THDTO));
 854         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 855                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 856         start = get_timer(0);
 857         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 858                 if (get_timer(0) - start > MAX_RETRY_MS) {
 859                         printf("%s: timedout waiting for ics!\n", __func__);
 860                         return -ETIMEDOUT;
 861                 }
 862         }
 863         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 864
 865         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 866
 867         mmc_enable_irq(mmc, NULL);
 868
 869 #if !CONFIG_IS_ENABLED(DM_MMC)
 870         mmc_init_stream(mmc_base);
 871 #endif
 872
 873         return 0;
 874 }
 875
 876 /*
 877  * MMC controller internal finite state machine reset
 878  *
 879  * Used to reset command or data internal state machines, using respectively
 880  * SRC or SRD bit of SYSCTL register
 881  */
 882 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 883 {
 884         ulong start;
 885
 886         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 887
 888         /*
 889          * CMD(DAT) lines reset procedures are slightly different
 890          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 891          * According to OMAP3 TRM:
 892          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 893          * returns to 0x0.
 894          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 895          * procedure steps must be as follows:
 896          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 897          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 898          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 899          * 3. Wait until the SRC (SRD) bit returns to 0x0
 900          *    (reset procedure is completed).
 901          */
 902 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 903         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 904         if (!(readl(&mmc_base->sysctl) & bit)) {
 905                 start = get_timer(0);
 906                 while (!(readl(&mmc_base->sysctl) & bit)) {
 907                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 908                                 return;
 909                 }
 910         }
 911 #endif
 912         start = get_timer(0);
 913         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 914                 if (get_timer(0) - start > MAX_RETRY_MS) {
 915                         printf("%s: timedout waiting for sysctl %x to clear\n",
 916                                 __func__, bit);
 917                         return;
 918                 }
 919         }
 920 }
 921
 922 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 923 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 924 {
 925         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 926         struct omap_hsmmc_adma_desc *desc;
 927         u8 attr;
 928
 929         desc = &priv->adma_desc_table[priv->desc_slot];
 930
 931         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 932         if (!end)
 933                 priv->desc_slot++;
 934         else
 935                 attr |= ADMA_DESC_ATTR_END;
 936
 937         desc->len = len;
 938         desc->addr = (u32)buf;
 939         desc->reserved = 0;
 940         desc->attr = attr;
 941 }
 942
 943 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 944                                           struct mmc_data *data)
 945 {
 946         uint total_len = data->blocksize * data->blocks;
 947         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 948         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 949         int i = desc_count;
 950         char *buf;
 951
 952         priv->desc_slot = 0;
 953         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 954                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 955                                 sizeof(struct omap_hsmmc_adma_desc));
 956
 957         if (data->flags & MMC_DATA_READ)
 958                 buf = data->dest;
 959         else
 960                 buf = (char *)data->src;
 961
 962         while (--i) {
 963                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 964                 buf += ADMA_MAX_LEN;
 965                 total_len -= ADMA_MAX_LEN;
 966         }
 967
 968         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 969
 970         flush_dcache_range((long)priv->adma_desc_table,
 971                            (long)priv->adma_desc_table +
 972                            ROUND(desc_count *
 973                            sizeof(struct omap_hsmmc_adma_desc),
 974                            ARCH_DMA_MINALIGN));
 975 }
 976
 977 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 978 {
 979         struct hsmmc *mmc_base;
 980         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 981         u32 val;
 982         char *buf;
 983
 984         mmc_base = priv->base_addr;
 985         omap_hsmmc_prepare_adma_table(mmc, data);
 986
 987         if (data->flags & MMC_DATA_READ)
 988                 buf = data->dest;
 989         else
 990                 buf = (char *)data->src;
 991
 992         val = readl(&mmc_base->hctl);
 993         val |= DMA_SELECT;
 994         writel(val, &mmc_base->hctl);
 995
 996         val = readl(&mmc_base->con);
 997         val |= DMA_MASTER;
 998         writel(val, &mmc_base->con);
 999
1000         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1001
1002         flush_dcache_range((u32)buf,
1003                            (u32)buf +
1004                            ROUND(data->blocksize * data->blocks,
1005                                  ARCH_DMA_MINALIGN));
1006 }
1007
1008 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1009 {
1010         struct hsmmc *mmc_base;
1011         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1012         u32 val;
1013
1014         mmc_base = priv->base_addr;
1015
1016         val = readl(&mmc_base->con);
1017         val &= ~DMA_MASTER;
1018         writel(val, &mmc_base->con);
1019
1020         val = readl(&mmc_base->hctl);
1021         val &= ~DMA_SELECT;
1022         writel(val, &mmc_base->hctl);
1023
1024         kfree(priv->adma_desc_table);
1025 }
1026 #else
1027 #define omap_hsmmc_adma_desc
1028 #define omap_hsmmc_prepare_adma_table
1029 #define omap_hsmmc_prepare_data
1030 #define omap_hsmmc_dma_cleanup
1031 #endif
1032
1033 #if !CONFIG_IS_ENABLED(DM_MMC)
1034 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1035                         struct mmc_data *data)
1036 {
1037         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1038 #else
1039 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1040                         struct mmc_data *data)
1041 {
1042         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1043         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1044         struct mmc *mmc = upriv->mmc;
1045 #endif
1046         struct hsmmc *mmc_base;
1047         unsigned int flags, mmc_stat;
1048         ulong start;
1049         priv->last_cmd = cmd->cmdidx;
1050
1051         mmc_base = priv->base_addr;
1052
1053         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1054                 return 0;
1055
1056         start = get_timer(0);
1057         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1058                 if (get_timer(0) - start > MAX_RETRY_MS) {
1059                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1060                                         __func__);
1061                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1062                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1063                         return -ETIMEDOUT;
1064                 }
1065         }
1066         writel(0xFFFFFFFF, &mmc_base->stat);
1067         if (readl(&mmc_base->stat)) {
1068                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1069                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1070         }
1071
1072         /*
1073          * CMDREG
1074          * CMDIDX[13:8] : Command index
1075          * DATAPRNT[5]  : Data Present Select
1076          * ENCMDIDX[4]  : Command Index Check Enable
1077          * ENCMDCRC[3]  : Command CRC Check Enable
1078          * RSPTYP[1:0]
1079          *      00 = No Response
1080          *      01 = Length 136
1081          *      10 = Length 48
1082          *      11 = Length 48 Check busy after response
1083          */
1084         /* Delay added before checking the status of frq change
1085          * retry not supported by mmc.c(core file)
1086          */
1087         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1088                 udelay(50000); /* wait 50 ms */
1089
1090         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1091                 flags = 0;
1092         else if (cmd->resp_type & MMC_RSP_136)
1093                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1094         else if (cmd->resp_type & MMC_RSP_BUSY)
1095                 flags = RSP_TYPE_LGHT48B;
1096         else
1097                 flags = RSP_TYPE_LGHT48;
1098
1099         /* enable default flags */
1100         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1101                         MSBS_SGLEBLK);
1102         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1103
1104         if (cmd->resp_type & MMC_RSP_CRC)
1105                 flags |= CCCE_CHECK;
1106         if (cmd->resp_type & MMC_RSP_OPCODE)
1107                 flags |= CICE_CHECK;
1108
1109         if (data) {
1110                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1111                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1112                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1113                         data->blocksize = 512;
1114                         writel(data->blocksize | (data->blocks << 16),
1115                                                         &mmc_base->blk);
1116                 } else
1117                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1118
1119                 if (data->flags & MMC_DATA_READ)
1120                         flags |= (DP_DATA | DDIR_READ);
1121                 else
1122                         flags |= (DP_DATA | DDIR_WRITE);
1123
1124 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1125                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1126                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1127                         omap_hsmmc_prepare_data(mmc, data);
1128                         flags |= DE_ENABLE;
1129                 }
1130 #endif
1131         }
1132
1133         mmc_enable_irq(mmc, cmd);
1134
1135         writel(cmd->cmdarg, &mmc_base->arg);
1136         udelay(20);             /* To fix "No status update" error on eMMC */
1137         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1138
1139         start = get_timer(0);
1140         do {
1141                 mmc_stat = readl(&mmc_base->stat);
1142                 if (get_timer(start) > MAX_RETRY_MS) {
1143                         printf("%s : timeout: No status update\n", __func__);
1144                         return -ETIMEDOUT;
1145                 }
1146         } while (!mmc_stat);
1147
1148         if ((mmc_stat & IE_CTO) != 0) {
1149                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1150                 return -ETIMEDOUT;
1151         } else if ((mmc_stat & ERRI_MASK) != 0)
1152                 return -1;
1153
1154         if (mmc_stat & CC_MASK) {
1155                 writel(CC_MASK, &mmc_base->stat);
1156                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1157                         if (cmd->resp_type & MMC_RSP_136) {
1158                                 /* response type 2 */
1159                                 cmd->response[3] = readl(&mmc_base->rsp10);
1160                                 cmd->response[2] = readl(&mmc_base->rsp32);
1161                                 cmd->response[1] = readl(&mmc_base->rsp54);
1162                                 cmd->response[0] = readl(&mmc_base->rsp76);
1163                         } else
1164                                 /* response types 1, 1b, 3, 4, 5, 6 */
1165                                 cmd->response[0] = readl(&mmc_base->rsp10);
1166                 }
1167         }
1168
1169 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1170         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1171             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1172                 u32 sz_mb, timeout;
1173
1174                 if (mmc_stat & IE_ADMAE) {
1175                         omap_hsmmc_dma_cleanup(mmc);
1176                         return -EIO;
1177                 }
1178
1179                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1180                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1181                 if (timeout < MAX_RETRY_MS)
1182                         timeout = MAX_RETRY_MS;
1183
1184                 start = get_timer(0);
1185                 do {
1186                         mmc_stat = readl(&mmc_base->stat);
1187                         if (mmc_stat & TC_MASK) {
1188                                 writel(readl(&mmc_base->stat) | TC_MASK,
1189                                        &mmc_base->stat);
1190                                 break;
1191                         }
1192                         if (get_timer(start) > timeout) {
1193                                 printf("%s : DMA timeout: No status update\n",
1194                                        __func__);
1195                                 return -ETIMEDOUT;
1196                         }
1197                 } while (1);
1198
1199                 omap_hsmmc_dma_cleanup(mmc);
1200                 return 0;
1201         }
1202 #endif
1203
1204         if (data && (data->flags & MMC_DATA_READ)) {
1205                 mmc_read_data(mmc_base, data->dest,
1206                                 data->blocksize * data->blocks);
1207         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1208                 mmc_write_data(mmc_base, data->src,
1209                                 data->blocksize * data->blocks);
1210         }
1211         return 0;
1212 }
1213
1214 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1215 {
1216         unsigned int *output_buf = (unsigned int *)buf;
1217         unsigned int mmc_stat;
1218         unsigned int count;
1219
1220         /*
1221          * Start Polled Read
1222          */
1223         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1224         count /= 4;
1225
1226         while (size) {
1227                 ulong start = get_timer(0);
1228                 do {
1229                         mmc_stat = readl(&mmc_base->stat);
1230                         if (get_timer(0) - start > MAX_RETRY_MS) {
1231                                 printf("%s: timedout waiting for status!\n",
1232                                                 __func__);
1233                                 return -ETIMEDOUT;
1234                         }
1235                 } while (mmc_stat == 0);
1236
1237                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1238                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1239
1240                 if ((mmc_stat & ERRI_MASK) != 0)
1241                         return 1;
1242
1243                 if (mmc_stat & BRR_MASK) {
1244                         unsigned int k;
1245
1246                         writel(readl(&mmc_base->stat) | BRR_MASK,
1247                                 &mmc_base->stat);
1248                         for (k = 0; k < count; k++) {
1249                                 *output_buf = readl(&mmc_base->data);
1250                                 output_buf++;
1251                         }
1252                         size -= (count*4);
1253                 }
1254
1255                 if (mmc_stat & BWR_MASK)
1256                         writel(readl(&mmc_base->stat) | BWR_MASK,
1257                                 &mmc_base->stat);
1258
1259                 if (mmc_stat & TC_MASK) {
1260                         writel(readl(&mmc_base->stat) | TC_MASK,
1261                                 &mmc_base->stat);
1262                         break;
1263                 }
1264         }
1265         return 0;
1266 }
1267
1268 #if CONFIG_IS_ENABLED(MMC_WRITE)
1269 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1270                           unsigned int size)
1271 {
1272         unsigned int *input_buf = (unsigned int *)buf;
1273         unsigned int mmc_stat;
1274         unsigned int count;
1275
1276         /*
1277          * Start Polled Write
1278          */
1279         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1280         count /= 4;
1281
1282         while (size) {
1283                 ulong start = get_timer(0);
1284                 do {
1285                         mmc_stat = readl(&mmc_base->stat);
1286                         if (get_timer(0) - start > MAX_RETRY_MS) {
1287                                 printf("%s: timedout waiting for status!\n",
1288                                                 __func__);
1289                                 return -ETIMEDOUT;
1290                         }
1291                 } while (mmc_stat == 0);
1292
1293                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1294                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1295
1296                 if ((mmc_stat & ERRI_MASK) != 0)
1297                         return 1;
1298
1299                 if (mmc_stat & BWR_MASK) {
1300                         unsigned int k;
1301
1302                         writel(readl(&mmc_base->stat) | BWR_MASK,
1303                                         &mmc_base->stat);
1304                         for (k = 0; k < count; k++) {
1305                                 writel(*input_buf, &mmc_base->data);
1306                                 input_buf++;
1307                         }
1308                         size -= (count*4);
1309                 }
1310
1311                 if (mmc_stat & BRR_MASK)
1312                         writel(readl(&mmc_base->stat) | BRR_MASK,
1313                                 &mmc_base->stat);
1314
1315                 if (mmc_stat & TC_MASK) {
1316                         writel(readl(&mmc_base->stat) | TC_MASK,
1317                                 &mmc_base->stat);
1318                         break;
1319                 }
1320         }
1321         return 0;
1322 }
1323 #else
1324 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1325                           unsigned int size)
1326 {
1327         return -ENOTSUPP;
1328 }
1329 #endif
1330 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1331 {
1332         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1333 }
1334
1335 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1336 {
1337         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1338 }
1339
1340 static void omap_hsmmc_set_clock(struct mmc *mmc)
1341 {
1342         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1343         struct hsmmc *mmc_base;
1344         unsigned int dsor = 0;
1345         ulong start;
1346
1347         mmc_base = priv->base_addr;
1348         omap_hsmmc_stop_clock(mmc_base);
1349
1350         /* TODO: Is setting DTO required here? */
1351         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1352                     (ICE_STOP | DTO_15THDTO));
1353
1354         if (mmc->clock != 0) {
1355                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1356                 if (dsor > CLKD_MAX)
1357                         dsor = CLKD_MAX;
1358         } else {
1359                 dsor = CLKD_MAX;
1360         }
1361
1362         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1363                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1364
1365         start = get_timer(0);
1366         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1367                 if (get_timer(0) - start > MAX_RETRY_MS) {
1368                         printf("%s: timedout waiting for ics!\n", __func__);
1369                         return;
1370                 }
1371         }
1372
1373         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1374         mmc->clock = priv->clock;
1375         omap_hsmmc_start_clock(mmc_base);
1376 }
1377
1378 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1379 {
1380         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1381         struct hsmmc *mmc_base;
1382
1383         mmc_base = priv->base_addr;
1384         /* configue bus width */
1385         switch (mmc->bus_width) {
1386         case 8:
1387                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1388                         &mmc_base->con);
1389                 break;
1390
1391         case 4:
1392                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1393                         &mmc_base->con);
1394                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1395                         &mmc_base->hctl);
1396                 break;
1397
1398         case 1:
1399         default:
1400                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1401                         &mmc_base->con);
1402                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1403                         &mmc_base->hctl);
1404                 break;
1405         }
1406
1407         priv->bus_width = mmc->bus_width;
1408 }
1409
1410 #if !CONFIG_IS_ENABLED(DM_MMC)
1411 static int omap_hsmmc_set_ios(struct mmc *mmc)
1412 {
1413         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1414 #else
1415 static int omap_hsmmc_set_ios(struct udevice *dev)
1416 {
1417         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1418         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1419         struct mmc *mmc = upriv->mmc;
1420 #endif
1421         struct hsmmc *mmc_base = priv->base_addr;
1422         int ret = 0;
1423
1424         if (priv->bus_width != mmc->bus_width)
1425                 omap_hsmmc_set_bus_width(mmc);
1426
1427         if (priv->clock != mmc->clock)
1428                 omap_hsmmc_set_clock(mmc);
1429
1430         if (mmc->clk_disable)
1431                 omap_hsmmc_stop_clock(mmc_base);
1432         else
1433                 omap_hsmmc_start_clock(mmc_base);
1434
1435 #if CONFIG_IS_ENABLED(DM_MMC)
1436         if (priv->mode != mmc->selected_mode)
1437                 omap_hsmmc_set_timing(mmc);
1438
1439 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1440         if (priv->signal_voltage != mmc->signal_voltage)
1441                 ret = omap_hsmmc_set_signal_voltage(mmc);
1442 #endif
1443 #endif
1444         return ret;
1445 }
1446
1447 #ifdef OMAP_HSMMC_USE_GPIO
1448 #if CONFIG_IS_ENABLED(DM_MMC)
1449 static int omap_hsmmc_getcd(struct udevice *dev)
1450 {
1451         int value = -1;
1452 #if CONFIG_IS_ENABLED(DM_GPIO)
1453         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1454         value = dm_gpio_get_value(&priv->cd_gpio);
1455 #endif
1456         /* if no CD return as 1 */
1457         if (value < 0)
1458                 return 1;
1459
1460         return value;
1461 }
1462
1463 static int omap_hsmmc_getwp(struct udevice *dev)
1464 {
1465         int value = 0;
1466 #if CONFIG_IS_ENABLED(DM_GPIO)
1467         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1468         value = dm_gpio_get_value(&priv->wp_gpio);
1469 #endif
1470         /* if no WP return as 0 */
1471         if (value < 0)
1472                 return 0;
1473         return value;
1474 }
1475 #else
1476 static int omap_hsmmc_getcd(struct mmc *mmc)
1477 {
1478         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1479         int cd_gpio;
1480
1481         /* if no CD return as 1 */
1482         cd_gpio = priv->cd_gpio;
1483         if (cd_gpio < 0)
1484                 return 1;
1485
1486         /* NOTE: assumes card detect signal is active-low */
1487         return !gpio_get_value(cd_gpio);
1488 }
1489
1490 static int omap_hsmmc_getwp(struct mmc *mmc)
1491 {
1492         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1493         int wp_gpio;
1494
1495         /* if no WP return as 0 */
1496         wp_gpio = priv->wp_gpio;
1497         if (wp_gpio < 0)
1498                 return 0;
1499
1500         /* NOTE: assumes write protect signal is active-high */
1501         return gpio_get_value(wp_gpio);
1502 }
1503 #endif
1504 #endif
1505
1506 #if CONFIG_IS_ENABLED(DM_MMC)
1507 static const struct dm_mmc_ops omap_hsmmc_ops = {
1508         .send_cmd       = omap_hsmmc_send_cmd,
1509         .set_ios        = omap_hsmmc_set_ios,
1510 #ifdef OMAP_HSMMC_USE_GPIO
1511         .get_cd         = omap_hsmmc_getcd,
1512         .get_wp         = omap_hsmmc_getwp,
1513 #endif
1514 #ifdef MMC_SUPPORTS_TUNING
1515         .execute_tuning = omap_hsmmc_execute_tuning,
1516 #endif
1517         .wait_dat0      = omap_hsmmc_wait_dat0,
1518 };
1519 #else
1520 static const struct mmc_ops omap_hsmmc_ops = {
1521         .send_cmd       = omap_hsmmc_send_cmd,
1522         .set_ios        = omap_hsmmc_set_ios,
1523         .init           = omap_hsmmc_init_setup,
1524 #ifdef OMAP_HSMMC_USE_GPIO
1525         .getcd          = omap_hsmmc_getcd,
1526         .getwp          = omap_hsmmc_getwp,
1527 #endif
1528 };
1529 #endif
1530
1531 #if !CONFIG_IS_ENABLED(DM_MMC)
1532 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1533                 int wp_gpio)
1534 {
1535         struct mmc *mmc;
1536         struct omap_hsmmc_data *priv;
1537         struct mmc_config *cfg;
1538         uint host_caps_val;
1539
1540         priv = calloc(1, sizeof(*priv));
1541         if (priv == NULL)
1542                 return -1;
1543
1544         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1545
1546         switch (dev_index) {
1547         case 0:
1548                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1549                 break;
1550 #ifdef OMAP_HSMMC2_BASE
1551         case 1:
1552                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1553 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1554         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1555         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1556                 defined(CONFIG_HSMMC2_8BIT)
1557                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1558                 host_caps_val |= MMC_MODE_8BIT;
1559 #endif
1560                 break;
1561 #endif
1562 #ifdef OMAP_HSMMC3_BASE
1563         case 2:
1564                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1565 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1566                 /* Enable 8-bit interface for eMMC on DRA7XX */
1567                 host_caps_val |= MMC_MODE_8BIT;
1568 #endif
1569                 break;
1570 #endif
1571         default:
1572                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1573                 return 1;
1574         }
1575 #ifdef OMAP_HSMMC_USE_GPIO
1576         /* on error gpio values are set to -1, which is what we want */
1577         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1578         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1579 #endif
1580
1581         cfg = &priv->cfg;
1582
1583         cfg->name = "OMAP SD/MMC";
1584         cfg->ops = &omap_hsmmc_ops;
1585
1586         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1587         cfg->host_caps = host_caps_val & ~host_caps_mask;
1588
1589         cfg->f_min = 400000;
1590
1591         if (f_max != 0)
1592                 cfg->f_max = f_max;
1593         else {
1594                 if (cfg->host_caps & MMC_MODE_HS) {
1595                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1596                                 cfg->f_max = 52000000;
1597                         else
1598                                 cfg->f_max = 26000000;
1599                 } else
1600                         cfg->f_max = 20000000;
1601         }
1602
1603         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1604
1605 #if defined(CONFIG_OMAP34XX)
1606         /*
1607          * Silicon revs 2.1 and older do not support multiblock transfers.
1608          */
1609         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1610                 cfg->b_max = 1;
1611 #endif
1612
1613         mmc = mmc_create(cfg, priv);
1614         if (mmc == NULL)
1615                 return -1;
1616
1617         return 0;
1618 }
1619 #else
1620
1621 #ifdef CONFIG_IODELAY_RECALIBRATION
1622 static struct pad_conf_entry *
1623 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1624 {
1625         int index = 0;
1626         struct pad_conf_entry *padconf;
1627
1628         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1629         if (!padconf) {
1630                 debug("failed to allocate memory\n");
1631                 return 0;
1632         }
1633
1634         while (index < count) {
1635                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1636                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1637                 index++;
1638         }
1639
1640         return padconf;
1641 }
1642
1643 static struct iodelay_cfg_entry *
1644 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1645 {
1646         int index = 0;
1647         struct iodelay_cfg_entry *iodelay;
1648
1649         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1650         if (!iodelay) {
1651                 debug("failed to allocate memory\n");
1652                 return 0;
1653         }
1654
1655         while (index < count) {
1656                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1657                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1658                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1659                 index++;
1660         }
1661
1662         return iodelay;
1663 }
1664
1665 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1666                                                    const char *name, int *len)
1667 {
1668         const void *fdt = gd->fdt_blob;
1669         int offset;
1670         const fdt32_t *pinctrl;
1671
1672         offset = fdt_node_offset_by_phandle(fdt, phandle);
1673         if (offset < 0) {
1674                 debug("failed to get pinctrl node %s.\n",
1675                       fdt_strerror(offset));
1676                 return 0;
1677         }
1678
1679         pinctrl = fdt_getprop(fdt, offset, name, len);
1680         if (!pinctrl) {
1681                 debug("failed to get property %s\n", name);
1682                 return 0;
1683         }
1684
1685         return pinctrl;
1686 }
1687
1688 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1689                                                 char *prop_name)
1690 {
1691         const void *fdt = gd->fdt_blob;
1692         const __be32 *phandle;
1693         int node = dev_of_offset(mmc->dev);
1694
1695         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1696         if (!phandle) {
1697                 debug("failed to get property %s\n", prop_name);
1698                 return 0;
1699         }
1700
1701         return fdt32_to_cpu(*phandle);
1702 }
1703
1704 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1705                                                char *prop_name)
1706 {
1707         const void *fdt = gd->fdt_blob;
1708         const __be32 *phandle;
1709         int len;
1710         int count;
1711         int node = dev_of_offset(mmc->dev);
1712
1713         phandle = fdt_getprop(fdt, node, prop_name, &len);
1714         if (!phandle) {
1715                 debug("failed to get property %s\n", prop_name);
1716                 return 0;
1717         }
1718
1719         /* No manual mode iodelay values if count < 2 */
1720         count = len / sizeof(*phandle);
1721         if (count < 2)
1722                 return 0;
1723
1724         return fdt32_to_cpu(*(phandle + 1));
1725 }
1726
1727 static struct pad_conf_entry *
1728 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1729 {
1730         int len;
1731         int count;
1732         struct pad_conf_entry *padconf;
1733         u32 phandle;
1734         const fdt32_t *pinctrl;
1735
1736         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1737         if (!phandle)
1738                 return ERR_PTR(-EINVAL);
1739
1740         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1741                                                &len);
1742         if (!pinctrl)
1743                 return ERR_PTR(-EINVAL);
1744
1745         count = (len / sizeof(*pinctrl)) / 2;
1746         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1747         if (!padconf)
1748                 return ERR_PTR(-EINVAL);
1749
1750         *npads = count;
1751
1752         return padconf;
1753 }
1754
1755 static struct iodelay_cfg_entry *
1756 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1757 {
1758         int len;
1759         int count;
1760         struct iodelay_cfg_entry *iodelay;
1761         u32 phandle;
1762         const fdt32_t *pinctrl;
1763
1764         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1765         /* Not all modes have manual mode iodelay values. So its not fatal */
1766         if (!phandle)
1767                 return 0;
1768
1769         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1770                                                &len);
1771         if (!pinctrl)
1772                 return ERR_PTR(-EINVAL);
1773
1774         count = (len / sizeof(*pinctrl)) / 3;
1775         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1776         if (!iodelay)
1777                 return ERR_PTR(-EINVAL);
1778
1779         *niodelay = count;
1780
1781         return iodelay;
1782 }
1783
1784 static struct omap_hsmmc_pinctrl_state *
1785 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1786 {
1787         int index;
1788         int npads = 0;
1789         int niodelays = 0;
1790         const void *fdt = gd->fdt_blob;
1791         int node = dev_of_offset(mmc->dev);
1792         char prop_name[11];
1793         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1794
1795         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1796                          malloc(sizeof(*pinctrl_state));
1797         if (!pinctrl_state) {
1798                 debug("failed to allocate memory\n");
1799                 return 0;
1800         }
1801
1802         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1803         if (index < 0) {
1804                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1805                 goto err_pinctrl_state;
1806         }
1807
1808         sprintf(prop_name, "pinctrl-%d", index);
1809
1810         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1811                                                          &npads);
1812         if (IS_ERR(pinctrl_state->padconf))
1813                 goto err_pinctrl_state;
1814         pinctrl_state->npads = npads;
1815
1816         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1817                                                         &niodelays);
1818         if (IS_ERR(pinctrl_state->iodelay))
1819                 goto err_padconf;
1820         pinctrl_state->niodelays = niodelays;
1821
1822         return pinctrl_state;
1823
1824 err_padconf:
1825         kfree(pinctrl_state->padconf);
1826
1827 err_pinctrl_state:
1828         kfree(pinctrl_state);
1829         return 0;
1830 }
1831
1832 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1833         do {                                                            \
1834                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1835                 char str[20];                                           \
1836                 if (!(cfg->host_caps & capmask))                        \
1837                         break;                                          \
1838                                                                         \
1839                 if (priv->hw_rev) {                                     \
1840                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1841                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1842                 }                                                       \
1843                                                                         \
1844                 if (!s)                                                 \
1845                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1846                                                                         \
1847                 if (!s && !optional) {                                  \
1848                         debug("%s: no pinctrl for %s\n",                \
1849                               mmc->dev->name, #mode);                   \
1850                         cfg->host_caps &= ~(capmask);                   \
1851                 } else {                                                \
1852                         priv->mode##_pinctrl_state = s;                 \
1853                 }                                                       \
1854         } while (0)
1855
1856 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1857 {
1858         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1859         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1860         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1861
1862         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1863                 return 0;
1864
1865         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1866         if (!default_pinctrl) {
1867                 printf("no pinctrl state for default mode\n");
1868                 return -EINVAL;
1869         }
1870
1871         priv->default_pinctrl_state = default_pinctrl;
1872
1873         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1874         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1875         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1876         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1877         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1878
1879         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1880         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1881         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1882
1883         return 0;
1884 }
1885 #endif
1886
1887 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1888 #ifdef CONFIG_OMAP54XX
1889 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1890 {
1891         return NULL;
1892 }
1893 #endif
1894
1895 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1896 {
1897         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1898         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1899
1900         struct mmc_config *cfg = &plat->cfg;
1901 #ifdef CONFIG_OMAP54XX
1902         const struct mmc_platform_fixups *fixups;
1903 #endif
1904         const void *fdt = gd->fdt_blob;
1905         int node = dev_of_offset(dev);
1906         int ret;
1907
1908         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1909                                       sizeof(struct hsmmc *),
1910                                       MAP_NOCACHE);
1911
1912         ret = mmc_of_parse(dev, cfg);
1913         if (ret < 0)
1914                 return ret;
1915
1916         if (!cfg->f_max)
1917                 cfg->f_max = 52000000;
1918         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1919         cfg->f_min = 400000;
1920         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1921         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1922         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1923                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1924         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1925                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1926         if (of_data)
1927                 plat->controller_flags |= of_data->controller_flags;
1928
1929 #ifdef CONFIG_OMAP54XX
1930         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1931         if (fixups) {
1932                 plat->hw_rev = fixups->hw_rev;
1933                 cfg->host_caps &= ~fixups->unsupported_caps;
1934                 cfg->f_max = fixups->max_freq;
1935         }
1936 #endif
1937
1938         return 0;
1939 }
1940 #endif
1941
1942 #ifdef CONFIG_BLK
1943
1944 static int omap_hsmmc_bind(struct udevice *dev)
1945 {
1946         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1947         plat->mmc = calloc(1, sizeof(struct mmc));
1948         return mmc_bind(dev, plat->mmc, &plat->cfg);
1949 }
1950 #endif
1951 static int omap_hsmmc_probe(struct udevice *dev)
1952 {
1953         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1954         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1955         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1956         struct mmc_config *cfg = &plat->cfg;
1957         struct mmc *mmc;
1958 #ifdef CONFIG_IODELAY_RECALIBRATION
1959         int ret;
1960 #endif
1961
1962         cfg->name = "OMAP SD/MMC";
1963         priv->base_addr = plat->base_addr;
1964         priv->controller_flags = plat->controller_flags;
1965         priv->hw_rev = plat->hw_rev;
1966
1967 #ifdef CONFIG_BLK
1968         mmc = plat->mmc;
1969 #else
1970         mmc = mmc_create(cfg, priv);
1971         if (mmc == NULL)
1972                 return -1;
1973 #endif
1974 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1975         device_get_supply_regulator(dev, "pbias-supply",
1976                                     &priv->pbias_supply);
1977 #endif
1978 #if defined(OMAP_HSMMC_USE_GPIO)
1979 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1980         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1981         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1982 #endif
1983 #endif
1984
1985         mmc->dev = dev;
1986         upriv->mmc = mmc;
1987
1988 #ifdef CONFIG_IODELAY_RECALIBRATION
1989         ret = omap_hsmmc_get_pinctrl_state(mmc);
1990         /*
1991          * disable high speed modes for the platforms that require IO delay
1992          * and for which we don't have this information
1993          */
1994         if ((ret < 0) &&
1995             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1996                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1997                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1998                                     UHS_CAPS);
1999         }
2000 #endif
2001
2002         return omap_hsmmc_init_setup(mmc);
2003 }
2004
2005 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2006
2007 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2008         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2009 };
2010
2011 static const struct udevice_id omap_hsmmc_ids[] = {
2012         { .compatible = "ti,omap3-hsmmc" },
2013         { .compatible = "ti,omap4-hsmmc" },
2014         { .compatible = "ti,am33xx-hsmmc" },
2015         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2016         { }
2017 };
2018 #endif
2019
2020 U_BOOT_DRIVER(omap_hsmmc) = {
2021         .name   = "omap_hsmmc",
2022         .id     = UCLASS_MMC,
2023 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2024         .of_match = omap_hsmmc_ids,
2025         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2026         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2027 #endif
2028 #ifdef CONFIG_BLK
2029         .bind = omap_hsmmc_bind,
2030 #endif
2031         .ops = &omap_hsmmc_ops,
2032         .probe  = omap_hsmmc_probe,
2033         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2034 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2035         .flags  = DM_FLAG_PRE_RELOC,
2036 #endif
2037 };
2038 #endif