drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <cpu_func.h>
  28 #include <log.h>
  29 #include <malloc.h>
  30 #include <memalign.h>
  31 #include <mmc.h>
  32 #include <part.h>
  33 #include <i2c.h>
  34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  35 #include <palmas.h>
  36 #endif
  37 #include <asm/cache.h>
  38 #include <asm/io.h>
  39 #include <asm/arch/mmc_host_def.h>
  40 #ifdef CONFIG_OMAP54XX
  41 #include <asm/arch/mux_dra7xx.h>
  42 #include <asm/arch/dra7xx_iodelay.h>
  43 #endif
  44 #if !defined(CONFIG_SOC_KEYSTONE)
  45 #include <asm/gpio.h>
  46 #include <asm/arch/sys_proto.h>
  47 #endif
  48 #ifdef CONFIG_MMC_OMAP36XX_PINS
  49 #include <asm/arch/mux.h>
  50 #endif
  51 #include <dm.h>
  52 #include <dm/devres.h>
  53 #include <linux/err.h>
  54 #include <power/regulator.h>
  55 #include <thermal.h>
  56
  57 DECLARE_GLOBAL_DATA_PTR;
  58
  59 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  60 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  61         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  62 #define OMAP_HSMMC_USE_GPIO
  63 #else
  64 #undef OMAP_HSMMC_USE_GPIO
  65 #endif
  66
  67 /* common definitions for all OMAPs */
  68 #define SYSCTL_SRC      (1 << 25)
  69 #define SYSCTL_SRD      (1 << 26)
  70
  71 #ifdef CONFIG_IODELAY_RECALIBRATION
  72 struct omap_hsmmc_pinctrl_state {
  73         struct pad_conf_entry *padconf;
  74         int npads;
  75         struct iodelay_cfg_entry *iodelay;
  76         int niodelays;
  77 };
  78 #endif
  79
  80 struct omap_hsmmc_data {
  81         struct hsmmc *base_addr;
  82 #if !CONFIG_IS_ENABLED(DM_MMC)
  83         struct mmc_config cfg;
  84 #endif
  85         uint bus_width;
  86         uint clock;
  87         ushort last_cmd;
  88 #ifdef OMAP_HSMMC_USE_GPIO
  89 #if CONFIG_IS_ENABLED(DM_MMC)
  90         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  91         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  92 #else
  93         int cd_gpio;
  94         int wp_gpio;
  95 #endif
  96 #endif
  97 #if CONFIG_IS_ENABLED(DM_MMC)
  98         enum bus_mode mode;
  99 #endif
 100         u8 controller_flags;
 101 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 102         struct omap_hsmmc_adma_desc *adma_desc_table;
 103         uint desc_slot;
 104 #endif
 105         const char *hw_rev;
 106         struct udevice *pbias_supply;
 107         uint signal_voltage;
 108 #ifdef CONFIG_IODELAY_RECALIBRATION
 109         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 113         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 114         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 115         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 116         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 117         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 118 #endif
 119 };
 120
 121 struct omap_mmc_of_data {
 122         u8 controller_flags;
 123 };
 124
 125 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 126 struct omap_hsmmc_adma_desc {
 127         u8 attr;
 128         u8 reserved;
 129         u16 len;
 130         u32 addr;
 131 };
 132
 133 #define ADMA_MAX_LEN    63488
 134
 135 /* Decriptor table defines */
 136 #define ADMA_DESC_ATTR_VALID            BIT(0)
 137 #define ADMA_DESC_ATTR_END              BIT(1)
 138 #define ADMA_DESC_ATTR_INT              BIT(2)
 139 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 140 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 141
 142 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 143 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 144 #endif
 145
 146 /* If we fail after 1 second wait, something is really bad */
 147 #define MAX_RETRY_MS    1000
 148 #define MMC_TIMEOUT_MS  20
 149
 150 /* DMA transfers can take a long time if a lot a data is transferred.
 151  * The timeout must take in account the amount of data. Let's assume
 152  * that the time will never exceed 333 ms per MB (in other word we assume
 153  * that the bandwidth is always above 3MB/s).
 154  */
 155 #define DMA_TIMEOUT_PER_MB      333
 156 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 157 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 158 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 159 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 160
 161 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 162 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 163                         unsigned int siz);
 164 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 165 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 166 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 167
 168 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 169 {
 170 #if CONFIG_IS_ENABLED(DM_MMC)
 171         return dev_get_priv(mmc->dev);
 172 #else
 173         return (struct omap_hsmmc_data *)mmc->priv;
 174 #endif
 175 }
 176 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 177 {
 178 #if CONFIG_IS_ENABLED(DM_MMC)
 179         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 180         return &plat->cfg;
 181 #else
 182         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 183 #endif
 184 }
 185
 186 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 187 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 188 {
 189         int ret;
 190
 191 #if !CONFIG_IS_ENABLED(DM_GPIO)
 192         if (!gpio_is_valid(gpio))
 193                 return -1;
 194 #endif
 195         ret = gpio_request(gpio, label);
 196         if (ret)
 197                 return ret;
 198
 199         ret = gpio_direction_input(gpio);
 200         if (ret)
 201                 return ret;
 202
 203         return gpio;
 204 }
 205 #endif
 206
 207 static unsigned char mmc_board_init(struct mmc *mmc)
 208 {
 209 #if defined(CONFIG_OMAP34XX)
 210         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 211         t2_t *t2_base = (t2_t *)T2_BASE;
 212         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 213         u32 pbias_lite;
 214 #ifdef CONFIG_MMC_OMAP36XX_PINS
 215         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 216 #endif
 217
 218         pbias_lite = readl(&t2_base->pbias_lite);
 219         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 220 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 221         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 222         pbias_lite &= ~PBIASLITEVMODE0;
 223 #endif
 224 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 225         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 226         pbias_lite &= ~PBIASLITEVMODE1;
 227 #endif
 228 #ifdef CONFIG_MMC_OMAP36XX_PINS
 229         if (get_cpu_family() == CPU_OMAP36XX) {
 230                 /* Disable extended drain IO before changing PBIAS */
 231                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 232                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 233         }
 234 #endif
 235         writel(pbias_lite, &t2_base->pbias_lite);
 236
 237         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 238                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 239                 &t2_base->pbias_lite);
 240
 241 #ifdef CONFIG_MMC_OMAP36XX_PINS
 242         if (get_cpu_family() == CPU_OMAP36XX)
 243                 /* Enable extended drain IO after changing PBIAS */
 244                 writel(wkup_ctrl |
 245                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 246                                 OMAP34XX_CTRL_WKUP_CTRL);
 247 #endif
 248         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 249                 &t2_base->devconf0);
 250
 251         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 252                 &t2_base->devconf1);
 253
 254         /* Change from default of 52MHz to 26MHz if necessary */
 255         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 256                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 257                         &t2_base->ctl_prog_io1);
 258
 259         writel(readl(&prcm_base->fclken1_core) |
 260                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 261                 &prcm_base->fclken1_core);
 262
 263         writel(readl(&prcm_base->iclken1_core) |
 264                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 265                 &prcm_base->iclken1_core);
 266 #endif
 267
 268 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 269         !CONFIG_IS_ENABLED(DM_REGULATOR)
 270         /* PBIAS config needed for MMC1 only */
 271         if (mmc_get_blk_desc(mmc)->devnum == 0)
 272                 vmmc_pbias_config(LDO_VOLT_3V3);
 273 #endif
 274
 275         return 0;
 276 }
 277
 278 void mmc_init_stream(struct hsmmc *mmc_base)
 279 {
 280         ulong start;
 281
 282         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 283
 284         writel(MMC_CMD0, &mmc_base->cmd);
 285         start = get_timer(0);
 286         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 287                 if (get_timer(0) - start > MAX_RETRY_MS) {
 288                         printf("%s: timedout waiting for cc!\n", __func__);
 289                         return;
 290                 }
 291         }
 292         writel(CC_MASK, &mmc_base->stat)
 293                 ;
 294         writel(MMC_CMD0, &mmc_base->cmd)
 295                 ;
 296         start = get_timer(0);
 297         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 298                 if (get_timer(0) - start > MAX_RETRY_MS) {
 299                         printf("%s: timedout waiting for cc2!\n", __func__);
 300                         return;
 301                 }
 302         }
 303         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 304 }
 305
 306 #if CONFIG_IS_ENABLED(DM_MMC)
 307 #ifdef CONFIG_IODELAY_RECALIBRATION
 308 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 309 {
 310         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 311         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 312
 313         switch (priv->mode) {
 314         case MMC_HS_200:
 315                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 316                 break;
 317         case UHS_SDR104:
 318                 pinctrl_state = priv->sdr104_pinctrl_state;
 319                 break;
 320         case UHS_SDR50:
 321                 pinctrl_state = priv->sdr50_pinctrl_state;
 322                 break;
 323         case UHS_DDR50:
 324                 pinctrl_state = priv->ddr50_pinctrl_state;
 325                 break;
 326         case UHS_SDR25:
 327                 pinctrl_state = priv->sdr25_pinctrl_state;
 328                 break;
 329         case UHS_SDR12:
 330                 pinctrl_state = priv->sdr12_pinctrl_state;
 331                 break;
 332         case SD_HS:
 333         case MMC_HS:
 334         case MMC_HS_52:
 335                 pinctrl_state = priv->hs_pinctrl_state;
 336                 break;
 337         case MMC_DDR_52:
 338                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 339         default:
 340                 pinctrl_state = priv->default_pinctrl_state;
 341                 break;
 342         }
 343
 344         if (!pinctrl_state)
 345                 pinctrl_state = priv->default_pinctrl_state;
 346
 347         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 348                 if (pinctrl_state->iodelay)
 349                         late_recalibrate_iodelay(pinctrl_state->padconf,
 350                                                  pinctrl_state->npads,
 351                                                  pinctrl_state->iodelay,
 352                                                  pinctrl_state->niodelays);
 353                 else
 354                         do_set_mux32((*ctrl)->control_padconf_core_base,
 355                                      pinctrl_state->padconf,
 356                                      pinctrl_state->npads);
 357         }
 358 }
 359 #endif
 360 static void omap_hsmmc_set_timing(struct mmc *mmc)
 361 {
 362         u32 val;
 363         struct hsmmc *mmc_base;
 364         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 365
 366         mmc_base = priv->base_addr;
 367
 368         omap_hsmmc_stop_clock(mmc_base);
 369         val = readl(&mmc_base->ac12);
 370         val &= ~AC12_UHSMC_MASK;
 371         priv->mode = mmc->selected_mode;
 372
 373         if (mmc_is_mode_ddr(priv->mode))
 374                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 375         else
 376                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 377
 378         switch (priv->mode) {
 379         case MMC_HS_200:
 380         case UHS_SDR104:
 381                 val |= AC12_UHSMC_SDR104;
 382                 break;
 383         case UHS_SDR50:
 384                 val |= AC12_UHSMC_SDR50;
 385                 break;
 386         case MMC_DDR_52:
 387         case UHS_DDR50:
 388                 val |= AC12_UHSMC_DDR50;
 389                 break;
 390         case SD_HS:
 391         case MMC_HS_52:
 392         case UHS_SDR25:
 393                 val |= AC12_UHSMC_SDR25;
 394                 break;
 395         case MMC_LEGACY:
 396         case MMC_HS:
 397         case UHS_SDR12:
 398                 val |= AC12_UHSMC_SDR12;
 399                 break;
 400         default:
 401                 val |= AC12_UHSMC_RES;
 402                 break;
 403         }
 404         writel(val, &mmc_base->ac12);
 405
 406 #ifdef CONFIG_IODELAY_RECALIBRATION
 407         omap_hsmmc_io_recalibrate(mmc);
 408 #endif
 409         omap_hsmmc_start_clock(mmc_base);
 410 }
 411
 412 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 413 {
 414         struct hsmmc *mmc_base;
 415         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 416         u32 hctl, ac12;
 417
 418         mmc_base = priv->base_addr;
 419
 420         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 421         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 422
 423         switch (signal_voltage) {
 424         case MMC_SIGNAL_VOLTAGE_330:
 425                 hctl |= SDVS_3V3;
 426                 break;
 427         case MMC_SIGNAL_VOLTAGE_180:
 428                 hctl |= SDVS_1V8;
 429                 ac12 |= AC12_V1V8_SIGEN;
 430                 break;
 431         }
 432
 433         writel(hctl, &mmc_base->hctl);
 434         writel(ac12, &mmc_base->ac12);
 435 }
 436
 437 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 438 {
 439         int ret = -ETIMEDOUT;
 440         u32 con;
 441         bool dat0_high;
 442         bool target_dat0_high = !!state;
 443         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 444         struct hsmmc *mmc_base = priv->base_addr;
 445
 446         con = readl(&mmc_base->con);
 447         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 448
 449         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 450         while (timeout_us--) {
 451                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 452                 if (dat0_high == target_dat0_high) {
 453                         ret = 0;
 454                         break;
 455                 }
 456                 udelay(10);
 457         }
 458         writel(con, &mmc_base->con);
 459
 460         return ret;
 461 }
 462
 463 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 464 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 465 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 466 {
 467         int ret = 0;
 468         int uV = mV * 1000;
 469
 470         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 471
 472         if (!mmc->vqmmc_supply)
 473                 return 0;
 474
 475         /* Disable PBIAS */
 476         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 477         if (ret)
 478                 return ret;
 479
 480         /* Turn off IO voltage */
 481         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 482         if (ret)
 483                 return ret;
 484         /* Program a new IO voltage value */
 485         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 486         if (ret)
 487                 return ret;
 488         /* Turn on IO voltage */
 489         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 490         if (ret)
 491                 return ret;
 492
 493         /* Program PBIAS voltage*/
 494         ret = regulator_set_value(priv->pbias_supply, uV);
 495         if (ret && ret != -ENOSYS)
 496                 return ret;
 497         /* Enable PBIAS */
 498         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 499         if (ret)
 500                 return ret;
 501
 502         return 0;
 503 }
 504 #endif
 505
 506 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 507 {
 508         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 509         struct hsmmc *mmc_base = priv->base_addr;
 510         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 511         u32 capa_mask;
 512         __maybe_unused u8 palmas_ldo_volt;
 513         u32 val;
 514
 515         if (mv < 0)
 516                 return -EINVAL;
 517
 518         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 519                 mv = 3300;
 520                 capa_mask = VS33_3V3SUP;
 521                 palmas_ldo_volt = LDO_VOLT_3V3;
 522         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 523                 capa_mask = VS18_1V8SUP;
 524                 palmas_ldo_volt = LDO_VOLT_1V8;
 525         } else {
 526                 return -EOPNOTSUPP;
 527         }
 528
 529         val = readl(&mmc_base->capa);
 530         if (!(val & capa_mask))
 531                 return -EOPNOTSUPP;
 532
 533         priv->signal_voltage = mmc->signal_voltage;
 534
 535         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 536
 537 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 538         return omap_hsmmc_set_io_regulator(mmc, mv);
 539 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 540         defined(CONFIG_PALMAS_POWER)
 541         if (mmc_get_blk_desc(mmc)->devnum == 0)
 542                 vmmc_pbias_config(palmas_ldo_volt);
 543         return 0;
 544 #else
 545         return 0;
 546 #endif
 547 }
 548 #endif
 549
 550 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 551 {
 552         struct hsmmc *mmc_base;
 553         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 554         u32 val;
 555
 556         mmc_base = priv->base_addr;
 557         val = readl(&mmc_base->capa);
 558
 559         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 560                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 561         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 562                 val |= VS33_3V3SUP;
 563                 val &= ~VS18_1V8SUP;
 564         } else {
 565                 val |= VS18_1V8SUP;
 566                 val &= ~VS33_3V3SUP;
 567         }
 568
 569         writel(val, &mmc_base->capa);
 570
 571         return val;
 572 }
 573
 574 #ifdef MMC_SUPPORTS_TUNING
 575 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 576 {
 577         struct hsmmc *mmc_base;
 578         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 579         u32 val;
 580
 581         mmc_base = priv->base_addr;
 582         val = readl(&mmc_base->ac12);
 583         val &= ~(AC12_SCLK_SEL);
 584         writel(val, &mmc_base->ac12);
 585
 586         val = readl(&mmc_base->dll);
 587         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 588         writel(val, &mmc_base->dll);
 589 }
 590
 591 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 592 {
 593         int i;
 594         struct hsmmc *mmc_base;
 595         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 596         u32 val;
 597
 598         mmc_base = priv->base_addr;
 599         val = readl(&mmc_base->dll);
 600         val |= DLL_FORCE_VALUE;
 601         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 602         val |= (count << DLL_FORCE_SR_C_SHIFT);
 603         writel(val, &mmc_base->dll);
 604
 605         val |= DLL_CALIB;
 606         writel(val, &mmc_base->dll);
 607         for (i = 0; i < 1000; i++) {
 608                 if (readl(&mmc_base->dll) & DLL_CALIB)
 609                         break;
 610         }
 611         val &= ~DLL_CALIB;
 612         writel(val, &mmc_base->dll);
 613 }
 614
 615 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 616 {
 617         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 618         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 619         struct mmc *mmc = upriv->mmc;
 620         struct hsmmc *mmc_base;
 621         u32 val;
 622         u8 cur_match, prev_match = 0;
 623         int ret;
 624         u32 phase_delay = 0;
 625         u32 start_window = 0, max_window = 0;
 626         u32 length = 0, max_len = 0;
 627         bool single_point_failure = false;
 628         struct udevice *thermal_dev;
 629         int temperature;
 630         int i;
 631
 632         mmc_base = priv->base_addr;
 633         val = readl(&mmc_base->capa2);
 634
 635         /* clock tuning is not needed for upto 52MHz */
 636         if (!((mmc->selected_mode == MMC_HS_200) ||
 637               (mmc->selected_mode == UHS_SDR104) ||
 638               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 639                 return 0;
 640
 641         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 642         if (ret) {
 643                 printf("Couldn't get thermal device for tuning\n");
 644                 return ret;
 645         }
 646         ret = thermal_get_temp(thermal_dev, &temperature);
 647         if (ret) {
 648                 printf("Couldn't get temperature for tuning\n");
 649                 return ret;
 650         }
 651         val = readl(&mmc_base->dll);
 652         val |= DLL_SWT;
 653         writel(val, &mmc_base->dll);
 654
 655         /*
 656          * Stage 1: Search for a maximum pass window ignoring any
 657          * any single point failures. If the tuning value ends up
 658          * near it, move away from it in stage 2 below
 659          */
 660         while (phase_delay <= MAX_PHASE_DELAY) {
 661                 omap_hsmmc_set_dll(mmc, phase_delay);
 662
 663                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 664
 665                 if (cur_match) {
 666                         if (prev_match) {
 667                                 length++;
 668                         } else if (single_point_failure) {
 669                                 /* ignore single point failure */
 670                                 length++;
 671                                 single_point_failure = false;
 672                         } else {
 673                                 start_window = phase_delay;
 674                                 length = 1;
 675                         }
 676                 } else {
 677                         single_point_failure = prev_match;
 678                 }
 679
 680                 if (length > max_len) {
 681                         max_window = start_window;
 682                         max_len = length;
 683                 }
 684
 685                 prev_match = cur_match;
 686                 phase_delay += 4;
 687         }
 688
 689         if (!max_len) {
 690                 ret = -EIO;
 691                 goto tuning_error;
 692         }
 693
 694         val = readl(&mmc_base->ac12);
 695         if (!(val & AC12_SCLK_SEL)) {
 696                 ret = -EIO;
 697                 goto tuning_error;
 698         }
 699         /*
 700          * Assign tuning value as a ratio of maximum pass window based
 701          * on temperature
 702          */
 703         if (temperature < -20000)
 704                 phase_delay = min(max_window + 4 * max_len - 24,
 705                                   max_window +
 706                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 707         else if (temperature < 20000)
 708                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 709         else if (temperature < 40000)
 710                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 711         else if (temperature < 70000)
 712                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 713         else if (temperature < 90000)
 714                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 715         else if (temperature < 120000)
 716                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 717         else
 718                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 719
 720         /*
 721          * Stage 2: Search for a single point failure near the chosen tuning
 722          * value in two steps. First in the +3 to +10 range and then in the
 723          * +2 to -10 range. If found, move away from it in the appropriate
 724          * direction by the appropriate amount depending on the temperature.
 725          */
 726         for (i = 3; i <= 10; i++) {
 727                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 728                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 729                         if (temperature < 10000)
 730                                 phase_delay += i + 6;
 731                         else if (temperature < 20000)
 732                                 phase_delay += i - 12;
 733                         else if (temperature < 70000)
 734                                 phase_delay += i - 8;
 735                         else if (temperature < 90000)
 736                                 phase_delay += i - 6;
 737                         else
 738                                 phase_delay += i - 6;
 739
 740                         goto single_failure_found;
 741                 }
 742         }
 743
 744         for (i = 2; i >= -10; i--) {
 745                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 746                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 747                         if (temperature < 10000)
 748                                 phase_delay += i + 12;
 749                         else if (temperature < 20000)
 750                                 phase_delay += i + 8;
 751                         else if (temperature < 70000)
 752                                 phase_delay += i + 8;
 753                         else if (temperature < 90000)
 754                                 phase_delay += i + 10;
 755                         else
 756                                 phase_delay += i + 12;
 757
 758                         goto single_failure_found;
 759                 }
 760         }
 761
 762 single_failure_found:
 763
 764         omap_hsmmc_set_dll(mmc, phase_delay);
 765
 766         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 767         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 768
 769         return 0;
 770
 771 tuning_error:
 772
 773         omap_hsmmc_disable_tuning(mmc);
 774         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 775         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 776
 777         return ret;
 778 }
 779 #endif
 780 #endif
 781
 782 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 783 {
 784         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 785         struct hsmmc *mmc_base = priv->base_addr;
 786         u32 irq_mask = INT_EN_MASK;
 787
 788         /*
 789          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 790          * tuning procedure and DCRC should be disabled. But see occurences
 791          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 792          * interrupts occur along with BRR, so the data is actually in the
 793          * buffer. It has to be debugged why these interrutps occur
 794          */
 795         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 796                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 797
 798         writel(irq_mask, &mmc_base->ie);
 799 }
 800
 801 static int omap_hsmmc_init_setup(struct mmc *mmc)
 802 {
 803         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 804         struct hsmmc *mmc_base;
 805         unsigned int reg_val;
 806         unsigned int dsor;
 807         ulong start;
 808
 809         mmc_base = priv->base_addr;
 810         mmc_board_init(mmc);
 811
 812         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 813                 &mmc_base->sysconfig);
 814         start = get_timer(0);
 815         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 816                 if (get_timer(0) - start > MAX_RETRY_MS) {
 817                         printf("%s: timedout waiting for cc2!\n", __func__);
 818                         return -ETIMEDOUT;
 819                 }
 820         }
 821         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 822         start = get_timer(0);
 823         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 824                 if (get_timer(0) - start > MAX_RETRY_MS) {
 825                         printf("%s: timedout waiting for softresetall!\n",
 826                                 __func__);
 827                         return -ETIMEDOUT;
 828                 }
 829         }
 830 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 831         reg_val = readl(&mmc_base->hl_hwinfo);
 832         if (reg_val & MADMA_EN)
 833                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 834 #endif
 835
 836 #if CONFIG_IS_ENABLED(DM_MMC)
 837         reg_val = omap_hsmmc_set_capabilities(mmc);
 838         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 839                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 840 #else
 841         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 842         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 843                 &mmc_base->capa);
 844 #endif
 845
 846         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 847
 848         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 849                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 850                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 851
 852         dsor = 240;
 853         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 854                 (ICE_STOP | DTO_15THDTO));
 855         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 856                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 857         start = get_timer(0);
 858         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 859                 if (get_timer(0) - start > MAX_RETRY_MS) {
 860                         printf("%s: timedout waiting for ics!\n", __func__);
 861                         return -ETIMEDOUT;
 862                 }
 863         }
 864         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 865
 866         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 867
 868         mmc_enable_irq(mmc, NULL);
 869
 870 #if !CONFIG_IS_ENABLED(DM_MMC)
 871         mmc_init_stream(mmc_base);
 872 #endif
 873
 874         return 0;
 875 }
 876
 877 /*
 878  * MMC controller internal finite state machine reset
 879  *
 880  * Used to reset command or data internal state machines, using respectively
 881  * SRC or SRD bit of SYSCTL register
 882  */
 883 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 884 {
 885         ulong start;
 886
 887         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 888
 889         /*
 890          * CMD(DAT) lines reset procedures are slightly different
 891          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 892          * According to OMAP3 TRM:
 893          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 894          * returns to 0x0.
 895          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 896          * procedure steps must be as follows:
 897          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 898          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 899          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 900          * 3. Wait until the SRC (SRD) bit returns to 0x0
 901          *    (reset procedure is completed).
 902          */
 903 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 904         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 905         if (!(readl(&mmc_base->sysctl) & bit)) {
 906                 start = get_timer(0);
 907                 while (!(readl(&mmc_base->sysctl) & bit)) {
 908                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 909                                 return;
 910                 }
 911         }
 912 #endif
 913         start = get_timer(0);
 914         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 915                 if (get_timer(0) - start > MAX_RETRY_MS) {
 916                         printf("%s: timedout waiting for sysctl %x to clear\n",
 917                                 __func__, bit);
 918                         return;
 919                 }
 920         }
 921 }
 922
 923 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 924 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 925 {
 926         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 927         struct omap_hsmmc_adma_desc *desc;
 928         u8 attr;
 929
 930         desc = &priv->adma_desc_table[priv->desc_slot];
 931
 932         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 933         if (!end)
 934                 priv->desc_slot++;
 935         else
 936                 attr |= ADMA_DESC_ATTR_END;
 937
 938         desc->len = len;
 939         desc->addr = (u32)buf;
 940         desc->reserved = 0;
 941         desc->attr = attr;
 942 }
 943
 944 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 945                                           struct mmc_data *data)
 946 {
 947         uint total_len = data->blocksize * data->blocks;
 948         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 949         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 950         int i = desc_count;
 951         char *buf;
 952
 953         priv->desc_slot = 0;
 954         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 955                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 956                                 sizeof(struct omap_hsmmc_adma_desc));
 957
 958         if (data->flags & MMC_DATA_READ)
 959                 buf = data->dest;
 960         else
 961                 buf = (char *)data->src;
 962
 963         while (--i) {
 964                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 965                 buf += ADMA_MAX_LEN;
 966                 total_len -= ADMA_MAX_LEN;
 967         }
 968
 969         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 970
 971         flush_dcache_range((long)priv->adma_desc_table,
 972                            (long)priv->adma_desc_table +
 973                            ROUND(desc_count *
 974                            sizeof(struct omap_hsmmc_adma_desc),
 975                            ARCH_DMA_MINALIGN));
 976 }
 977
 978 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 979 {
 980         struct hsmmc *mmc_base;
 981         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 982         u32 val;
 983         char *buf;
 984
 985         mmc_base = priv->base_addr;
 986         omap_hsmmc_prepare_adma_table(mmc, data);
 987
 988         if (data->flags & MMC_DATA_READ)
 989                 buf = data->dest;
 990         else
 991                 buf = (char *)data->src;
 992
 993         val = readl(&mmc_base->hctl);
 994         val |= DMA_SELECT;
 995         writel(val, &mmc_base->hctl);
 996
 997         val = readl(&mmc_base->con);
 998         val |= DMA_MASTER;
 999         writel(val, &mmc_base->con);
1000
1001         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1002
1003         flush_dcache_range((u32)buf,
1004                            (u32)buf +
1005                            ROUND(data->blocksize * data->blocks,
1006                                  ARCH_DMA_MINALIGN));
1007 }
1008
1009 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1010 {
1011         struct hsmmc *mmc_base;
1012         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1013         u32 val;
1014
1015         mmc_base = priv->base_addr;
1016
1017         val = readl(&mmc_base->con);
1018         val &= ~DMA_MASTER;
1019         writel(val, &mmc_base->con);
1020
1021         val = readl(&mmc_base->hctl);
1022         val &= ~DMA_SELECT;
1023         writel(val, &mmc_base->hctl);
1024
1025         kfree(priv->adma_desc_table);
1026 }
1027 #else
1028 #define omap_hsmmc_adma_desc
1029 #define omap_hsmmc_prepare_adma_table
1030 #define omap_hsmmc_prepare_data
1031 #define omap_hsmmc_dma_cleanup
1032 #endif
1033
1034 #if !CONFIG_IS_ENABLED(DM_MMC)
1035 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1036                         struct mmc_data *data)
1037 {
1038         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1039 #else
1040 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1041                         struct mmc_data *data)
1042 {
1043         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1044         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1045         struct mmc *mmc = upriv->mmc;
1046 #endif
1047         struct hsmmc *mmc_base;
1048         unsigned int flags, mmc_stat;
1049         ulong start;
1050         priv->last_cmd = cmd->cmdidx;
1051
1052         mmc_base = priv->base_addr;
1053
1054         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1055                 return 0;
1056
1057         start = get_timer(0);
1058         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1059                 if (get_timer(0) - start > MAX_RETRY_MS) {
1060                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1061                                         __func__);
1062                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1063                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1064                         return -ETIMEDOUT;
1065                 }
1066         }
1067         writel(0xFFFFFFFF, &mmc_base->stat);
1068         if (readl(&mmc_base->stat)) {
1069                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1070                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1071         }
1072
1073         /*
1074          * CMDREG
1075          * CMDIDX[13:8] : Command index
1076          * DATAPRNT[5]  : Data Present Select
1077          * ENCMDIDX[4]  : Command Index Check Enable
1078          * ENCMDCRC[3]  : Command CRC Check Enable
1079          * RSPTYP[1:0]
1080          *      00 = No Response
1081          *      01 = Length 136
1082          *      10 = Length 48
1083          *      11 = Length 48 Check busy after response
1084          */
1085         /* Delay added before checking the status of frq change
1086          * retry not supported by mmc.c(core file)
1087          */
1088         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1089                 udelay(50000); /* wait 50 ms */
1090
1091         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1092                 flags = 0;
1093         else if (cmd->resp_type & MMC_RSP_136)
1094                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1095         else if (cmd->resp_type & MMC_RSP_BUSY)
1096                 flags = RSP_TYPE_LGHT48B;
1097         else
1098                 flags = RSP_TYPE_LGHT48;
1099
1100         /* enable default flags */
1101         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1102                         MSBS_SGLEBLK);
1103         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1104
1105         if (cmd->resp_type & MMC_RSP_CRC)
1106                 flags |= CCCE_CHECK;
1107         if (cmd->resp_type & MMC_RSP_OPCODE)
1108                 flags |= CICE_CHECK;
1109
1110         if (data) {
1111                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1112                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1113                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1114                         data->blocksize = 512;
1115                         writel(data->blocksize | (data->blocks << 16),
1116                                                         &mmc_base->blk);
1117                 } else
1118                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1119
1120                 if (data->flags & MMC_DATA_READ)
1121                         flags |= (DP_DATA | DDIR_READ);
1122                 else
1123                         flags |= (DP_DATA | DDIR_WRITE);
1124
1125 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1126                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1127                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1128                         omap_hsmmc_prepare_data(mmc, data);
1129                         flags |= DE_ENABLE;
1130                 }
1131 #endif
1132         }
1133
1134         mmc_enable_irq(mmc, cmd);
1135
1136         writel(cmd->cmdarg, &mmc_base->arg);
1137         udelay(20);             /* To fix "No status update" error on eMMC */
1138         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1139
1140         start = get_timer(0);
1141         do {
1142                 mmc_stat = readl(&mmc_base->stat);
1143                 if (get_timer(start) > MAX_RETRY_MS) {
1144                         printf("%s : timeout: No status update\n", __func__);
1145                         return -ETIMEDOUT;
1146                 }
1147         } while (!mmc_stat);
1148
1149         if ((mmc_stat & IE_CTO) != 0) {
1150                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1151                 return -ETIMEDOUT;
1152         } else if ((mmc_stat & ERRI_MASK) != 0)
1153                 return -1;
1154
1155         if (mmc_stat & CC_MASK) {
1156                 writel(CC_MASK, &mmc_base->stat);
1157                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1158                         if (cmd->resp_type & MMC_RSP_136) {
1159                                 /* response type 2 */
1160                                 cmd->response[3] = readl(&mmc_base->rsp10);
1161                                 cmd->response[2] = readl(&mmc_base->rsp32);
1162                                 cmd->response[1] = readl(&mmc_base->rsp54);
1163                                 cmd->response[0] = readl(&mmc_base->rsp76);
1164                         } else
1165                                 /* response types 1, 1b, 3, 4, 5, 6 */
1166                                 cmd->response[0] = readl(&mmc_base->rsp10);
1167                 }
1168         }
1169
1170 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1171         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1172             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1173                 u32 sz_mb, timeout;
1174
1175                 if (mmc_stat & IE_ADMAE) {
1176                         omap_hsmmc_dma_cleanup(mmc);
1177                         return -EIO;
1178                 }
1179
1180                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1181                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1182                 if (timeout < MAX_RETRY_MS)
1183                         timeout = MAX_RETRY_MS;
1184
1185                 start = get_timer(0);
1186                 do {
1187                         mmc_stat = readl(&mmc_base->stat);
1188                         if (mmc_stat & TC_MASK) {
1189                                 writel(readl(&mmc_base->stat) | TC_MASK,
1190                                        &mmc_base->stat);
1191                                 break;
1192                         }
1193                         if (get_timer(start) > timeout) {
1194                                 printf("%s : DMA timeout: No status update\n",
1195                                        __func__);
1196                                 return -ETIMEDOUT;
1197                         }
1198                 } while (1);
1199
1200                 omap_hsmmc_dma_cleanup(mmc);
1201                 return 0;
1202         }
1203 #endif
1204
1205         if (data && (data->flags & MMC_DATA_READ)) {
1206                 mmc_read_data(mmc_base, data->dest,
1207                                 data->blocksize * data->blocks);
1208         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1209                 mmc_write_data(mmc_base, data->src,
1210                                 data->blocksize * data->blocks);
1211         }
1212         return 0;
1213 }
1214
1215 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1216 {
1217         unsigned int *output_buf = (unsigned int *)buf;
1218         unsigned int mmc_stat;
1219         unsigned int count;
1220
1221         /*
1222          * Start Polled Read
1223          */
1224         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1225         count /= 4;
1226
1227         while (size) {
1228                 ulong start = get_timer(0);
1229                 do {
1230                         mmc_stat = readl(&mmc_base->stat);
1231                         if (get_timer(0) - start > MAX_RETRY_MS) {
1232                                 printf("%s: timedout waiting for status!\n",
1233                                                 __func__);
1234                                 return -ETIMEDOUT;
1235                         }
1236                 } while (mmc_stat == 0);
1237
1238                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1239                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1240
1241                 if ((mmc_stat & ERRI_MASK) != 0)
1242                         return 1;
1243
1244                 if (mmc_stat & BRR_MASK) {
1245                         unsigned int k;
1246
1247                         writel(readl(&mmc_base->stat) | BRR_MASK,
1248                                 &mmc_base->stat);
1249                         for (k = 0; k < count; k++) {
1250                                 *output_buf = readl(&mmc_base->data);
1251                                 output_buf++;
1252                         }
1253                         size -= (count*4);
1254                 }
1255
1256                 if (mmc_stat & BWR_MASK)
1257                         writel(readl(&mmc_base->stat) | BWR_MASK,
1258                                 &mmc_base->stat);
1259
1260                 if (mmc_stat & TC_MASK) {
1261                         writel(readl(&mmc_base->stat) | TC_MASK,
1262                                 &mmc_base->stat);
1263                         break;
1264                 }
1265         }
1266         return 0;
1267 }
1268
1269 #if CONFIG_IS_ENABLED(MMC_WRITE)
1270 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1271                           unsigned int size)
1272 {
1273         unsigned int *input_buf = (unsigned int *)buf;
1274         unsigned int mmc_stat;
1275         unsigned int count;
1276
1277         /*
1278          * Start Polled Write
1279          */
1280         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1281         count /= 4;
1282
1283         while (size) {
1284                 ulong start = get_timer(0);
1285                 do {
1286                         mmc_stat = readl(&mmc_base->stat);
1287                         if (get_timer(0) - start > MAX_RETRY_MS) {
1288                                 printf("%s: timedout waiting for status!\n",
1289                                                 __func__);
1290                                 return -ETIMEDOUT;
1291                         }
1292                 } while (mmc_stat == 0);
1293
1294                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1295                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1296
1297                 if ((mmc_stat & ERRI_MASK) != 0)
1298                         return 1;
1299
1300                 if (mmc_stat & BWR_MASK) {
1301                         unsigned int k;
1302
1303                         writel(readl(&mmc_base->stat) | BWR_MASK,
1304                                         &mmc_base->stat);
1305                         for (k = 0; k < count; k++) {
1306                                 writel(*input_buf, &mmc_base->data);
1307                                 input_buf++;
1308                         }
1309                         size -= (count*4);
1310                 }
1311
1312                 if (mmc_stat & BRR_MASK)
1313                         writel(readl(&mmc_base->stat) | BRR_MASK,
1314                                 &mmc_base->stat);
1315
1316                 if (mmc_stat & TC_MASK) {
1317                         writel(readl(&mmc_base->stat) | TC_MASK,
1318                                 &mmc_base->stat);
1319                         break;
1320                 }
1321         }
1322         return 0;
1323 }
1324 #else
1325 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1326                           unsigned int size)
1327 {
1328         return -ENOTSUPP;
1329 }
1330 #endif
1331 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1332 {
1333         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1334 }
1335
1336 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1337 {
1338         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1339 }
1340
1341 static void omap_hsmmc_set_clock(struct mmc *mmc)
1342 {
1343         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1344         struct hsmmc *mmc_base;
1345         unsigned int dsor = 0;
1346         ulong start;
1347
1348         mmc_base = priv->base_addr;
1349         omap_hsmmc_stop_clock(mmc_base);
1350
1351         /* TODO: Is setting DTO required here? */
1352         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1353                     (ICE_STOP | DTO_15THDTO));
1354
1355         if (mmc->clock != 0) {
1356                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1357                 if (dsor > CLKD_MAX)
1358                         dsor = CLKD_MAX;
1359         } else {
1360                 dsor = CLKD_MAX;
1361         }
1362
1363         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1364                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1365
1366         start = get_timer(0);
1367         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1368                 if (get_timer(0) - start > MAX_RETRY_MS) {
1369                         printf("%s: timedout waiting for ics!\n", __func__);
1370                         return;
1371                 }
1372         }
1373
1374         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1375         mmc->clock = priv->clock;
1376         omap_hsmmc_start_clock(mmc_base);
1377 }
1378
1379 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1380 {
1381         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1382         struct hsmmc *mmc_base;
1383
1384         mmc_base = priv->base_addr;
1385         /* configue bus width */
1386         switch (mmc->bus_width) {
1387         case 8:
1388                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1389                         &mmc_base->con);
1390                 break;
1391
1392         case 4:
1393                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1394                         &mmc_base->con);
1395                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1396                         &mmc_base->hctl);
1397                 break;
1398
1399         case 1:
1400         default:
1401                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1402                         &mmc_base->con);
1403                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1404                         &mmc_base->hctl);
1405                 break;
1406         }
1407
1408         priv->bus_width = mmc->bus_width;
1409 }
1410
1411 #if !CONFIG_IS_ENABLED(DM_MMC)
1412 static int omap_hsmmc_set_ios(struct mmc *mmc)
1413 {
1414         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1415 #else
1416 static int omap_hsmmc_set_ios(struct udevice *dev)
1417 {
1418         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1419         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1420         struct mmc *mmc = upriv->mmc;
1421 #endif
1422         struct hsmmc *mmc_base = priv->base_addr;
1423         int ret = 0;
1424
1425         if (priv->bus_width != mmc->bus_width)
1426                 omap_hsmmc_set_bus_width(mmc);
1427
1428         if (priv->clock != mmc->clock)
1429                 omap_hsmmc_set_clock(mmc);
1430
1431         if (mmc->clk_disable)
1432                 omap_hsmmc_stop_clock(mmc_base);
1433         else
1434                 omap_hsmmc_start_clock(mmc_base);
1435
1436 #if CONFIG_IS_ENABLED(DM_MMC)
1437         if (priv->mode != mmc->selected_mode)
1438                 omap_hsmmc_set_timing(mmc);
1439
1440 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1441         if (priv->signal_voltage != mmc->signal_voltage)
1442                 ret = omap_hsmmc_set_signal_voltage(mmc);
1443 #endif
1444 #endif
1445         return ret;
1446 }
1447
1448 #ifdef OMAP_HSMMC_USE_GPIO
1449 #if CONFIG_IS_ENABLED(DM_MMC)
1450 static int omap_hsmmc_getcd(struct udevice *dev)
1451 {
1452         int value = -1;
1453 #if CONFIG_IS_ENABLED(DM_GPIO)
1454         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1455         value = dm_gpio_get_value(&priv->cd_gpio);
1456 #endif
1457         /* if no CD return as 1 */
1458         if (value < 0)
1459                 return 1;
1460
1461         return value;
1462 }
1463
1464 static int omap_hsmmc_getwp(struct udevice *dev)
1465 {
1466         int value = 0;
1467 #if CONFIG_IS_ENABLED(DM_GPIO)
1468         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1469         value = dm_gpio_get_value(&priv->wp_gpio);
1470 #endif
1471         /* if no WP return as 0 */
1472         if (value < 0)
1473                 return 0;
1474         return value;
1475 }
1476 #else
1477 static int omap_hsmmc_getcd(struct mmc *mmc)
1478 {
1479         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1480         int cd_gpio;
1481
1482         /* if no CD return as 1 */
1483         cd_gpio = priv->cd_gpio;
1484         if (cd_gpio < 0)
1485                 return 1;
1486
1487         /* NOTE: assumes card detect signal is active-low */
1488         return !gpio_get_value(cd_gpio);
1489 }
1490
1491 static int omap_hsmmc_getwp(struct mmc *mmc)
1492 {
1493         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1494         int wp_gpio;
1495
1496         /* if no WP return as 0 */
1497         wp_gpio = priv->wp_gpio;
1498         if (wp_gpio < 0)
1499                 return 0;
1500
1501         /* NOTE: assumes write protect signal is active-high */
1502         return gpio_get_value(wp_gpio);
1503 }
1504 #endif
1505 #endif
1506
1507 #if CONFIG_IS_ENABLED(DM_MMC)
1508 static const struct dm_mmc_ops omap_hsmmc_ops = {
1509         .send_cmd       = omap_hsmmc_send_cmd,
1510         .set_ios        = omap_hsmmc_set_ios,
1511 #ifdef OMAP_HSMMC_USE_GPIO
1512         .get_cd         = omap_hsmmc_getcd,
1513         .get_wp         = omap_hsmmc_getwp,
1514 #endif
1515 #ifdef MMC_SUPPORTS_TUNING
1516         .execute_tuning = omap_hsmmc_execute_tuning,
1517 #endif
1518         .wait_dat0      = omap_hsmmc_wait_dat0,
1519 };
1520 #else
1521 static const struct mmc_ops omap_hsmmc_ops = {
1522         .send_cmd       = omap_hsmmc_send_cmd,
1523         .set_ios        = omap_hsmmc_set_ios,
1524         .init           = omap_hsmmc_init_setup,
1525 #ifdef OMAP_HSMMC_USE_GPIO
1526         .getcd          = omap_hsmmc_getcd,
1527         .getwp          = omap_hsmmc_getwp,
1528 #endif
1529 };
1530 #endif
1531
1532 #if !CONFIG_IS_ENABLED(DM_MMC)
1533 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1534                 int wp_gpio)
1535 {
1536         struct mmc *mmc;
1537         struct omap_hsmmc_data *priv;
1538         struct mmc_config *cfg;
1539         uint host_caps_val;
1540
1541         priv = calloc(1, sizeof(*priv));
1542         if (priv == NULL)
1543                 return -1;
1544
1545         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1546
1547         switch (dev_index) {
1548         case 0:
1549                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1550                 break;
1551 #ifdef OMAP_HSMMC2_BASE
1552         case 1:
1553                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1554 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1555         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1556         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1557                 defined(CONFIG_HSMMC2_8BIT)
1558                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1559                 host_caps_val |= MMC_MODE_8BIT;
1560 #endif
1561                 break;
1562 #endif
1563 #ifdef OMAP_HSMMC3_BASE
1564         case 2:
1565                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1566 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1567                 /* Enable 8-bit interface for eMMC on DRA7XX */
1568                 host_caps_val |= MMC_MODE_8BIT;
1569 #endif
1570                 break;
1571 #endif
1572         default:
1573                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1574                 return 1;
1575         }
1576 #ifdef OMAP_HSMMC_USE_GPIO
1577         /* on error gpio values are set to -1, which is what we want */
1578         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1579         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1580 #endif
1581
1582         cfg = &priv->cfg;
1583
1584         cfg->name = "OMAP SD/MMC";
1585         cfg->ops = &omap_hsmmc_ops;
1586
1587         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1588         cfg->host_caps = host_caps_val & ~host_caps_mask;
1589
1590         cfg->f_min = 400000;
1591
1592         if (f_max != 0)
1593                 cfg->f_max = f_max;
1594         else {
1595                 if (cfg->host_caps & MMC_MODE_HS) {
1596                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1597                                 cfg->f_max = 52000000;
1598                         else
1599                                 cfg->f_max = 26000000;
1600                 } else
1601                         cfg->f_max = 20000000;
1602         }
1603
1604         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1605
1606 #if defined(CONFIG_OMAP34XX)
1607         /*
1608          * Silicon revs 2.1 and older do not support multiblock transfers.
1609          */
1610         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1611                 cfg->b_max = 1;
1612 #endif
1613
1614         mmc = mmc_create(cfg, priv);
1615         if (mmc == NULL)
1616                 return -1;
1617
1618         return 0;
1619 }
1620 #else
1621
1622 #ifdef CONFIG_IODELAY_RECALIBRATION
1623 static struct pad_conf_entry *
1624 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1625 {
1626         int index = 0;
1627         struct pad_conf_entry *padconf;
1628
1629         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1630         if (!padconf) {
1631                 debug("failed to allocate memory\n");
1632                 return 0;
1633         }
1634
1635         while (index < count) {
1636                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1637                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1638                 index++;
1639         }
1640
1641         return padconf;
1642 }
1643
1644 static struct iodelay_cfg_entry *
1645 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1646 {
1647         int index = 0;
1648         struct iodelay_cfg_entry *iodelay;
1649
1650         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1651         if (!iodelay) {
1652                 debug("failed to allocate memory\n");
1653                 return 0;
1654         }
1655
1656         while (index < count) {
1657                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1658                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1659                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1660                 index++;
1661         }
1662
1663         return iodelay;
1664 }
1665
1666 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1667                                                    const char *name, int *len)
1668 {
1669         const void *fdt = gd->fdt_blob;
1670         int offset;
1671         const fdt32_t *pinctrl;
1672
1673         offset = fdt_node_offset_by_phandle(fdt, phandle);
1674         if (offset < 0) {
1675                 debug("failed to get pinctrl node %s.\n",
1676                       fdt_strerror(offset));
1677                 return 0;
1678         }
1679
1680         pinctrl = fdt_getprop(fdt, offset, name, len);
1681         if (!pinctrl) {
1682                 debug("failed to get property %s\n", name);
1683                 return 0;
1684         }
1685
1686         return pinctrl;
1687 }
1688
1689 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1690                                                 char *prop_name)
1691 {
1692         const void *fdt = gd->fdt_blob;
1693         const __be32 *phandle;
1694         int node = dev_of_offset(mmc->dev);
1695
1696         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1697         if (!phandle) {
1698                 debug("failed to get property %s\n", prop_name);
1699                 return 0;
1700         }
1701
1702         return fdt32_to_cpu(*phandle);
1703 }
1704
1705 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1706                                                char *prop_name)
1707 {
1708         const void *fdt = gd->fdt_blob;
1709         const __be32 *phandle;
1710         int len;
1711         int count;
1712         int node = dev_of_offset(mmc->dev);
1713
1714         phandle = fdt_getprop(fdt, node, prop_name, &len);
1715         if (!phandle) {
1716                 debug("failed to get property %s\n", prop_name);
1717                 return 0;
1718         }
1719
1720         /* No manual mode iodelay values if count < 2 */
1721         count = len / sizeof(*phandle);
1722         if (count < 2)
1723                 return 0;
1724
1725         return fdt32_to_cpu(*(phandle + 1));
1726 }
1727
1728 static struct pad_conf_entry *
1729 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1730 {
1731         int len;
1732         int count;
1733         struct pad_conf_entry *padconf;
1734         u32 phandle;
1735         const fdt32_t *pinctrl;
1736
1737         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1738         if (!phandle)
1739                 return ERR_PTR(-EINVAL);
1740
1741         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1742                                                &len);
1743         if (!pinctrl)
1744                 return ERR_PTR(-EINVAL);
1745
1746         count = (len / sizeof(*pinctrl)) / 2;
1747         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1748         if (!padconf)
1749                 return ERR_PTR(-EINVAL);
1750
1751         *npads = count;
1752
1753         return padconf;
1754 }
1755
1756 static struct iodelay_cfg_entry *
1757 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1758 {
1759         int len;
1760         int count;
1761         struct iodelay_cfg_entry *iodelay;
1762         u32 phandle;
1763         const fdt32_t *pinctrl;
1764
1765         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1766         /* Not all modes have manual mode iodelay values. So its not fatal */
1767         if (!phandle)
1768                 return 0;
1769
1770         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1771                                                &len);
1772         if (!pinctrl)
1773                 return ERR_PTR(-EINVAL);
1774
1775         count = (len / sizeof(*pinctrl)) / 3;
1776         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1777         if (!iodelay)
1778                 return ERR_PTR(-EINVAL);
1779
1780         *niodelay = count;
1781
1782         return iodelay;
1783 }
1784
1785 static struct omap_hsmmc_pinctrl_state *
1786 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1787 {
1788         int index;
1789         int npads = 0;
1790         int niodelays = 0;
1791         const void *fdt = gd->fdt_blob;
1792         int node = dev_of_offset(mmc->dev);
1793         char prop_name[11];
1794         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1795
1796         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1797                          malloc(sizeof(*pinctrl_state));
1798         if (!pinctrl_state) {
1799                 debug("failed to allocate memory\n");
1800                 return 0;
1801         }
1802
1803         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1804         if (index < 0) {
1805                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1806                 goto err_pinctrl_state;
1807         }
1808
1809         sprintf(prop_name, "pinctrl-%d", index);
1810
1811         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1812                                                          &npads);
1813         if (IS_ERR(pinctrl_state->padconf))
1814                 goto err_pinctrl_state;
1815         pinctrl_state->npads = npads;
1816
1817         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1818                                                         &niodelays);
1819         if (IS_ERR(pinctrl_state->iodelay))
1820                 goto err_padconf;
1821         pinctrl_state->niodelays = niodelays;
1822
1823         return pinctrl_state;
1824
1825 err_padconf:
1826         kfree(pinctrl_state->padconf);
1827
1828 err_pinctrl_state:
1829         kfree(pinctrl_state);
1830         return 0;
1831 }
1832
1833 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1834         do {                                                            \
1835                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1836                 char str[20];                                           \
1837                 if (!(cfg->host_caps & capmask))                        \
1838                         break;                                          \
1839                                                                         \
1840                 if (priv->hw_rev) {                                     \
1841                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1842                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1843                 }                                                       \
1844                                                                         \
1845                 if (!s)                                                 \
1846                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1847                                                                         \
1848                 if (!s && !optional) {                                  \
1849                         debug("%s: no pinctrl for %s\n",                \
1850                               mmc->dev->name, #mode);                   \
1851                         cfg->host_caps &= ~(capmask);                   \
1852                 } else {                                                \
1853                         priv->mode##_pinctrl_state = s;                 \
1854                 }                                                       \
1855         } while (0)
1856
1857 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1858 {
1859         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1860         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1861         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1862
1863         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1864                 return 0;
1865
1866         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1867         if (!default_pinctrl) {
1868                 printf("no pinctrl state for default mode\n");
1869                 return -EINVAL;
1870         }
1871
1872         priv->default_pinctrl_state = default_pinctrl;
1873
1874         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1875         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1876         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1877         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1878         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1879
1880         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1881         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1882         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1883
1884         return 0;
1885 }
1886 #endif
1887
1888 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1889 #ifdef CONFIG_OMAP54XX
1890 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1891 {
1892         return NULL;
1893 }
1894 #endif
1895
1896 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1897 {
1898         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1899         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1900
1901         struct mmc_config *cfg = &plat->cfg;
1902 #ifdef CONFIG_OMAP54XX
1903         const struct mmc_platform_fixups *fixups;
1904 #endif
1905         const void *fdt = gd->fdt_blob;
1906         int node = dev_of_offset(dev);
1907         int ret;
1908
1909         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1910                                       sizeof(struct hsmmc *),
1911                                       MAP_NOCACHE);
1912
1913         ret = mmc_of_parse(dev, cfg);
1914         if (ret < 0)
1915                 return ret;
1916
1917         if (!cfg->f_max)
1918                 cfg->f_max = 52000000;
1919         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1920         cfg->f_min = 400000;
1921         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1922         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1923         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1924                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1925         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1926                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1927         if (of_data)
1928                 plat->controller_flags |= of_data->controller_flags;
1929
1930 #ifdef CONFIG_OMAP54XX
1931         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1932         if (fixups) {
1933                 plat->hw_rev = fixups->hw_rev;
1934                 cfg->host_caps &= ~fixups->unsupported_caps;
1935                 cfg->f_max = fixups->max_freq;
1936         }
1937 #endif
1938
1939         return 0;
1940 }
1941 #endif
1942
1943 #ifdef CONFIG_BLK
1944
1945 static int omap_hsmmc_bind(struct udevice *dev)
1946 {
1947         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1948         plat->mmc = calloc(1, sizeof(struct mmc));
1949         return mmc_bind(dev, plat->mmc, &plat->cfg);
1950 }
1951 #endif
1952 static int omap_hsmmc_probe(struct udevice *dev)
1953 {
1954         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1955         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1956         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1957         struct mmc_config *cfg = &plat->cfg;
1958         struct mmc *mmc;
1959 #ifdef CONFIG_IODELAY_RECALIBRATION
1960         int ret;
1961 #endif
1962
1963         cfg->name = "OMAP SD/MMC";
1964         priv->base_addr = plat->base_addr;
1965         priv->controller_flags = plat->controller_flags;
1966         priv->hw_rev = plat->hw_rev;
1967
1968 #ifdef CONFIG_BLK
1969         mmc = plat->mmc;
1970 #else
1971         mmc = mmc_create(cfg, priv);
1972         if (mmc == NULL)
1973                 return -1;
1974 #endif
1975 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1976         device_get_supply_regulator(dev, "pbias-supply",
1977                                     &priv->pbias_supply);
1978 #endif
1979 #if defined(OMAP_HSMMC_USE_GPIO)
1980 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1981         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1982         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1983 #endif
1984 #endif
1985
1986         mmc->dev = dev;
1987         upriv->mmc = mmc;
1988
1989 #ifdef CONFIG_IODELAY_RECALIBRATION
1990         ret = omap_hsmmc_get_pinctrl_state(mmc);
1991         /*
1992          * disable high speed modes for the platforms that require IO delay
1993          * and for which we don't have this information
1994          */
1995         if ((ret < 0) &&
1996             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1997                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1998                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1999                                     UHS_CAPS);
2000         }
2001 #endif
2002
2003         return omap_hsmmc_init_setup(mmc);
2004 }
2005
2006 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2007
2008 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2009         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2010 };
2011
2012 static const struct udevice_id omap_hsmmc_ids[] = {
2013         { .compatible = "ti,omap3-hsmmc" },
2014         { .compatible = "ti,omap4-hsmmc" },
2015         { .compatible = "ti,am33xx-hsmmc" },
2016         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2017         { }
2018 };
2019 #endif
2020
2021 U_BOOT_DRIVER(omap_hsmmc) = {
2022         .name   = "omap_hsmmc",
2023         .id     = UCLASS_MMC,
2024 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2025         .of_match = omap_hsmmc_ids,
2026         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2027         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2028 #endif
2029 #ifdef CONFIG_BLK
2030         .bind = omap_hsmmc_bind,
2031 #endif
2032         .ops = &omap_hsmmc_ops,
2033         .probe  = omap_hsmmc_probe,
2034         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2035 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2036         .flags  = DM_FLAG_PRE_RELOC,
2037 #endif
2038 };
2039 #endif