drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <cpu_func.h>
  28 #include <log.h>
  29 #include <malloc.h>
  30 #include <memalign.h>
  31 #include <mmc.h>
  32 #include <part.h>
  33 #include <i2c.h>
  34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  35 #include <palmas.h>
  36 #endif
  37 #include <asm/cache.h>
  38 #include <asm/io.h>
  39 #include <asm/arch/mmc_host_def.h>
  40 #ifdef CONFIG_OMAP54XX
  41 #include <asm/arch/mux_dra7xx.h>
  42 #include <asm/arch/dra7xx_iodelay.h>
  43 #endif
  44 #if !defined(CONFIG_SOC_KEYSTONE)
  45 #include <asm/gpio.h>
  46 #include <asm/arch/sys_proto.h>
  47 #endif
  48 #ifdef CONFIG_MMC_OMAP36XX_PINS
  49 #include <asm/arch/mux.h>
  50 #endif
  51 #include <dm.h>
  52 #include <dm/devres.h>
  53 #include <linux/delay.h>
  54 #include <linux/err.h>
  55 #include <power/regulator.h>
  56 #include <thermal.h>
  57
  58 DECLARE_GLOBAL_DATA_PTR;
  59
  60 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  61 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  62         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  63 #define OMAP_HSMMC_USE_GPIO
  64 #else
  65 #undef OMAP_HSMMC_USE_GPIO
  66 #endif
  67
  68 /* common definitions for all OMAPs */
  69 #define SYSCTL_SRC      (1 << 25)
  70 #define SYSCTL_SRD      (1 << 26)
  71
  72 #ifdef CONFIG_IODELAY_RECALIBRATION
  73 struct omap_hsmmc_pinctrl_state {
  74         struct pad_conf_entry *padconf;
  75         int npads;
  76         struct iodelay_cfg_entry *iodelay;
  77         int niodelays;
  78 };
  79 #endif
  80
  81 struct omap_hsmmc_data {
  82         struct hsmmc *base_addr;
  83 #if !CONFIG_IS_ENABLED(DM_MMC)
  84         struct mmc_config cfg;
  85 #endif
  86         uint bus_width;
  87         uint clock;
  88         ushort last_cmd;
  89 #ifdef OMAP_HSMMC_USE_GPIO
  90 #if CONFIG_IS_ENABLED(DM_MMC)
  91         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  92         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  93 #else
  94         int cd_gpio;
  95         int wp_gpio;
  96 #endif
  97 #endif
  98 #if CONFIG_IS_ENABLED(DM_MMC)
  99         enum bus_mode mode;
 100 #endif
 101         u8 controller_flags;
 102 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 103         struct omap_hsmmc_adma_desc *adma_desc_table;
 104         uint desc_slot;
 105 #endif
 106         const char *hw_rev;
 107         struct udevice *pbias_supply;
 108         uint signal_voltage;
 109 #ifdef CONFIG_IODELAY_RECALIBRATION
 110         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 113         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 114         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 115         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 116         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 117         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 118         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 119 #endif
 120 };
 121
 122 struct omap_mmc_of_data {
 123         u8 controller_flags;
 124 };
 125
 126 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 127 struct omap_hsmmc_adma_desc {
 128         u8 attr;
 129         u8 reserved;
 130         u16 len;
 131         u32 addr;
 132 };
 133
 134 #define ADMA_MAX_LEN    63488
 135
 136 /* Decriptor table defines */
 137 #define ADMA_DESC_ATTR_VALID            BIT(0)
 138 #define ADMA_DESC_ATTR_END              BIT(1)
 139 #define ADMA_DESC_ATTR_INT              BIT(2)
 140 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 141 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 142
 143 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 144 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 145 #endif
 146
 147 /* If we fail after 1 second wait, something is really bad */
 148 #define MAX_RETRY_MS    1000
 149 #define MMC_TIMEOUT_MS  20
 150
 151 /* DMA transfers can take a long time if a lot a data is transferred.
 152  * The timeout must take in account the amount of data. Let's assume
 153  * that the time will never exceed 333 ms per MB (in other word we assume
 154  * that the bandwidth is always above 3MB/s).
 155  */
 156 #define DMA_TIMEOUT_PER_MB      333
 157 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 158 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 159 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 160 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 161
 162 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 163 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 164                         unsigned int siz);
 165 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 166 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 167 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 168
 169 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 170 {
 171 #if CONFIG_IS_ENABLED(DM_MMC)
 172         return dev_get_priv(mmc->dev);
 173 #else
 174         return (struct omap_hsmmc_data *)mmc->priv;
 175 #endif
 176 }
 177 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 178 {
 179 #if CONFIG_IS_ENABLED(DM_MMC)
 180         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 181         return &plat->cfg;
 182 #else
 183         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 184 #endif
 185 }
 186
 187 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 188 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 189 {
 190         int ret;
 191
 192 #if !CONFIG_IS_ENABLED(DM_GPIO)
 193         if (!gpio_is_valid(gpio))
 194                 return -1;
 195 #endif
 196         ret = gpio_request(gpio, label);
 197         if (ret)
 198                 return ret;
 199
 200         ret = gpio_direction_input(gpio);
 201         if (ret)
 202                 return ret;
 203
 204         return gpio;
 205 }
 206 #endif
 207
 208 static unsigned char mmc_board_init(struct mmc *mmc)
 209 {
 210 #if defined(CONFIG_OMAP34XX)
 211         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 212         t2_t *t2_base = (t2_t *)T2_BASE;
 213         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 214         u32 pbias_lite;
 215 #ifdef CONFIG_MMC_OMAP36XX_PINS
 216         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 217 #endif
 218
 219         pbias_lite = readl(&t2_base->pbias_lite);
 220         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 221 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 222         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 223         pbias_lite &= ~PBIASLITEVMODE0;
 224 #endif
 225 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 226         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 227         pbias_lite &= ~PBIASLITEVMODE1;
 228 #endif
 229 #ifdef CONFIG_MMC_OMAP36XX_PINS
 230         if (get_cpu_family() == CPU_OMAP36XX) {
 231                 /* Disable extended drain IO before changing PBIAS */
 232                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 233                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 234         }
 235 #endif
 236         writel(pbias_lite, &t2_base->pbias_lite);
 237
 238         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 239                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 240                 &t2_base->pbias_lite);
 241
 242 #ifdef CONFIG_MMC_OMAP36XX_PINS
 243         if (get_cpu_family() == CPU_OMAP36XX)
 244                 /* Enable extended drain IO after changing PBIAS */
 245                 writel(wkup_ctrl |
 246                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 247                                 OMAP34XX_CTRL_WKUP_CTRL);
 248 #endif
 249         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 250                 &t2_base->devconf0);
 251
 252         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 253                 &t2_base->devconf1);
 254
 255         /* Change from default of 52MHz to 26MHz if necessary */
 256         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 257                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 258                         &t2_base->ctl_prog_io1);
 259
 260         writel(readl(&prcm_base->fclken1_core) |
 261                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 262                 &prcm_base->fclken1_core);
 263
 264         writel(readl(&prcm_base->iclken1_core) |
 265                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 266                 &prcm_base->iclken1_core);
 267 #endif
 268
 269 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 270         !CONFIG_IS_ENABLED(DM_REGULATOR)
 271         /* PBIAS config needed for MMC1 only */
 272         if (mmc_get_blk_desc(mmc)->devnum == 0)
 273                 vmmc_pbias_config(LDO_VOLT_3V3);
 274 #endif
 275
 276         return 0;
 277 }
 278
 279 void mmc_init_stream(struct hsmmc *mmc_base)
 280 {
 281         ulong start;
 282
 283         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 284
 285         writel(MMC_CMD0, &mmc_base->cmd);
 286         start = get_timer(0);
 287         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 288                 if (get_timer(0) - start > MAX_RETRY_MS) {
 289                         printf("%s: timedout waiting for cc!\n", __func__);
 290                         return;
 291                 }
 292         }
 293         writel(CC_MASK, &mmc_base->stat)
 294                 ;
 295         writel(MMC_CMD0, &mmc_base->cmd)
 296                 ;
 297         start = get_timer(0);
 298         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 299                 if (get_timer(0) - start > MAX_RETRY_MS) {
 300                         printf("%s: timedout waiting for cc2!\n", __func__);
 301                         return;
 302                 }
 303         }
 304         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 305 }
 306
 307 #if CONFIG_IS_ENABLED(DM_MMC)
 308 #ifdef CONFIG_IODELAY_RECALIBRATION
 309 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 310 {
 311         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 312         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 313
 314         switch (priv->mode) {
 315         case MMC_HS_200:
 316                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 317                 break;
 318         case UHS_SDR104:
 319                 pinctrl_state = priv->sdr104_pinctrl_state;
 320                 break;
 321         case UHS_SDR50:
 322                 pinctrl_state = priv->sdr50_pinctrl_state;
 323                 break;
 324         case UHS_DDR50:
 325                 pinctrl_state = priv->ddr50_pinctrl_state;
 326                 break;
 327         case UHS_SDR25:
 328                 pinctrl_state = priv->sdr25_pinctrl_state;
 329                 break;
 330         case UHS_SDR12:
 331                 pinctrl_state = priv->sdr12_pinctrl_state;
 332                 break;
 333         case SD_HS:
 334         case MMC_HS:
 335         case MMC_HS_52:
 336                 pinctrl_state = priv->hs_pinctrl_state;
 337                 break;
 338         case MMC_DDR_52:
 339                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 340         default:
 341                 pinctrl_state = priv->default_pinctrl_state;
 342                 break;
 343         }
 344
 345         if (!pinctrl_state)
 346                 pinctrl_state = priv->default_pinctrl_state;
 347
 348         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 349                 if (pinctrl_state->iodelay)
 350                         late_recalibrate_iodelay(pinctrl_state->padconf,
 351                                                  pinctrl_state->npads,
 352                                                  pinctrl_state->iodelay,
 353                                                  pinctrl_state->niodelays);
 354                 else
 355                         do_set_mux32((*ctrl)->control_padconf_core_base,
 356                                      pinctrl_state->padconf,
 357                                      pinctrl_state->npads);
 358         }
 359 }
 360 #endif
 361 static void omap_hsmmc_set_timing(struct mmc *mmc)
 362 {
 363         u32 val;
 364         struct hsmmc *mmc_base;
 365         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 366
 367         mmc_base = priv->base_addr;
 368
 369         omap_hsmmc_stop_clock(mmc_base);
 370         val = readl(&mmc_base->ac12);
 371         val &= ~AC12_UHSMC_MASK;
 372         priv->mode = mmc->selected_mode;
 373
 374         if (mmc_is_mode_ddr(priv->mode))
 375                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 376         else
 377                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 378
 379         switch (priv->mode) {
 380         case MMC_HS_200:
 381         case UHS_SDR104:
 382                 val |= AC12_UHSMC_SDR104;
 383                 break;
 384         case UHS_SDR50:
 385                 val |= AC12_UHSMC_SDR50;
 386                 break;
 387         case MMC_DDR_52:
 388         case UHS_DDR50:
 389                 val |= AC12_UHSMC_DDR50;
 390                 break;
 391         case SD_HS:
 392         case MMC_HS_52:
 393         case UHS_SDR25:
 394                 val |= AC12_UHSMC_SDR25;
 395                 break;
 396         case MMC_LEGACY:
 397         case MMC_HS:
 398         case UHS_SDR12:
 399                 val |= AC12_UHSMC_SDR12;
 400                 break;
 401         default:
 402                 val |= AC12_UHSMC_RES;
 403                 break;
 404         }
 405         writel(val, &mmc_base->ac12);
 406
 407 #ifdef CONFIG_IODELAY_RECALIBRATION
 408         omap_hsmmc_io_recalibrate(mmc);
 409 #endif
 410         omap_hsmmc_start_clock(mmc_base);
 411 }
 412
 413 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 414 {
 415         struct hsmmc *mmc_base;
 416         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 417         u32 hctl, ac12;
 418
 419         mmc_base = priv->base_addr;
 420
 421         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 422         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 423
 424         switch (signal_voltage) {
 425         case MMC_SIGNAL_VOLTAGE_330:
 426                 hctl |= SDVS_3V3;
 427                 break;
 428         case MMC_SIGNAL_VOLTAGE_180:
 429                 hctl |= SDVS_1V8;
 430                 ac12 |= AC12_V1V8_SIGEN;
 431                 break;
 432         }
 433
 434         writel(hctl, &mmc_base->hctl);
 435         writel(ac12, &mmc_base->ac12);
 436 }
 437
 438 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 439 {
 440         int ret = -ETIMEDOUT;
 441         u32 con;
 442         bool dat0_high;
 443         bool target_dat0_high = !!state;
 444         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 445         struct hsmmc *mmc_base = priv->base_addr;
 446
 447         con = readl(&mmc_base->con);
 448         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 449
 450         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 451         while (timeout_us--) {
 452                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 453                 if (dat0_high == target_dat0_high) {
 454                         ret = 0;
 455                         break;
 456                 }
 457                 udelay(10);
 458         }
 459         writel(con, &mmc_base->con);
 460
 461         return ret;
 462 }
 463
 464 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 465 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 466 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 467 {
 468         int ret = 0;
 469         int uV = mV * 1000;
 470
 471         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 472
 473         if (!mmc->vqmmc_supply)
 474                 return 0;
 475
 476         /* Disable PBIAS */
 477         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 478         if (ret)
 479                 return ret;
 480
 481         /* Turn off IO voltage */
 482         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 483         if (ret)
 484                 return ret;
 485         /* Program a new IO voltage value */
 486         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 487         if (ret)
 488                 return ret;
 489         /* Turn on IO voltage */
 490         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 491         if (ret)
 492                 return ret;
 493
 494         /* Program PBIAS voltage*/
 495         ret = regulator_set_value(priv->pbias_supply, uV);
 496         if (ret && ret != -ENOSYS)
 497                 return ret;
 498         /* Enable PBIAS */
 499         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 500         if (ret)
 501                 return ret;
 502
 503         return 0;
 504 }
 505 #endif
 506
 507 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 508 {
 509         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 510         struct hsmmc *mmc_base = priv->base_addr;
 511         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 512         u32 capa_mask;
 513         __maybe_unused u8 palmas_ldo_volt;
 514         u32 val;
 515
 516         if (mv < 0)
 517                 return -EINVAL;
 518
 519         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 520                 mv = 3300;
 521                 capa_mask = VS33_3V3SUP;
 522                 palmas_ldo_volt = LDO_VOLT_3V3;
 523         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 524                 capa_mask = VS18_1V8SUP;
 525                 palmas_ldo_volt = LDO_VOLT_1V8;
 526         } else {
 527                 return -EOPNOTSUPP;
 528         }
 529
 530         val = readl(&mmc_base->capa);
 531         if (!(val & capa_mask))
 532                 return -EOPNOTSUPP;
 533
 534         priv->signal_voltage = mmc->signal_voltage;
 535
 536         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 537
 538 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 539         return omap_hsmmc_set_io_regulator(mmc, mv);
 540 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 541         defined(CONFIG_PALMAS_POWER)
 542         if (mmc_get_blk_desc(mmc)->devnum == 0)
 543                 vmmc_pbias_config(palmas_ldo_volt);
 544         return 0;
 545 #else
 546         return 0;
 547 #endif
 548 }
 549 #endif
 550
 551 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 552 {
 553         struct hsmmc *mmc_base;
 554         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 555         u32 val;
 556
 557         mmc_base = priv->base_addr;
 558         val = readl(&mmc_base->capa);
 559
 560         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 561                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 562         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 563                 val |= VS33_3V3SUP;
 564                 val &= ~VS18_1V8SUP;
 565         } else {
 566                 val |= VS18_1V8SUP;
 567                 val &= ~VS33_3V3SUP;
 568         }
 569
 570         writel(val, &mmc_base->capa);
 571
 572         return val;
 573 }
 574
 575 #ifdef MMC_SUPPORTS_TUNING
 576 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 577 {
 578         struct hsmmc *mmc_base;
 579         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 580         u32 val;
 581
 582         mmc_base = priv->base_addr;
 583         val = readl(&mmc_base->ac12);
 584         val &= ~(AC12_SCLK_SEL);
 585         writel(val, &mmc_base->ac12);
 586
 587         val = readl(&mmc_base->dll);
 588         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 589         writel(val, &mmc_base->dll);
 590 }
 591
 592 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 593 {
 594         int i;
 595         struct hsmmc *mmc_base;
 596         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 597         u32 val;
 598
 599         mmc_base = priv->base_addr;
 600         val = readl(&mmc_base->dll);
 601         val |= DLL_FORCE_VALUE;
 602         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 603         val |= (count << DLL_FORCE_SR_C_SHIFT);
 604         writel(val, &mmc_base->dll);
 605
 606         val |= DLL_CALIB;
 607         writel(val, &mmc_base->dll);
 608         for (i = 0; i < 1000; i++) {
 609                 if (readl(&mmc_base->dll) & DLL_CALIB)
 610                         break;
 611         }
 612         val &= ~DLL_CALIB;
 613         writel(val, &mmc_base->dll);
 614 }
 615
 616 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 617 {
 618         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 619         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 620         struct mmc *mmc = upriv->mmc;
 621         struct hsmmc *mmc_base;
 622         u32 val;
 623         u8 cur_match, prev_match = 0;
 624         int ret;
 625         u32 phase_delay = 0;
 626         u32 start_window = 0, max_window = 0;
 627         u32 length = 0, max_len = 0;
 628         bool single_point_failure = false;
 629         struct udevice *thermal_dev;
 630         int temperature;
 631         int i;
 632
 633         mmc_base = priv->base_addr;
 634         val = readl(&mmc_base->capa2);
 635
 636         /* clock tuning is not needed for upto 52MHz */
 637         if (!((mmc->selected_mode == MMC_HS_200) ||
 638               (mmc->selected_mode == UHS_SDR104) ||
 639               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 640                 return 0;
 641
 642         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 643         if (ret) {
 644                 printf("Couldn't get thermal device for tuning\n");
 645                 return ret;
 646         }
 647         ret = thermal_get_temp(thermal_dev, &temperature);
 648         if (ret) {
 649                 printf("Couldn't get temperature for tuning\n");
 650                 return ret;
 651         }
 652         val = readl(&mmc_base->dll);
 653         val |= DLL_SWT;
 654         writel(val, &mmc_base->dll);
 655
 656         /*
 657          * Stage 1: Search for a maximum pass window ignoring any
 658          * any single point failures. If the tuning value ends up
 659          * near it, move away from it in stage 2 below
 660          */
 661         while (phase_delay <= MAX_PHASE_DELAY) {
 662                 omap_hsmmc_set_dll(mmc, phase_delay);
 663
 664                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 665
 666                 if (cur_match) {
 667                         if (prev_match) {
 668                                 length++;
 669                         } else if (single_point_failure) {
 670                                 /* ignore single point failure */
 671                                 length++;
 672                                 single_point_failure = false;
 673                         } else {
 674                                 start_window = phase_delay;
 675                                 length = 1;
 676                         }
 677                 } else {
 678                         single_point_failure = prev_match;
 679                 }
 680
 681                 if (length > max_len) {
 682                         max_window = start_window;
 683                         max_len = length;
 684                 }
 685
 686                 prev_match = cur_match;
 687                 phase_delay += 4;
 688         }
 689
 690         if (!max_len) {
 691                 ret = -EIO;
 692                 goto tuning_error;
 693         }
 694
 695         val = readl(&mmc_base->ac12);
 696         if (!(val & AC12_SCLK_SEL)) {
 697                 ret = -EIO;
 698                 goto tuning_error;
 699         }
 700         /*
 701          * Assign tuning value as a ratio of maximum pass window based
 702          * on temperature
 703          */
 704         if (temperature < -20000)
 705                 phase_delay = min(max_window + 4 * max_len - 24,
 706                                   max_window +
 707                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 708         else if (temperature < 20000)
 709                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 710         else if (temperature < 40000)
 711                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 712         else if (temperature < 70000)
 713                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 714         else if (temperature < 90000)
 715                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 716         else if (temperature < 120000)
 717                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 718         else
 719                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 720
 721         /*
 722          * Stage 2: Search for a single point failure near the chosen tuning
 723          * value in two steps. First in the +3 to +10 range and then in the
 724          * +2 to -10 range. If found, move away from it in the appropriate
 725          * direction by the appropriate amount depending on the temperature.
 726          */
 727         for (i = 3; i <= 10; i++) {
 728                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 729                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 730                         if (temperature < 10000)
 731                                 phase_delay += i + 6;
 732                         else if (temperature < 20000)
 733                                 phase_delay += i - 12;
 734                         else if (temperature < 70000)
 735                                 phase_delay += i - 8;
 736                         else if (temperature < 90000)
 737                                 phase_delay += i - 6;
 738                         else
 739                                 phase_delay += i - 6;
 740
 741                         goto single_failure_found;
 742                 }
 743         }
 744
 745         for (i = 2; i >= -10; i--) {
 746                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 747                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 748                         if (temperature < 10000)
 749                                 phase_delay += i + 12;
 750                         else if (temperature < 20000)
 751                                 phase_delay += i + 8;
 752                         else if (temperature < 70000)
 753                                 phase_delay += i + 8;
 754                         else if (temperature < 90000)
 755                                 phase_delay += i + 10;
 756                         else
 757                                 phase_delay += i + 12;
 758
 759                         goto single_failure_found;
 760                 }
 761         }
 762
 763 single_failure_found:
 764
 765         omap_hsmmc_set_dll(mmc, phase_delay);
 766
 767         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 768         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 769
 770         return 0;
 771
 772 tuning_error:
 773
 774         omap_hsmmc_disable_tuning(mmc);
 775         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 776         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 777
 778         return ret;
 779 }
 780 #endif
 781 #endif
 782
 783 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 784 {
 785         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 786         struct hsmmc *mmc_base = priv->base_addr;
 787         u32 irq_mask = INT_EN_MASK;
 788
 789         /*
 790          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 791          * tuning procedure and DCRC should be disabled. But see occurences
 792          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 793          * interrupts occur along with BRR, so the data is actually in the
 794          * buffer. It has to be debugged why these interrutps occur
 795          */
 796         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 797                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 798
 799         writel(irq_mask, &mmc_base->ie);
 800 }
 801
 802 static int omap_hsmmc_init_setup(struct mmc *mmc)
 803 {
 804         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 805         struct hsmmc *mmc_base;
 806         unsigned int reg_val;
 807         unsigned int dsor;
 808         ulong start;
 809
 810         mmc_base = priv->base_addr;
 811         mmc_board_init(mmc);
 812
 813         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 814                 &mmc_base->sysconfig);
 815         start = get_timer(0);
 816         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 817                 if (get_timer(0) - start > MAX_RETRY_MS) {
 818                         printf("%s: timedout waiting for cc2!\n", __func__);
 819                         return -ETIMEDOUT;
 820                 }
 821         }
 822         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 823         start = get_timer(0);
 824         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 825                 if (get_timer(0) - start > MAX_RETRY_MS) {
 826                         printf("%s: timedout waiting for softresetall!\n",
 827                                 __func__);
 828                         return -ETIMEDOUT;
 829                 }
 830         }
 831 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 832         reg_val = readl(&mmc_base->hl_hwinfo);
 833         if (reg_val & MADMA_EN)
 834                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 835 #endif
 836
 837 #if CONFIG_IS_ENABLED(DM_MMC)
 838         reg_val = omap_hsmmc_set_capabilities(mmc);
 839         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 840                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 841 #else
 842         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 843         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 844                 &mmc_base->capa);
 845 #endif
 846
 847         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 848
 849         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 850                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 851                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 852
 853         dsor = 240;
 854         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 855                 (ICE_STOP | DTO_15THDTO));
 856         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 857                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 858         start = get_timer(0);
 859         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 860                 if (get_timer(0) - start > MAX_RETRY_MS) {
 861                         printf("%s: timedout waiting for ics!\n", __func__);
 862                         return -ETIMEDOUT;
 863                 }
 864         }
 865         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 866
 867         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 868
 869         mmc_enable_irq(mmc, NULL);
 870
 871 #if !CONFIG_IS_ENABLED(DM_MMC)
 872         mmc_init_stream(mmc_base);
 873 #endif
 874
 875         return 0;
 876 }
 877
 878 /*
 879  * MMC controller internal finite state machine reset
 880  *
 881  * Used to reset command or data internal state machines, using respectively
 882  * SRC or SRD bit of SYSCTL register
 883  */
 884 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 885 {
 886         ulong start;
 887
 888         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 889
 890         /*
 891          * CMD(DAT) lines reset procedures are slightly different
 892          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 893          * According to OMAP3 TRM:
 894          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 895          * returns to 0x0.
 896          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 897          * procedure steps must be as follows:
 898          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 899          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 900          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 901          * 3. Wait until the SRC (SRD) bit returns to 0x0
 902          *    (reset procedure is completed).
 903          */
 904 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 905         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 906         if (!(readl(&mmc_base->sysctl) & bit)) {
 907                 start = get_timer(0);
 908                 while (!(readl(&mmc_base->sysctl) & bit)) {
 909                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 910                                 return;
 911                 }
 912         }
 913 #endif
 914         start = get_timer(0);
 915         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 916                 if (get_timer(0) - start > MAX_RETRY_MS) {
 917                         printf("%s: timedout waiting for sysctl %x to clear\n",
 918                                 __func__, bit);
 919                         return;
 920                 }
 921         }
 922 }
 923
 924 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 925 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 926 {
 927         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 928         struct omap_hsmmc_adma_desc *desc;
 929         u8 attr;
 930
 931         desc = &priv->adma_desc_table[priv->desc_slot];
 932
 933         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 934         if (!end)
 935                 priv->desc_slot++;
 936         else
 937                 attr |= ADMA_DESC_ATTR_END;
 938
 939         desc->len = len;
 940         desc->addr = (u32)buf;
 941         desc->reserved = 0;
 942         desc->attr = attr;
 943 }
 944
 945 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 946                                           struct mmc_data *data)
 947 {
 948         uint total_len = data->blocksize * data->blocks;
 949         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 950         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 951         int i = desc_count;
 952         char *buf;
 953
 954         priv->desc_slot = 0;
 955         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 956                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 957                                 sizeof(struct omap_hsmmc_adma_desc));
 958
 959         if (data->flags & MMC_DATA_READ)
 960                 buf = data->dest;
 961         else
 962                 buf = (char *)data->src;
 963
 964         while (--i) {
 965                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 966                 buf += ADMA_MAX_LEN;
 967                 total_len -= ADMA_MAX_LEN;
 968         }
 969
 970         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 971
 972         flush_dcache_range((long)priv->adma_desc_table,
 973                            (long)priv->adma_desc_table +
 974                            ROUND(desc_count *
 975                            sizeof(struct omap_hsmmc_adma_desc),
 976                            ARCH_DMA_MINALIGN));
 977 }
 978
 979 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 980 {
 981         struct hsmmc *mmc_base;
 982         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 983         u32 val;
 984         char *buf;
 985
 986         mmc_base = priv->base_addr;
 987         omap_hsmmc_prepare_adma_table(mmc, data);
 988
 989         if (data->flags & MMC_DATA_READ)
 990                 buf = data->dest;
 991         else
 992                 buf = (char *)data->src;
 993
 994         val = readl(&mmc_base->hctl);
 995         val |= DMA_SELECT;
 996         writel(val, &mmc_base->hctl);
 997
 998         val = readl(&mmc_base->con);
 999         val |= DMA_MASTER;
1000         writel(val, &mmc_base->con);
1001
1002         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1003
1004         flush_dcache_range((u32)buf,
1005                            (u32)buf +
1006                            ROUND(data->blocksize * data->blocks,
1007                                  ARCH_DMA_MINALIGN));
1008 }
1009
1010 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1011 {
1012         struct hsmmc *mmc_base;
1013         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1014         u32 val;
1015
1016         mmc_base = priv->base_addr;
1017
1018         val = readl(&mmc_base->con);
1019         val &= ~DMA_MASTER;
1020         writel(val, &mmc_base->con);
1021
1022         val = readl(&mmc_base->hctl);
1023         val &= ~DMA_SELECT;
1024         writel(val, &mmc_base->hctl);
1025
1026         kfree(priv->adma_desc_table);
1027 }
1028 #else
1029 #define omap_hsmmc_adma_desc
1030 #define omap_hsmmc_prepare_adma_table
1031 #define omap_hsmmc_prepare_data
1032 #define omap_hsmmc_dma_cleanup
1033 #endif
1034
1035 #if !CONFIG_IS_ENABLED(DM_MMC)
1036 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1037                         struct mmc_data *data)
1038 {
1039         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1040 #else
1041 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1042                         struct mmc_data *data)
1043 {
1044         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1045         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1046         struct mmc *mmc = upriv->mmc;
1047 #endif
1048         struct hsmmc *mmc_base;
1049         unsigned int flags, mmc_stat;
1050         ulong start;
1051         priv->last_cmd = cmd->cmdidx;
1052
1053         mmc_base = priv->base_addr;
1054
1055         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1056                 return 0;
1057
1058         start = get_timer(0);
1059         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1060                 if (get_timer(0) - start > MAX_RETRY_MS) {
1061                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1062                                         __func__);
1063                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1064                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1065                         return -ETIMEDOUT;
1066                 }
1067         }
1068         writel(0xFFFFFFFF, &mmc_base->stat);
1069         if (readl(&mmc_base->stat)) {
1070                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1071                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1072         }
1073
1074         /*
1075          * CMDREG
1076          * CMDIDX[13:8] : Command index
1077          * DATAPRNT[5]  : Data Present Select
1078          * ENCMDIDX[4]  : Command Index Check Enable
1079          * ENCMDCRC[3]  : Command CRC Check Enable
1080          * RSPTYP[1:0]
1081          *      00 = No Response
1082          *      01 = Length 136
1083          *      10 = Length 48
1084          *      11 = Length 48 Check busy after response
1085          */
1086         /* Delay added before checking the status of frq change
1087          * retry not supported by mmc.c(core file)
1088          */
1089         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1090                 udelay(50000); /* wait 50 ms */
1091
1092         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1093                 flags = 0;
1094         else if (cmd->resp_type & MMC_RSP_136)
1095                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1096         else if (cmd->resp_type & MMC_RSP_BUSY)
1097                 flags = RSP_TYPE_LGHT48B;
1098         else
1099                 flags = RSP_TYPE_LGHT48;
1100
1101         /* enable default flags */
1102         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1103                         MSBS_SGLEBLK);
1104         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1105
1106         if (cmd->resp_type & MMC_RSP_CRC)
1107                 flags |= CCCE_CHECK;
1108         if (cmd->resp_type & MMC_RSP_OPCODE)
1109                 flags |= CICE_CHECK;
1110
1111         if (data) {
1112                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1113                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1114                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1115                         data->blocksize = 512;
1116                         writel(data->blocksize | (data->blocks << 16),
1117                                                         &mmc_base->blk);
1118                 } else
1119                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1120
1121                 if (data->flags & MMC_DATA_READ)
1122                         flags |= (DP_DATA | DDIR_READ);
1123                 else
1124                         flags |= (DP_DATA | DDIR_WRITE);
1125
1126 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1127                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1128                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1129                         omap_hsmmc_prepare_data(mmc, data);
1130                         flags |= DE_ENABLE;
1131                 }
1132 #endif
1133         }
1134
1135         mmc_enable_irq(mmc, cmd);
1136
1137         writel(cmd->cmdarg, &mmc_base->arg);
1138         udelay(20);             /* To fix "No status update" error on eMMC */
1139         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1140
1141         start = get_timer(0);
1142         do {
1143                 mmc_stat = readl(&mmc_base->stat);
1144                 if (get_timer(start) > MAX_RETRY_MS) {
1145                         printf("%s : timeout: No status update\n", __func__);
1146                         return -ETIMEDOUT;
1147                 }
1148         } while (!mmc_stat);
1149
1150         if ((mmc_stat & IE_CTO) != 0) {
1151                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1152                 return -ETIMEDOUT;
1153         } else if ((mmc_stat & ERRI_MASK) != 0)
1154                 return -1;
1155
1156         if (mmc_stat & CC_MASK) {
1157                 writel(CC_MASK, &mmc_base->stat);
1158                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1159                         if (cmd->resp_type & MMC_RSP_136) {
1160                                 /* response type 2 */
1161                                 cmd->response[3] = readl(&mmc_base->rsp10);
1162                                 cmd->response[2] = readl(&mmc_base->rsp32);
1163                                 cmd->response[1] = readl(&mmc_base->rsp54);
1164                                 cmd->response[0] = readl(&mmc_base->rsp76);
1165                         } else
1166                                 /* response types 1, 1b, 3, 4, 5, 6 */
1167                                 cmd->response[0] = readl(&mmc_base->rsp10);
1168                 }
1169         }
1170
1171 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1172         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1173             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1174                 u32 sz_mb, timeout;
1175
1176                 if (mmc_stat & IE_ADMAE) {
1177                         omap_hsmmc_dma_cleanup(mmc);
1178                         return -EIO;
1179                 }
1180
1181                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1182                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1183                 if (timeout < MAX_RETRY_MS)
1184                         timeout = MAX_RETRY_MS;
1185
1186                 start = get_timer(0);
1187                 do {
1188                         mmc_stat = readl(&mmc_base->stat);
1189                         if (mmc_stat & TC_MASK) {
1190                                 writel(readl(&mmc_base->stat) | TC_MASK,
1191                                        &mmc_base->stat);
1192                                 break;
1193                         }
1194                         if (get_timer(start) > timeout) {
1195                                 printf("%s : DMA timeout: No status update\n",
1196                                        __func__);
1197                                 return -ETIMEDOUT;
1198                         }
1199                 } while (1);
1200
1201                 omap_hsmmc_dma_cleanup(mmc);
1202                 return 0;
1203         }
1204 #endif
1205
1206         if (data && (data->flags & MMC_DATA_READ)) {
1207                 mmc_read_data(mmc_base, data->dest,
1208                                 data->blocksize * data->blocks);
1209         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1210                 mmc_write_data(mmc_base, data->src,
1211                                 data->blocksize * data->blocks);
1212         }
1213         return 0;
1214 }
1215
1216 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1217 {
1218         unsigned int *output_buf = (unsigned int *)buf;
1219         unsigned int mmc_stat;
1220         unsigned int count;
1221
1222         /*
1223          * Start Polled Read
1224          */
1225         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1226         count /= 4;
1227
1228         while (size) {
1229                 ulong start = get_timer(0);
1230                 do {
1231                         mmc_stat = readl(&mmc_base->stat);
1232                         if (get_timer(0) - start > MAX_RETRY_MS) {
1233                                 printf("%s: timedout waiting for status!\n",
1234                                                 __func__);
1235                                 return -ETIMEDOUT;
1236                         }
1237                 } while (mmc_stat == 0);
1238
1239                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1240                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1241
1242                 if ((mmc_stat & ERRI_MASK) != 0)
1243                         return 1;
1244
1245                 if (mmc_stat & BRR_MASK) {
1246                         unsigned int k;
1247
1248                         writel(readl(&mmc_base->stat) | BRR_MASK,
1249                                 &mmc_base->stat);
1250                         for (k = 0; k < count; k++) {
1251                                 *output_buf = readl(&mmc_base->data);
1252                                 output_buf++;
1253                         }
1254                         size -= (count*4);
1255                 }
1256
1257                 if (mmc_stat & BWR_MASK)
1258                         writel(readl(&mmc_base->stat) | BWR_MASK,
1259                                 &mmc_base->stat);
1260
1261                 if (mmc_stat & TC_MASK) {
1262                         writel(readl(&mmc_base->stat) | TC_MASK,
1263                                 &mmc_base->stat);
1264                         break;
1265                 }
1266         }
1267         return 0;
1268 }
1269
1270 #if CONFIG_IS_ENABLED(MMC_WRITE)
1271 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1272                           unsigned int size)
1273 {
1274         unsigned int *input_buf = (unsigned int *)buf;
1275         unsigned int mmc_stat;
1276         unsigned int count;
1277
1278         /*
1279          * Start Polled Write
1280          */
1281         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1282         count /= 4;
1283
1284         while (size) {
1285                 ulong start = get_timer(0);
1286                 do {
1287                         mmc_stat = readl(&mmc_base->stat);
1288                         if (get_timer(0) - start > MAX_RETRY_MS) {
1289                                 printf("%s: timedout waiting for status!\n",
1290                                                 __func__);
1291                                 return -ETIMEDOUT;
1292                         }
1293                 } while (mmc_stat == 0);
1294
1295                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1296                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1297
1298                 if ((mmc_stat & ERRI_MASK) != 0)
1299                         return 1;
1300
1301                 if (mmc_stat & BWR_MASK) {
1302                         unsigned int k;
1303
1304                         writel(readl(&mmc_base->stat) | BWR_MASK,
1305                                         &mmc_base->stat);
1306                         for (k = 0; k < count; k++) {
1307                                 writel(*input_buf, &mmc_base->data);
1308                                 input_buf++;
1309                         }
1310                         size -= (count*4);
1311                 }
1312
1313                 if (mmc_stat & BRR_MASK)
1314                         writel(readl(&mmc_base->stat) | BRR_MASK,
1315                                 &mmc_base->stat);
1316
1317                 if (mmc_stat & TC_MASK) {
1318                         writel(readl(&mmc_base->stat) | TC_MASK,
1319                                 &mmc_base->stat);
1320                         break;
1321                 }
1322         }
1323         return 0;
1324 }
1325 #else
1326 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1327                           unsigned int size)
1328 {
1329         return -ENOTSUPP;
1330 }
1331 #endif
1332 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1333 {
1334         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1335 }
1336
1337 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1338 {
1339         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1340 }
1341
1342 static void omap_hsmmc_set_clock(struct mmc *mmc)
1343 {
1344         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1345         struct hsmmc *mmc_base;
1346         unsigned int dsor = 0;
1347         ulong start;
1348
1349         mmc_base = priv->base_addr;
1350         omap_hsmmc_stop_clock(mmc_base);
1351
1352         /* TODO: Is setting DTO required here? */
1353         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1354                     (ICE_STOP | DTO_15THDTO));
1355
1356         if (mmc->clock != 0) {
1357                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1358                 if (dsor > CLKD_MAX)
1359                         dsor = CLKD_MAX;
1360         } else {
1361                 dsor = CLKD_MAX;
1362         }
1363
1364         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1365                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1366
1367         start = get_timer(0);
1368         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1369                 if (get_timer(0) - start > MAX_RETRY_MS) {
1370                         printf("%s: timedout waiting for ics!\n", __func__);
1371                         return;
1372                 }
1373         }
1374
1375         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1376         mmc->clock = priv->clock;
1377         omap_hsmmc_start_clock(mmc_base);
1378 }
1379
1380 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1381 {
1382         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1383         struct hsmmc *mmc_base;
1384
1385         mmc_base = priv->base_addr;
1386         /* configue bus width */
1387         switch (mmc->bus_width) {
1388         case 8:
1389                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1390                         &mmc_base->con);
1391                 break;
1392
1393         case 4:
1394                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1395                         &mmc_base->con);
1396                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1397                         &mmc_base->hctl);
1398                 break;
1399
1400         case 1:
1401         default:
1402                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1403                         &mmc_base->con);
1404                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1405                         &mmc_base->hctl);
1406                 break;
1407         }
1408
1409         priv->bus_width = mmc->bus_width;
1410 }
1411
1412 #if !CONFIG_IS_ENABLED(DM_MMC)
1413 static int omap_hsmmc_set_ios(struct mmc *mmc)
1414 {
1415         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1416 #else
1417 static int omap_hsmmc_set_ios(struct udevice *dev)
1418 {
1419         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1420         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1421         struct mmc *mmc = upriv->mmc;
1422 #endif
1423         struct hsmmc *mmc_base = priv->base_addr;
1424         int ret = 0;
1425
1426         if (priv->bus_width != mmc->bus_width)
1427                 omap_hsmmc_set_bus_width(mmc);
1428
1429         if (priv->clock != mmc->clock)
1430                 omap_hsmmc_set_clock(mmc);
1431
1432         if (mmc->clk_disable)
1433                 omap_hsmmc_stop_clock(mmc_base);
1434         else
1435                 omap_hsmmc_start_clock(mmc_base);
1436
1437 #if CONFIG_IS_ENABLED(DM_MMC)
1438         if (priv->mode != mmc->selected_mode)
1439                 omap_hsmmc_set_timing(mmc);
1440
1441 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1442         if (priv->signal_voltage != mmc->signal_voltage)
1443                 ret = omap_hsmmc_set_signal_voltage(mmc);
1444 #endif
1445 #endif
1446         return ret;
1447 }
1448
1449 #ifdef OMAP_HSMMC_USE_GPIO
1450 #if CONFIG_IS_ENABLED(DM_MMC)
1451 static int omap_hsmmc_getcd(struct udevice *dev)
1452 {
1453         int value = -1;
1454 #if CONFIG_IS_ENABLED(DM_GPIO)
1455         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1456         value = dm_gpio_get_value(&priv->cd_gpio);
1457 #endif
1458         /* if no CD return as 1 */
1459         if (value < 0)
1460                 return 1;
1461
1462         return value;
1463 }
1464
1465 static int omap_hsmmc_getwp(struct udevice *dev)
1466 {
1467         int value = 0;
1468 #if CONFIG_IS_ENABLED(DM_GPIO)
1469         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1470         value = dm_gpio_get_value(&priv->wp_gpio);
1471 #endif
1472         /* if no WP return as 0 */
1473         if (value < 0)
1474                 return 0;
1475         return value;
1476 }
1477 #else
1478 static int omap_hsmmc_getcd(struct mmc *mmc)
1479 {
1480         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1481         int cd_gpio;
1482
1483         /* if no CD return as 1 */
1484         cd_gpio = priv->cd_gpio;
1485         if (cd_gpio < 0)
1486                 return 1;
1487
1488         /* NOTE: assumes card detect signal is active-low */
1489         return !gpio_get_value(cd_gpio);
1490 }
1491
1492 static int omap_hsmmc_getwp(struct mmc *mmc)
1493 {
1494         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1495         int wp_gpio;
1496
1497         /* if no WP return as 0 */
1498         wp_gpio = priv->wp_gpio;
1499         if (wp_gpio < 0)
1500                 return 0;
1501
1502         /* NOTE: assumes write protect signal is active-high */
1503         return gpio_get_value(wp_gpio);
1504 }
1505 #endif
1506 #endif
1507
1508 #if CONFIG_IS_ENABLED(DM_MMC)
1509 static const struct dm_mmc_ops omap_hsmmc_ops = {
1510         .send_cmd       = omap_hsmmc_send_cmd,
1511         .set_ios        = omap_hsmmc_set_ios,
1512 #ifdef OMAP_HSMMC_USE_GPIO
1513         .get_cd         = omap_hsmmc_getcd,
1514         .get_wp         = omap_hsmmc_getwp,
1515 #endif
1516 #ifdef MMC_SUPPORTS_TUNING
1517         .execute_tuning = omap_hsmmc_execute_tuning,
1518 #endif
1519         .wait_dat0      = omap_hsmmc_wait_dat0,
1520 };
1521 #else
1522 static const struct mmc_ops omap_hsmmc_ops = {
1523         .send_cmd       = omap_hsmmc_send_cmd,
1524         .set_ios        = omap_hsmmc_set_ios,
1525         .init           = omap_hsmmc_init_setup,
1526 #ifdef OMAP_HSMMC_USE_GPIO
1527         .getcd          = omap_hsmmc_getcd,
1528         .getwp          = omap_hsmmc_getwp,
1529 #endif
1530 };
1531 #endif
1532
1533 #if !CONFIG_IS_ENABLED(DM_MMC)
1534 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1535                 int wp_gpio)
1536 {
1537         struct mmc *mmc;
1538         struct omap_hsmmc_data *priv;
1539         struct mmc_config *cfg;
1540         uint host_caps_val;
1541
1542         priv = calloc(1, sizeof(*priv));
1543         if (priv == NULL)
1544                 return -1;
1545
1546         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1547
1548         switch (dev_index) {
1549         case 0:
1550                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1551                 break;
1552 #ifdef OMAP_HSMMC2_BASE
1553         case 1:
1554                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1555 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1556         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1557         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1558                 defined(CONFIG_HSMMC2_8BIT)
1559                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1560                 host_caps_val |= MMC_MODE_8BIT;
1561 #endif
1562                 break;
1563 #endif
1564 #ifdef OMAP_HSMMC3_BASE
1565         case 2:
1566                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1567 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1568                 /* Enable 8-bit interface for eMMC on DRA7XX */
1569                 host_caps_val |= MMC_MODE_8BIT;
1570 #endif
1571                 break;
1572 #endif
1573         default:
1574                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1575                 return 1;
1576         }
1577 #ifdef OMAP_HSMMC_USE_GPIO
1578         /* on error gpio values are set to -1, which is what we want */
1579         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1580         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1581 #endif
1582
1583         cfg = &priv->cfg;
1584
1585         cfg->name = "OMAP SD/MMC";
1586         cfg->ops = &omap_hsmmc_ops;
1587
1588         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1589         cfg->host_caps = host_caps_val & ~host_caps_mask;
1590
1591         cfg->f_min = 400000;
1592
1593         if (f_max != 0)
1594                 cfg->f_max = f_max;
1595         else {
1596                 if (cfg->host_caps & MMC_MODE_HS) {
1597                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1598                                 cfg->f_max = 52000000;
1599                         else
1600                                 cfg->f_max = 26000000;
1601                 } else
1602                         cfg->f_max = 20000000;
1603         }
1604
1605         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1606
1607 #if defined(CONFIG_OMAP34XX)
1608         /*
1609          * Silicon revs 2.1 and older do not support multiblock transfers.
1610          */
1611         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1612                 cfg->b_max = 1;
1613 #endif
1614
1615         mmc = mmc_create(cfg, priv);
1616         if (mmc == NULL)
1617                 return -1;
1618
1619         return 0;
1620 }
1621 #else
1622
1623 #ifdef CONFIG_IODELAY_RECALIBRATION
1624 static struct pad_conf_entry *
1625 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1626 {
1627         int index = 0;
1628         struct pad_conf_entry *padconf;
1629
1630         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1631         if (!padconf) {
1632                 debug("failed to allocate memory\n");
1633                 return 0;
1634         }
1635
1636         while (index < count) {
1637                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1638                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1639                 index++;
1640         }
1641
1642         return padconf;
1643 }
1644
1645 static struct iodelay_cfg_entry *
1646 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1647 {
1648         int index = 0;
1649         struct iodelay_cfg_entry *iodelay;
1650
1651         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1652         if (!iodelay) {
1653                 debug("failed to allocate memory\n");
1654                 return 0;
1655         }
1656
1657         while (index < count) {
1658                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1659                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1660                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1661                 index++;
1662         }
1663
1664         return iodelay;
1665 }
1666
1667 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1668                                                    const char *name, int *len)
1669 {
1670         const void *fdt = gd->fdt_blob;
1671         int offset;
1672         const fdt32_t *pinctrl;
1673
1674         offset = fdt_node_offset_by_phandle(fdt, phandle);
1675         if (offset < 0) {
1676                 debug("failed to get pinctrl node %s.\n",
1677                       fdt_strerror(offset));
1678                 return 0;
1679         }
1680
1681         pinctrl = fdt_getprop(fdt, offset, name, len);
1682         if (!pinctrl) {
1683                 debug("failed to get property %s\n", name);
1684                 return 0;
1685         }
1686
1687         return pinctrl;
1688 }
1689
1690 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1691                                                 char *prop_name)
1692 {
1693         const void *fdt = gd->fdt_blob;
1694         const __be32 *phandle;
1695         int node = dev_of_offset(mmc->dev);
1696
1697         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1698         if (!phandle) {
1699                 debug("failed to get property %s\n", prop_name);
1700                 return 0;
1701         }
1702
1703         return fdt32_to_cpu(*phandle);
1704 }
1705
1706 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1707                                                char *prop_name)
1708 {
1709         const void *fdt = gd->fdt_blob;
1710         const __be32 *phandle;
1711         int len;
1712         int count;
1713         int node = dev_of_offset(mmc->dev);
1714
1715         phandle = fdt_getprop(fdt, node, prop_name, &len);
1716         if (!phandle) {
1717                 debug("failed to get property %s\n", prop_name);
1718                 return 0;
1719         }
1720
1721         /* No manual mode iodelay values if count < 2 */
1722         count = len / sizeof(*phandle);
1723         if (count < 2)
1724                 return 0;
1725
1726         return fdt32_to_cpu(*(phandle + 1));
1727 }
1728
1729 static struct pad_conf_entry *
1730 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1731 {
1732         int len;
1733         int count;
1734         struct pad_conf_entry *padconf;
1735         u32 phandle;
1736         const fdt32_t *pinctrl;
1737
1738         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1739         if (!phandle)
1740                 return ERR_PTR(-EINVAL);
1741
1742         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1743                                                &len);
1744         if (!pinctrl)
1745                 return ERR_PTR(-EINVAL);
1746
1747         count = (len / sizeof(*pinctrl)) / 2;
1748         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1749         if (!padconf)
1750                 return ERR_PTR(-EINVAL);
1751
1752         *npads = count;
1753
1754         return padconf;
1755 }
1756
1757 static struct iodelay_cfg_entry *
1758 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1759 {
1760         int len;
1761         int count;
1762         struct iodelay_cfg_entry *iodelay;
1763         u32 phandle;
1764         const fdt32_t *pinctrl;
1765
1766         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1767         /* Not all modes have manual mode iodelay values. So its not fatal */
1768         if (!phandle)
1769                 return 0;
1770
1771         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1772                                                &len);
1773         if (!pinctrl)
1774                 return ERR_PTR(-EINVAL);
1775
1776         count = (len / sizeof(*pinctrl)) / 3;
1777         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1778         if (!iodelay)
1779                 return ERR_PTR(-EINVAL);
1780
1781         *niodelay = count;
1782
1783         return iodelay;
1784 }
1785
1786 static struct omap_hsmmc_pinctrl_state *
1787 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1788 {
1789         int index;
1790         int npads = 0;
1791         int niodelays = 0;
1792         const void *fdt = gd->fdt_blob;
1793         int node = dev_of_offset(mmc->dev);
1794         char prop_name[11];
1795         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1796
1797         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1798                          malloc(sizeof(*pinctrl_state));
1799         if (!pinctrl_state) {
1800                 debug("failed to allocate memory\n");
1801                 return 0;
1802         }
1803
1804         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1805         if (index < 0) {
1806                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1807                 goto err_pinctrl_state;
1808         }
1809
1810         sprintf(prop_name, "pinctrl-%d", index);
1811
1812         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1813                                                          &npads);
1814         if (IS_ERR(pinctrl_state->padconf))
1815                 goto err_pinctrl_state;
1816         pinctrl_state->npads = npads;
1817
1818         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1819                                                         &niodelays);
1820         if (IS_ERR(pinctrl_state->iodelay))
1821                 goto err_padconf;
1822         pinctrl_state->niodelays = niodelays;
1823
1824         return pinctrl_state;
1825
1826 err_padconf:
1827         kfree(pinctrl_state->padconf);
1828
1829 err_pinctrl_state:
1830         kfree(pinctrl_state);
1831         return 0;
1832 }
1833
1834 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1835         do {                                                            \
1836                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1837                 char str[20];                                           \
1838                 if (!(cfg->host_caps & capmask))                        \
1839                         break;                                          \
1840                                                                         \
1841                 if (priv->hw_rev) {                                     \
1842                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1843                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1844                 }                                                       \
1845                                                                         \
1846                 if (!s)                                                 \
1847                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1848                                                                         \
1849                 if (!s && !optional) {                                  \
1850                         debug("%s: no pinctrl for %s\n",                \
1851                               mmc->dev->name, #mode);                   \
1852                         cfg->host_caps &= ~(capmask);                   \
1853                 } else {                                                \
1854                         priv->mode##_pinctrl_state = s;                 \
1855                 }                                                       \
1856         } while (0)
1857
1858 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1859 {
1860         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1861         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1862         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1863
1864         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1865                 return 0;
1866
1867         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1868         if (!default_pinctrl) {
1869                 printf("no pinctrl state for default mode\n");
1870                 return -EINVAL;
1871         }
1872
1873         priv->default_pinctrl_state = default_pinctrl;
1874
1875         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1876         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1877         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1878         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1879         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1880
1881         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1882         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1883         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1884
1885         return 0;
1886 }
1887 #endif
1888
1889 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1890 #ifdef CONFIG_OMAP54XX
1891 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1892 {
1893         return NULL;
1894 }
1895 #endif
1896
1897 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1898 {
1899         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1900         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1901
1902         struct mmc_config *cfg = &plat->cfg;
1903 #ifdef CONFIG_OMAP54XX
1904         const struct mmc_platform_fixups *fixups;
1905 #endif
1906         const void *fdt = gd->fdt_blob;
1907         int node = dev_of_offset(dev);
1908         int ret;
1909
1910         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1911                                       sizeof(struct hsmmc *),
1912                                       MAP_NOCACHE);
1913
1914         ret = mmc_of_parse(dev, cfg);
1915         if (ret < 0)
1916                 return ret;
1917
1918         if (!cfg->f_max)
1919                 cfg->f_max = 52000000;
1920         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1921         cfg->f_min = 400000;
1922         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1923         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1924         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1925                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1926         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1927                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1928         if (of_data)
1929                 plat->controller_flags |= of_data->controller_flags;
1930
1931 #ifdef CONFIG_OMAP54XX
1932         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1933         if (fixups) {
1934                 plat->hw_rev = fixups->hw_rev;
1935                 cfg->host_caps &= ~fixups->unsupported_caps;
1936                 cfg->f_max = fixups->max_freq;
1937         }
1938 #endif
1939
1940         return 0;
1941 }
1942 #endif
1943
1944 #ifdef CONFIG_BLK
1945
1946 static int omap_hsmmc_bind(struct udevice *dev)
1947 {
1948         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1949         plat->mmc = calloc(1, sizeof(struct mmc));
1950         return mmc_bind(dev, plat->mmc, &plat->cfg);
1951 }
1952 #endif
1953 static int omap_hsmmc_probe(struct udevice *dev)
1954 {
1955         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1956         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1957         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1958         struct mmc_config *cfg = &plat->cfg;
1959         struct mmc *mmc;
1960 #ifdef CONFIG_IODELAY_RECALIBRATION
1961         int ret;
1962 #endif
1963
1964         cfg->name = "OMAP SD/MMC";
1965         priv->base_addr = plat->base_addr;
1966         priv->controller_flags = plat->controller_flags;
1967         priv->hw_rev = plat->hw_rev;
1968
1969 #ifdef CONFIG_BLK
1970         mmc = plat->mmc;
1971 #else
1972         mmc = mmc_create(cfg, priv);
1973         if (mmc == NULL)
1974                 return -1;
1975 #endif
1976 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1977         device_get_supply_regulator(dev, "pbias-supply",
1978                                     &priv->pbias_supply);
1979 #endif
1980 #if defined(OMAP_HSMMC_USE_GPIO)
1981 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1982         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1983         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1984 #endif
1985 #endif
1986
1987         mmc->dev = dev;
1988         upriv->mmc = mmc;
1989
1990 #ifdef CONFIG_IODELAY_RECALIBRATION
1991         ret = omap_hsmmc_get_pinctrl_state(mmc);
1992         /*
1993          * disable high speed modes for the platforms that require IO delay
1994          * and for which we don't have this information
1995          */
1996         if ((ret < 0) &&
1997             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1998                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1999                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2000                                     UHS_CAPS);
2001         }
2002 #endif
2003
2004         return omap_hsmmc_init_setup(mmc);
2005 }
2006
2007 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2008
2009 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2010         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2011 };
2012
2013 static const struct udevice_id omap_hsmmc_ids[] = {
2014         { .compatible = "ti,omap3-hsmmc" },
2015         { .compatible = "ti,omap4-hsmmc" },
2016         { .compatible = "ti,am33xx-hsmmc" },
2017         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2018         { }
2019 };
2020 #endif
2021
2022 U_BOOT_DRIVER(omap_hsmmc) = {
2023         .name   = "omap_hsmmc",
2024         .id     = UCLASS_MMC,
2025 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2026         .of_match = omap_hsmmc_ids,
2027         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2028         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2029 #endif
2030 #ifdef CONFIG_BLK
2031         .bind = omap_hsmmc_bind,
2032 #endif
2033         .ops = &omap_hsmmc_ops,
2034         .probe  = omap_hsmmc_probe,
2035         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2036 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2037         .flags  = DM_FLAG_PRE_RELOC,
2038 #endif
2039 };
2040 #endif