1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 SSP MMC driver
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
8 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * on behalf of DENX Software Engineering GmbH
11 * Based on code from LTIB:
12 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
15 * Copyright 2007, Freescale Semiconductor, Inc
18 * Based vaguely on the pxa mmc code:
20 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
27 #include <linux/delay.h>
28 #include <linux/errno.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/mach-imx/dma.h>
34 #include <bouncebuf.h>
36 #define MXSMMC_MAX_TIMEOUT 10000
37 #define MXSMMC_SMALL_TRANSFER 512
39 #if !CONFIG_IS_ENABLED(DM_MMC)
42 int (*mmc_is_wp)(int);
44 struct mmc_config cfg; /* mmc configuration */
45 struct mxs_dma_desc *desc;
47 struct mxs_ssp_regs *regs;
49 #else /* CONFIG_IS_ENABLED(DM_MMC) */
50 #include <dm/device.h>
52 #include <dt-structs.h>
55 #define dtd_fsl_imx_mmc dtd_fsl_imx28_mmc
56 #else /* CONFIG_MX23 */
57 #define dtd_fsl_imx_mmc dtd_fsl_imx23_mmc
60 struct mxsmmc_platdata {
61 #if CONFIG_IS_ENABLED(OF_PLATDATA)
62 struct dtd_fsl_imx_mmc dtplat;
64 struct mmc_config cfg;
75 struct mxs_dma_desc *desc;
77 struct mxs_ssp_regs *regs;
78 unsigned int dma_channel;
82 #if !CONFIG_IS_ENABLED(DM_MMC)
83 static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
84 struct mmc_data *data);
86 static int mxsmmc_cd(struct mxsmmc_priv *priv)
88 struct mxs_ssp_regs *ssp_regs = priv->regs;
91 return priv->mmc_cd(priv->id);
93 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
96 static int mxsmmc_set_ios(struct mmc *mmc)
98 struct mxsmmc_priv *priv = mmc->priv;
99 struct mxs_ssp_regs *ssp_regs = priv->regs;
101 /* Set the clock speed */
103 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
105 switch (mmc->bus_width) {
107 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
110 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
113 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
117 /* Set the bus width */
118 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
119 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
121 debug("MMC%d: Set %d bits bus width\n",
122 mmc->block_dev.devnum, mmc->bus_width);
127 static int mxsmmc_init(struct mmc *mmc)
129 struct mxsmmc_priv *priv = mmc->priv;
130 struct mxs_ssp_regs *ssp_regs = priv->regs;
133 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
135 /* Reconfigure the SSP block for MMC operation */
136 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
137 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
138 SSP_CTRL1_DMA_ENABLE |
140 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
141 SSP_CTRL1_DATA_CRC_IRQ_EN |
142 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
143 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
144 SSP_CTRL1_RESP_ERR_IRQ_EN,
145 &ssp_regs->hw_ssp_ctrl1_set);
147 /* Set initial bit clock 400 KHz */
148 mxs_set_ssp_busclock(priv->id, 400);
150 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
151 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
153 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
158 static const struct mmc_ops mxsmmc_ops = {
159 .send_cmd = mxsmmc_send_cmd,
160 .set_ios = mxsmmc_set_ios,
164 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
166 struct mmc *mmc = NULL;
167 struct mxsmmc_priv *priv = NULL;
169 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
171 if (!mxs_ssp_bus_id_valid(id))
174 priv = malloc(sizeof(struct mxsmmc_priv));
178 priv->desc = mxs_dma_desc_alloc();
184 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
188 priv->mmc_is_wp = wp;
191 priv->regs = mxs_ssp_regs_by_bus(id);
193 priv->cfg.name = "MXS MMC";
194 priv->cfg.ops = &mxsmmc_ops;
196 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
198 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
199 MMC_MODE_HS_52MHz | MMC_MODE_HS;
202 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
203 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
204 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
205 * CLOCK_RATE could be any integer from 0 to 255.
207 priv->cfg.f_min = 400000;
208 priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id)
210 priv->cfg.b_max = 0x20;
212 mmc = mmc_create(&priv->cfg, priv);
214 mxs_dma_desc_free(priv->desc);
220 #endif /* CONFIG_IS_ENABLED(DM_MMC) */
222 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
224 struct mxs_ssp_regs *ssp_regs = priv->regs;
226 int timeout = MXSMMC_MAX_TIMEOUT;
228 uint32_t data_count = data->blocksize * data->blocks;
230 if (data->flags & MMC_DATA_READ) {
231 data_ptr = (uint32_t *)data->dest;
232 while (data_count && --timeout) {
233 reg = readl(&ssp_regs->hw_ssp_status);
234 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
235 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
237 timeout = MXSMMC_MAX_TIMEOUT;
242 data_ptr = (uint32_t *)data->src;
244 while (data_count && --timeout) {
245 reg = readl(&ssp_regs->hw_ssp_status);
246 if (!(reg & SSP_STATUS_FIFO_FULL)) {
247 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
249 timeout = MXSMMC_MAX_TIMEOUT;
255 return timeout ? 0 : -ECOMM;
258 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
260 uint32_t data_count = data->blocksize * data->blocks;
262 struct mxs_dma_desc *desc = priv->desc;
265 struct bounce_buffer bbstate;
267 memset(desc, 0, sizeof(struct mxs_dma_desc));
268 desc->address = (dma_addr_t)desc;
270 if (data->flags & MMC_DATA_READ) {
271 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
273 flags = GEN_BB_WRITE;
275 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
276 addr = (void *)data->src;
280 bounce_buffer_start(&bbstate, addr, data_count, flags);
282 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
284 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
285 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
287 #if !CONFIG_IS_ENABLED(DM_MMC)
288 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
290 dmach = priv->dma_channel;
292 mxs_dma_desc_append(dmach, priv->desc);
293 if (mxs_dma_go(dmach)) {
294 bounce_buffer_stop(&bbstate);
298 bounce_buffer_stop(&bbstate);
303 #if !CONFIG_IS_ENABLED(DM_MMC)
305 * Sends a command out on the bus. Takes the mmc pointer,
306 * a command pointer, and an optional data pointer.
309 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
311 struct mxsmmc_priv *priv = mmc->priv;
312 struct mxs_ssp_regs *ssp_regs = priv->regs;
315 mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
317 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
318 struct mxsmmc_priv *priv = dev_get_priv(dev);
319 struct mxs_ssp_regs *ssp_regs = priv->regs;
320 struct mmc *mmc = &plat->mmc;
326 #if !CONFIG_IS_ENABLED(DM_MMC)
327 int devnum = mmc->block_dev.devnum;
329 int devnum = mmc_get_blk_desc(mmc)->devnum;
331 debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx);
334 timeout = MXSMMC_MAX_TIMEOUT;
337 reg = readl(&ssp_regs->hw_ssp_status);
339 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
340 SSP_STATUS_CMD_BUSY))) {
346 printf("MMC%d: Bus busy timeout!\n", devnum);
349 #if !CONFIG_IS_ENABLED(DM_MMC)
350 /* See if card is present */
351 if (!mxsmmc_cd(priv)) {
352 printf("MMC%d: No card detected!\n", devnum);
356 /* Start building CTRL0 contents */
357 ctrl0 = priv->buswidth;
360 if (!(cmd->resp_type & MMC_RSP_CRC))
361 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
362 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
363 ctrl0 |= SSP_CTRL0_GET_RESP;
364 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
365 ctrl0 |= SSP_CTRL0_LONG_RESP;
367 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
368 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
370 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
373 reg = readl(&ssp_regs->hw_ssp_cmd0);
374 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
375 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
376 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
377 reg |= SSP_CMD0_APPEND_8CYC;
378 writel(reg, &ssp_regs->hw_ssp_cmd0);
380 /* Command argument */
381 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
386 if (data->flags & MMC_DATA_READ) {
387 ctrl0 |= SSP_CTRL0_READ;
388 #if !CONFIG_IS_ENABLED(DM_MMC)
389 } else if (priv->mmc_is_wp &&
390 priv->mmc_is_wp(devnum)) {
391 printf("MMC%d: Can not write a locked card!\n", devnum);
395 ctrl0 |= SSP_CTRL0_DATA_XFER;
397 reg = data->blocksize * data->blocks;
398 #if defined(CONFIG_MX23)
399 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
401 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
402 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
403 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
404 ((ffs(data->blocksize) - 1) <<
405 SSP_CMD0_BLOCK_SIZE_OFFSET));
406 #elif defined(CONFIG_MX28)
407 writel(reg, &ssp_regs->hw_ssp_xfer_size);
409 reg = ((data->blocks - 1) <<
410 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
411 ((ffs(data->blocksize) - 1) <<
412 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
413 writel(reg, &ssp_regs->hw_ssp_block_size);
417 /* Kick off the command */
418 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
419 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
421 /* Wait for the command to complete */
422 timeout = MXSMMC_MAX_TIMEOUT;
425 reg = readl(&ssp_regs->hw_ssp_status);
426 if (!(reg & SSP_STATUS_CMD_BUSY))
431 printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx);
435 /* Check command timeout */
436 if (reg & SSP_STATUS_RESP_TIMEOUT) {
437 debug("MMC%d: Command %d timeout (status 0x%08x)\n",
438 devnum, cmd->cmdidx, reg);
442 /* Check command errors */
443 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
444 printf("MMC%d: Command %d error (status 0x%08x)!\n",
445 devnum, cmd->cmdidx, reg);
449 /* Copy response to response buffer */
450 if (cmd->resp_type & MMC_RSP_136) {
451 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
452 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
453 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
454 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
456 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
458 /* Return if no data to process */
462 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
463 ret = mxsmmc_send_cmd_pio(priv, data);
465 printf("MMC%d: Data timeout with command %d "
466 "(status 0x%08x)!\n", devnum, cmd->cmdidx, reg);
470 ret = mxsmmc_send_cmd_dma(priv, data);
472 printf("MMC%d: DMA transfer failed\n", devnum);
477 /* Check data errors */
478 reg = readl(&ssp_regs->hw_ssp_status);
480 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
481 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
482 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
483 devnum, cmd->cmdidx, reg);
490 #if CONFIG_IS_ENABLED(DM_MMC)
491 /* Base numbers of i.MX2[38] clk for ssp0 IP block */
492 #define MXS_SSP_IMX23_CLKID_SSP0 33
493 #define MXS_SSP_IMX28_CLKID_SSP0 46
495 static int mxsmmc_get_cd(struct udevice *dev)
497 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
498 struct mxsmmc_priv *priv = dev_get_priv(dev);
499 struct mxs_ssp_regs *ssp_regs = priv->regs;
501 if (plat->non_removable)
504 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
507 static int mxsmmc_set_ios(struct udevice *dev)
509 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
510 struct mxsmmc_priv *priv = dev_get_priv(dev);
511 struct mxs_ssp_regs *ssp_regs = priv->regs;
512 struct mmc *mmc = &plat->mmc;
514 /* Set the clock speed */
516 mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000);
518 switch (mmc->bus_width) {
520 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
523 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
526 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
530 /* Set the bus width */
531 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
532 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
534 debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum,
540 static int mxsmmc_init(struct udevice *dev)
542 struct mxsmmc_priv *priv = dev_get_priv(dev);
543 struct mxs_ssp_regs *ssp_regs = priv->regs;
546 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
548 /* Reconfigure the SSP block for MMC operation */
549 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
550 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
551 SSP_CTRL1_DMA_ENABLE |
553 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
554 SSP_CTRL1_DATA_CRC_IRQ_EN |
555 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
556 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
557 SSP_CTRL1_RESP_ERR_IRQ_EN,
558 &ssp_regs->hw_ssp_ctrl1_set);
560 /* Set initial bit clock 400 KHz */
561 mxs_set_ssp_busclock(priv->clkid, 400);
563 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
564 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
566 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
571 static int mxsmmc_probe(struct udevice *dev)
573 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
574 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
575 struct mxsmmc_priv *priv = dev_get_priv(dev);
576 struct blk_desc *bdesc;
580 debug("%s: probe\n", __func__);
582 #if CONFIG_IS_ENABLED(OF_PLATDATA)
583 struct dtd_fsl_imx_mmc *dtplat = &plat->dtplat;
584 struct phandle_1_arg *p1a = &dtplat->clocks[0];
586 priv->buswidth = dtplat->bus_width;
587 priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
588 priv->dma_channel = dtplat->dmas[1];
590 plat->non_removable = dtplat->non_removable;
592 debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n",
593 priv->regs, priv->buswidth, clkid, plat->non_removable);
595 priv->regs = (struct mxs_ssp_regs *)plat->base;
596 priv->dma_channel = plat->dma_id;
597 clkid = plat->clk_id;
601 priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
602 #else /* CONFIG_MX23 */
603 priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
606 mmc->cfg = &plat->cfg;
609 priv->desc = mxs_dma_desc_alloc();
611 printf("%s: Cannot allocate DMA descriptor\n", __func__);
615 ret = mxs_dma_init_channel(priv->dma_channel);
619 plat->cfg.name = "MXS MMC";
620 plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
622 plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
623 MMC_MODE_HS_52MHz | MMC_MODE_HS;
626 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
627 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
628 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
629 * CLOCK_RATE could be any integer from 0 to 255.
631 plat->cfg.f_min = 400000;
632 plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2;
633 plat->cfg.b_max = 0x20;
635 bdesc = mmc_get_blk_desc(mmc);
637 printf("%s: No block device descriptor!\n", __func__);
641 if (plat->non_removable)
642 bdesc->removable = 0;
644 ret = mxsmmc_init(dev);
646 printf("%s: MMC%d init error %d\n", __func__,
649 /* Set the initial clock speed */
650 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
657 #if CONFIG_IS_ENABLED(BLK)
658 static int mxsmmc_bind(struct udevice *dev)
660 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
662 return mmc_bind(dev, &plat->mmc, &plat->cfg);
666 static const struct dm_mmc_ops mxsmmc_ops = {
667 .get_cd = mxsmmc_get_cd,
668 .send_cmd = mxsmmc_send_cmd,
669 .set_ios = mxsmmc_set_ios,
672 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
673 static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
675 struct mxsmmc_platdata *plat = bus->platdata;
679 plat->base = dev_read_addr(bus);
681 dev_read_u32_default(bus, "bus-width", 1);
682 plat->non_removable = dev_read_bool(bus, "non-removable");
684 ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
686 printf("%s: Reading 'dmas' property failed!\n", __func__);
689 plat->dma_id = prop[1];
691 ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
693 printf("%s: Reading 'clocks' property failed!\n", __func__);
696 plat->clk_id = prop[1];
698 debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n",
699 __func__, (uint)plat->base, plat->buswidth,
700 plat->non_removable ? "non-removable" : NULL,
701 plat->dma_id, plat->clk_id);
706 static const struct udevice_id mxsmmc_ids[] = {
707 { .compatible = "fsl,imx23-mmc", },
708 { .compatible = "fsl,imx28-mmc", },
713 U_BOOT_DRIVER(mxsmmc) = {
715 .name = "fsl_imx28_mmc",
716 #else /* CONFIG_MX23 */
717 .name = "fsl_imx23_mmc",
720 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
721 .of_match = mxsmmc_ids,
722 .ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
725 #if CONFIG_IS_ENABLED(BLK)
728 .probe = mxsmmc_probe,
729 .priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
730 .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
733 #endif /* CONFIG_DM_MMC */