1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 SSP MMC driver
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
8 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * on behalf of DENX Software Engineering GmbH
11 * Based on code from LTIB:
12 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
15 * Copyright 2007, Freescale Semiconductor, Inc
18 * Based vaguely on the pxa mmc code:
20 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
27 #include <linux/errno.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/mach-imx/dma.h>
33 #include <bouncebuf.h>
35 #define MXSMMC_MAX_TIMEOUT 10000
36 #define MXSMMC_SMALL_TRANSFER 512
38 #if !CONFIG_IS_ENABLED(DM_MMC)
41 int (*mmc_is_wp)(int);
43 struct mmc_config cfg; /* mmc configuration */
44 struct mxs_dma_desc *desc;
46 struct mxs_ssp_regs *regs;
48 #else /* CONFIG_IS_ENABLED(DM_MMC) */
49 #include <dm/device.h>
51 #include <dt-structs.h>
54 #define dtd_fsl_imx_mmc dtd_fsl_imx28_mmc
55 #else /* CONFIG_MX23 */
56 #define dtd_fsl_imx_mmc dtd_fsl_imx23_mmc
59 struct mxsmmc_platdata {
60 #if CONFIG_IS_ENABLED(OF_PLATDATA)
61 struct dtd_fsl_imx_mmc dtplat;
63 struct mmc_config cfg;
74 struct mxs_dma_desc *desc;
76 struct mxs_ssp_regs *regs;
77 unsigned int dma_channel;
81 #if !CONFIG_IS_ENABLED(DM_MMC)
82 static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
83 struct mmc_data *data);
85 static int mxsmmc_cd(struct mxsmmc_priv *priv)
87 struct mxs_ssp_regs *ssp_regs = priv->regs;
90 return priv->mmc_cd(priv->id);
92 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
95 static int mxsmmc_set_ios(struct mmc *mmc)
97 struct mxsmmc_priv *priv = mmc->priv;
98 struct mxs_ssp_regs *ssp_regs = priv->regs;
100 /* Set the clock speed */
102 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
104 switch (mmc->bus_width) {
106 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
109 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
112 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
116 /* Set the bus width */
117 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
118 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
120 debug("MMC%d: Set %d bits bus width\n",
121 mmc->block_dev.devnum, mmc->bus_width);
126 static int mxsmmc_init(struct mmc *mmc)
128 struct mxsmmc_priv *priv = mmc->priv;
129 struct mxs_ssp_regs *ssp_regs = priv->regs;
132 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
134 /* Reconfigure the SSP block for MMC operation */
135 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
136 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
137 SSP_CTRL1_DMA_ENABLE |
139 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
140 SSP_CTRL1_DATA_CRC_IRQ_EN |
141 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
142 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
143 SSP_CTRL1_RESP_ERR_IRQ_EN,
144 &ssp_regs->hw_ssp_ctrl1_set);
146 /* Set initial bit clock 400 KHz */
147 mxs_set_ssp_busclock(priv->id, 400);
149 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
150 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
152 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
157 static const struct mmc_ops mxsmmc_ops = {
158 .send_cmd = mxsmmc_send_cmd,
159 .set_ios = mxsmmc_set_ios,
163 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
165 struct mmc *mmc = NULL;
166 struct mxsmmc_priv *priv = NULL;
168 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
170 if (!mxs_ssp_bus_id_valid(id))
173 priv = malloc(sizeof(struct mxsmmc_priv));
177 priv->desc = mxs_dma_desc_alloc();
183 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
187 priv->mmc_is_wp = wp;
190 priv->regs = mxs_ssp_regs_by_bus(id);
192 priv->cfg.name = "MXS MMC";
193 priv->cfg.ops = &mxsmmc_ops;
195 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
197 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
198 MMC_MODE_HS_52MHz | MMC_MODE_HS;
201 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
202 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
203 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
204 * CLOCK_RATE could be any integer from 0 to 255.
206 priv->cfg.f_min = 400000;
207 priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id)
209 priv->cfg.b_max = 0x20;
211 mmc = mmc_create(&priv->cfg, priv);
213 mxs_dma_desc_free(priv->desc);
219 #endif /* CONFIG_IS_ENABLED(DM_MMC) */
221 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
223 struct mxs_ssp_regs *ssp_regs = priv->regs;
225 int timeout = MXSMMC_MAX_TIMEOUT;
227 uint32_t data_count = data->blocksize * data->blocks;
229 if (data->flags & MMC_DATA_READ) {
230 data_ptr = (uint32_t *)data->dest;
231 while (data_count && --timeout) {
232 reg = readl(&ssp_regs->hw_ssp_status);
233 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
234 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
236 timeout = MXSMMC_MAX_TIMEOUT;
241 data_ptr = (uint32_t *)data->src;
243 while (data_count && --timeout) {
244 reg = readl(&ssp_regs->hw_ssp_status);
245 if (!(reg & SSP_STATUS_FIFO_FULL)) {
246 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
248 timeout = MXSMMC_MAX_TIMEOUT;
254 return timeout ? 0 : -ECOMM;
257 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
259 uint32_t data_count = data->blocksize * data->blocks;
261 struct mxs_dma_desc *desc = priv->desc;
264 struct bounce_buffer bbstate;
266 memset(desc, 0, sizeof(struct mxs_dma_desc));
267 desc->address = (dma_addr_t)desc;
269 if (data->flags & MMC_DATA_READ) {
270 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
272 flags = GEN_BB_WRITE;
274 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
275 addr = (void *)data->src;
279 bounce_buffer_start(&bbstate, addr, data_count, flags);
281 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
283 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
284 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
286 #if !CONFIG_IS_ENABLED(DM_MMC)
287 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
289 dmach = priv->dma_channel;
291 mxs_dma_desc_append(dmach, priv->desc);
292 if (mxs_dma_go(dmach)) {
293 bounce_buffer_stop(&bbstate);
297 bounce_buffer_stop(&bbstate);
302 #if !CONFIG_IS_ENABLED(DM_MMC)
304 * Sends a command out on the bus. Takes the mmc pointer,
305 * a command pointer, and an optional data pointer.
308 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
310 struct mxsmmc_priv *priv = mmc->priv;
311 struct mxs_ssp_regs *ssp_regs = priv->regs;
314 mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
316 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
317 struct mxsmmc_priv *priv = dev_get_priv(dev);
318 struct mxs_ssp_regs *ssp_regs = priv->regs;
319 struct mmc *mmc = &plat->mmc;
325 #if !CONFIG_IS_ENABLED(DM_MMC)
326 int devnum = mmc->block_dev.devnum;
328 int devnum = mmc_get_blk_desc(mmc)->devnum;
330 debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx);
333 timeout = MXSMMC_MAX_TIMEOUT;
336 reg = readl(&ssp_regs->hw_ssp_status);
338 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
339 SSP_STATUS_CMD_BUSY))) {
345 printf("MMC%d: Bus busy timeout!\n", devnum);
348 #if !CONFIG_IS_ENABLED(DM_MMC)
349 /* See if card is present */
350 if (!mxsmmc_cd(priv)) {
351 printf("MMC%d: No card detected!\n", devnum);
355 /* Start building CTRL0 contents */
356 ctrl0 = priv->buswidth;
359 if (!(cmd->resp_type & MMC_RSP_CRC))
360 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
361 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
362 ctrl0 |= SSP_CTRL0_GET_RESP;
363 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
364 ctrl0 |= SSP_CTRL0_LONG_RESP;
366 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
367 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
369 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
372 reg = readl(&ssp_regs->hw_ssp_cmd0);
373 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
374 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
375 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
376 reg |= SSP_CMD0_APPEND_8CYC;
377 writel(reg, &ssp_regs->hw_ssp_cmd0);
379 /* Command argument */
380 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
385 if (data->flags & MMC_DATA_READ) {
386 ctrl0 |= SSP_CTRL0_READ;
387 #if !CONFIG_IS_ENABLED(DM_MMC)
388 } else if (priv->mmc_is_wp &&
389 priv->mmc_is_wp(devnum)) {
390 printf("MMC%d: Can not write a locked card!\n", devnum);
394 ctrl0 |= SSP_CTRL0_DATA_XFER;
396 reg = data->blocksize * data->blocks;
397 #if defined(CONFIG_MX23)
398 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
400 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
401 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
402 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
403 ((ffs(data->blocksize) - 1) <<
404 SSP_CMD0_BLOCK_SIZE_OFFSET));
405 #elif defined(CONFIG_MX28)
406 writel(reg, &ssp_regs->hw_ssp_xfer_size);
408 reg = ((data->blocks - 1) <<
409 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
410 ((ffs(data->blocksize) - 1) <<
411 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
412 writel(reg, &ssp_regs->hw_ssp_block_size);
416 /* Kick off the command */
417 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
418 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
420 /* Wait for the command to complete */
421 timeout = MXSMMC_MAX_TIMEOUT;
424 reg = readl(&ssp_regs->hw_ssp_status);
425 if (!(reg & SSP_STATUS_CMD_BUSY))
430 printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx);
434 /* Check command timeout */
435 if (reg & SSP_STATUS_RESP_TIMEOUT) {
436 debug("MMC%d: Command %d timeout (status 0x%08x)\n",
437 devnum, cmd->cmdidx, reg);
441 /* Check command errors */
442 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
443 printf("MMC%d: Command %d error (status 0x%08x)!\n",
444 devnum, cmd->cmdidx, reg);
448 /* Copy response to response buffer */
449 if (cmd->resp_type & MMC_RSP_136) {
450 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
451 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
452 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
453 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
455 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
457 /* Return if no data to process */
461 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
462 ret = mxsmmc_send_cmd_pio(priv, data);
464 printf("MMC%d: Data timeout with command %d "
465 "(status 0x%08x)!\n", devnum, cmd->cmdidx, reg);
469 ret = mxsmmc_send_cmd_dma(priv, data);
471 printf("MMC%d: DMA transfer failed\n", devnum);
476 /* Check data errors */
477 reg = readl(&ssp_regs->hw_ssp_status);
479 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
480 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
481 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
482 devnum, cmd->cmdidx, reg);
489 #if CONFIG_IS_ENABLED(DM_MMC)
490 /* Base numbers of i.MX2[38] clk for ssp0 IP block */
491 #define MXS_SSP_IMX23_CLKID_SSP0 33
492 #define MXS_SSP_IMX28_CLKID_SSP0 46
494 static int mxsmmc_get_cd(struct udevice *dev)
496 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
497 struct mxsmmc_priv *priv = dev_get_priv(dev);
498 struct mxs_ssp_regs *ssp_regs = priv->regs;
500 if (plat->non_removable)
503 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
506 static int mxsmmc_set_ios(struct udevice *dev)
508 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
509 struct mxsmmc_priv *priv = dev_get_priv(dev);
510 struct mxs_ssp_regs *ssp_regs = priv->regs;
511 struct mmc *mmc = &plat->mmc;
513 /* Set the clock speed */
515 mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000);
517 switch (mmc->bus_width) {
519 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
522 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
525 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
529 /* Set the bus width */
530 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
531 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
533 debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum,
539 static int mxsmmc_init(struct udevice *dev)
541 struct mxsmmc_priv *priv = dev_get_priv(dev);
542 struct mxs_ssp_regs *ssp_regs = priv->regs;
545 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
547 /* Reconfigure the SSP block for MMC operation */
548 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
549 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
550 SSP_CTRL1_DMA_ENABLE |
552 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
553 SSP_CTRL1_DATA_CRC_IRQ_EN |
554 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
555 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
556 SSP_CTRL1_RESP_ERR_IRQ_EN,
557 &ssp_regs->hw_ssp_ctrl1_set);
559 /* Set initial bit clock 400 KHz */
560 mxs_set_ssp_busclock(priv->clkid, 400);
562 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
563 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
565 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
570 static int mxsmmc_probe(struct udevice *dev)
572 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
573 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
574 struct mxsmmc_priv *priv = dev_get_priv(dev);
575 struct blk_desc *bdesc;
579 debug("%s: probe\n", __func__);
581 #if CONFIG_IS_ENABLED(OF_PLATDATA)
582 struct dtd_fsl_imx_mmc *dtplat = &plat->dtplat;
583 struct phandle_1_arg *p1a = &dtplat->clocks[0];
585 priv->buswidth = dtplat->bus_width;
586 priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
587 priv->dma_channel = dtplat->dmas[1];
589 plat->non_removable = dtplat->non_removable;
591 debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n",
592 priv->regs, priv->buswidth, clkid, plat->non_removable);
594 priv->regs = (struct mxs_ssp_regs *)plat->base;
595 priv->dma_channel = plat->dma_id;
596 clkid = plat->clk_id;
600 priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
601 #else /* CONFIG_MX23 */
602 priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
605 mmc->cfg = &plat->cfg;
608 priv->desc = mxs_dma_desc_alloc();
610 printf("%s: Cannot allocate DMA descriptor\n", __func__);
614 ret = mxs_dma_init_channel(priv->dma_channel);
618 plat->cfg.name = "MXS MMC";
619 plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
621 plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
622 MMC_MODE_HS_52MHz | MMC_MODE_HS;
625 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
626 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
627 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
628 * CLOCK_RATE could be any integer from 0 to 255.
630 plat->cfg.f_min = 400000;
631 plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2;
632 plat->cfg.b_max = 0x20;
634 bdesc = mmc_get_blk_desc(mmc);
636 printf("%s: No block device descriptor!\n", __func__);
640 if (plat->non_removable)
641 bdesc->removable = 0;
643 ret = mxsmmc_init(dev);
645 printf("%s: MMC%d init error %d\n", __func__,
648 /* Set the initial clock speed */
649 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
656 #if CONFIG_IS_ENABLED(BLK)
657 static int mxsmmc_bind(struct udevice *dev)
659 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
661 return mmc_bind(dev, &plat->mmc, &plat->cfg);
665 static const struct dm_mmc_ops mxsmmc_ops = {
666 .get_cd = mxsmmc_get_cd,
667 .send_cmd = mxsmmc_send_cmd,
668 .set_ios = mxsmmc_set_ios,
671 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
672 static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
674 struct mxsmmc_platdata *plat = bus->platdata;
678 plat->base = dev_read_addr(bus);
680 dev_read_u32_default(bus, "bus-width", 1);
681 plat->non_removable = dev_read_bool(bus, "non-removable");
683 ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
685 printf("%s: Reading 'dmas' property failed!\n", __func__);
688 plat->dma_id = prop[1];
690 ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
692 printf("%s: Reading 'clocks' property failed!\n", __func__);
695 plat->clk_id = prop[1];
697 debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n",
698 __func__, (uint)plat->base, plat->buswidth,
699 plat->non_removable ? "non-removable" : NULL,
700 plat->dma_id, plat->clk_id);
705 static const struct udevice_id mxsmmc_ids[] = {
706 { .compatible = "fsl,imx23-mmc", },
707 { .compatible = "fsl,imx28-mmc", },
712 U_BOOT_DRIVER(mxsmmc) = {
714 .name = "fsl_imx28_mmc",
715 #else /* CONFIG_MX23 */
716 .name = "fsl_imx23_mmc",
719 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
720 .of_match = mxsmmc_ids,
721 .ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
724 #if CONFIG_IS_ENABLED(BLK)
727 .probe = mxsmmc_probe,
728 .priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
729 .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
732 #endif /* CONFIG_DM_MMC */