1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
6 * Yangbo Lu <yangbo.lu@nxp.com>
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
21 #include <power/regulator.h>
23 #include <fsl_esdhc_imx.h>
24 #include <fdt_support.h>
27 #include <asm-generic/gpio.h>
28 #include <dm/pinctrl.h>
30 #if !CONFIG_IS_ENABLED(BLK)
31 #include "mmc_private.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
38 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
39 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
40 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
42 #define MAX_TUNING_LOOP 40
43 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
46 uint dsaddr; /* SDMA system address register */
47 uint blkattr; /* Block attributes register */
48 uint cmdarg; /* Command argument register */
49 uint xfertyp; /* Transfer type register */
50 uint cmdrsp0; /* Command response 0 register */
51 uint cmdrsp1; /* Command response 1 register */
52 uint cmdrsp2; /* Command response 2 register */
53 uint cmdrsp3; /* Command response 3 register */
54 uint datport; /* Buffer data port register */
55 uint prsstat; /* Present state register */
56 uint proctl; /* Protocol control register */
57 uint sysctl; /* System Control Register */
58 uint irqstat; /* Interrupt status register */
59 uint irqstaten; /* Interrupt status enable register */
60 uint irqsigen; /* Interrupt signal enable register */
61 uint autoc12err; /* Auto CMD error status register */
62 uint hostcapblt; /* Host controller capabilities register */
63 uint wml; /* Watermark level register */
64 uint mixctrl; /* For USDHC */
65 char reserved1[4]; /* reserved */
66 uint fevt; /* Force event register */
67 uint admaes; /* ADMA error status register */
68 uint adsaddr; /* ADMA system address register */
72 uint clktunectrlstatus;
80 uint tuning_ctrl; /* on i.MX6/7/8 */
82 uint hostver; /* Host controller version register */
83 char reserved6[4]; /* reserved */
84 uint dmaerraddr; /* DMA error address register */
85 char reserved7[4]; /* reserved */
86 uint dmaerrattr; /* DMA error attribute register */
87 char reserved8[4]; /* reserved */
88 uint hostcapblt2; /* Host controller capabilities register 2 */
89 char reserved9[8]; /* reserved */
90 uint tcr; /* Tuning control register */
91 char reserved10[28]; /* reserved */
92 uint sddirctl; /* SD direction control register */
93 char reserved11[712];/* reserved */
94 uint scr; /* eSDHC control register */
97 struct fsl_esdhc_plat {
98 struct mmc_config cfg;
102 struct esdhc_soc_data {
108 * struct fsl_esdhc_priv
110 * @esdhc_regs: registers of the sdhc controller
111 * @sdhc_clk: Current clk of the sdhc controller
112 * @bus_width: bus width, 1bit, 4bit or 8bit
115 * Following is used when Driver Model is enabled for MMC
116 * @dev: pointer for the device
117 * @non_removable: 0: removable; 1: non-removable
118 * @wp_enable: 1: enable checking wp; 0: no check
119 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
120 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
121 * @caps: controller capabilities
122 * @tuning_step: tuning step setting in tuning_ctrl register
123 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
124 * @strobe_dll_delay_target: settings in strobe_dllctrl
125 * @signal_voltage: indicating the current voltage
126 * @cd_gpio: gpio for card detection
127 * @wp_gpio: gpio for write protection
129 struct fsl_esdhc_priv {
130 struct fsl_esdhc *esdhc_regs;
131 unsigned int sdhc_clk;
135 unsigned int bus_width;
136 #if !CONFIG_IS_ENABLED(BLK)
146 u32 tuning_start_tap;
147 u32 strobe_dll_delay_target;
149 #if IS_ENABLED(CONFIG_DM_REGULATOR)
150 struct udevice *vqmmc_dev;
151 struct udevice *vmmc_dev;
153 #ifdef CONFIG_DM_GPIO
154 struct gpio_desc cd_gpio;
155 struct gpio_desc wp_gpio;
159 /* Return the XFERTYP flags for a given command and data packet */
160 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
165 xfertyp |= XFERTYP_DPSEL;
166 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
167 xfertyp |= XFERTYP_DMAEN;
169 if (data->blocks > 1) {
170 xfertyp |= XFERTYP_MSBSEL;
171 xfertyp |= XFERTYP_BCEN;
172 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
173 xfertyp |= XFERTYP_AC12EN;
177 if (data->flags & MMC_DATA_READ)
178 xfertyp |= XFERTYP_DTDSEL;
181 if (cmd->resp_type & MMC_RSP_CRC)
182 xfertyp |= XFERTYP_CCCEN;
183 if (cmd->resp_type & MMC_RSP_OPCODE)
184 xfertyp |= XFERTYP_CICEN;
185 if (cmd->resp_type & MMC_RSP_136)
186 xfertyp |= XFERTYP_RSPTYP_136;
187 else if (cmd->resp_type & MMC_RSP_BUSY)
188 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
189 else if (cmd->resp_type & MMC_RSP_PRESENT)
190 xfertyp |= XFERTYP_RSPTYP_48;
192 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
193 xfertyp |= XFERTYP_CMDTYP_ABORT;
195 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
198 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
200 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
202 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
203 struct mmc_data *data)
205 struct fsl_esdhc *regs = priv->esdhc_regs;
213 if (data->flags & MMC_DATA_READ) {
214 blocks = data->blocks;
217 start = get_timer(0);
218 size = data->blocksize;
219 irqstat = esdhc_read32(®s->irqstat);
220 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
221 if (get_timer(start) > PIO_TIMEOUT) {
222 printf("\nData Read Failed in PIO Mode.");
226 while (size && (!(irqstat & IRQSTAT_TC))) {
227 udelay(100); /* Wait before last byte transfer complete */
228 irqstat = esdhc_read32(®s->irqstat);
229 databuf = in_le32(®s->datport);
230 *((uint *)buffer) = databuf;
237 blocks = data->blocks;
238 buffer = (char *)data->src;
240 start = get_timer(0);
241 size = data->blocksize;
242 irqstat = esdhc_read32(®s->irqstat);
243 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
244 if (get_timer(start) > PIO_TIMEOUT) {
245 printf("\nData Write Failed in PIO Mode.");
249 while (size && (!(irqstat & IRQSTAT_TC))) {
250 udelay(100); /* Wait before last byte transfer complete */
251 databuf = *((uint *)buffer);
254 irqstat = esdhc_read32(®s->irqstat);
255 out_le32(®s->datport, databuf);
263 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
264 struct mmc_data *data)
267 struct fsl_esdhc *regs = priv->esdhc_regs;
268 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
269 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
274 wml_value = data->blocksize/4;
276 if (data->flags & MMC_DATA_READ) {
277 if (wml_value > WML_RD_WML_MAX)
278 wml_value = WML_RD_WML_MAX_VAL;
280 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
281 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
282 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
283 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
284 addr = virt_to_phys((void *)(data->dest));
285 if (upper_32_bits(addr))
286 printf("Error found for upper 32 bits\n");
288 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
290 esdhc_write32(®s->dsaddr, (u32)data->dest);
294 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
295 flush_dcache_range((ulong)data->src,
296 (ulong)data->src+data->blocks
299 if (wml_value > WML_WR_WML_MAX)
300 wml_value = WML_WR_WML_MAX_VAL;
301 if (priv->wp_enable) {
302 if ((esdhc_read32(®s->prsstat) &
303 PRSSTAT_WPSPL) == 0) {
304 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
308 #ifdef CONFIG_DM_GPIO
309 if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
310 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
316 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
318 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
319 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
320 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
321 addr = virt_to_phys((void *)(data->src));
322 if (upper_32_bits(addr))
323 printf("Error found for upper 32 bits\n");
325 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
327 esdhc_write32(®s->dsaddr, (u32)data->src);
332 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
334 /* Calculate the timeout period for data transactions */
336 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
337 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
338 * So, Number of SD Clock cycles for 0.25sec should be minimum
339 * (SD Clock/sec * 0.25 sec) SD Clock cycles
340 * = (mmc->clock * 1/4) SD Clock cycles
342 * => (2^(timeout+13)) >= mmc->clock * 1/4
343 * Taking log2 both the sides
344 * => timeout + 13 >= log2(mmc->clock/4)
345 * Rounding up to next power of 2
346 * => timeout + 13 = log2(mmc->clock/4) + 1
347 * => timeout + 13 = fls(mmc->clock/4)
349 * However, the MMC spec "It is strongly recommended for hosts to
350 * implement more than 500ms timeout value even if the card
351 * indicates the 250ms maximum busy length." Even the previous
352 * value of 300ms is known to be insufficient for some cards.
354 * => timeout + 13 = fls(mmc->clock/2)
356 timeout = fls(mmc->clock/2);
365 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
366 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
370 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
373 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
378 static void check_and_invalidate_dcache_range
379 (struct mmc_cmd *cmd,
380 struct mmc_data *data) {
383 unsigned size = roundup(ARCH_DMA_MINALIGN,
384 data->blocks*data->blocksize);
385 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
386 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
389 addr = virt_to_phys((void *)(data->dest));
390 if (upper_32_bits(addr))
391 printf("Error found for upper 32 bits\n");
393 start = lower_32_bits(addr);
395 start = (unsigned)data->dest;
398 invalidate_dcache_range(start, end);
401 #ifdef CONFIG_MCF5441x
403 * Swaps 32-bit words to little-endian byte order.
405 static inline void sd_swap_dma_buff(struct mmc_data *data)
407 int i, size = data->blocksize >> 2;
408 u32 *buffer = (u32 *)data->dest;
411 while (data->blocks--) {
412 for (i = 0; i < size; i++) {
413 sw = __sw32(*buffer);
421 * Sends a command out on the bus. Takes the mmc pointer,
422 * a command pointer, and an optional data pointer.
424 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
425 struct mmc_cmd *cmd, struct mmc_data *data)
430 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
431 struct fsl_esdhc *regs = priv->esdhc_regs;
434 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
435 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
439 esdhc_write32(®s->irqstat, -1);
443 /* Wait for the bus to be idle */
444 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
445 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
448 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
451 /* Wait at least 8 SD clock cycles before the next command */
453 * Note: This is way more than 8 cycles, but 1ms seems to
454 * resolve timing issues with some cards
458 /* Set up for a data transfer if we have one */
460 err = esdhc_setup_data(priv, mmc, data);
464 if (data->flags & MMC_DATA_READ)
465 check_and_invalidate_dcache_range(cmd, data);
468 /* Figure out the transfer arguments */
469 xfertyp = esdhc_xfertyp(cmd, data);
472 esdhc_write32(®s->irqsigen, 0);
474 /* Send the command */
475 esdhc_write32(®s->cmdarg, cmd->cmdarg);
476 #if defined(CONFIG_FSL_USDHC)
477 esdhc_write32(®s->mixctrl,
478 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
479 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
480 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
482 esdhc_write32(®s->xfertyp, xfertyp);
485 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
486 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
489 /* Wait for the command to complete */
490 start = get_timer(0);
491 while (!(esdhc_read32(®s->irqstat) & flags)) {
492 if (get_timer(start) > 1000) {
498 irqstat = esdhc_read32(®s->irqstat);
500 if (irqstat & CMD_ERR) {
505 if (irqstat & IRQSTAT_CTOE) {
510 /* Switch voltage to 1.8V if CMD11 succeeded */
511 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
512 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
514 printf("Run CMD11 1.8V switch\n");
515 /* Sleep for 5 ms - max time for card to switch to 1.8V */
519 /* Workaround for ESDHC errata ENGcm03648 */
520 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
523 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
524 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
531 printf("Timeout waiting for DAT0 to go high!\n");
537 /* Copy the response to the response buffer */
538 if (cmd->resp_type & MMC_RSP_136) {
539 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
541 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
542 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
543 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
544 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
545 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
546 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
547 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
548 cmd->response[3] = (cmdrsp0 << 8);
550 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
552 /* Wait until all of the blocks are transferred */
554 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
555 esdhc_pio_read_write(priv, data);
557 flags = DATA_COMPLETE;
558 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
559 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
564 irqstat = esdhc_read32(®s->irqstat);
566 if (irqstat & IRQSTAT_DTOE) {
571 if (irqstat & DATA_ERR) {
575 } while ((irqstat & flags) != flags);
578 * Need invalidate the dcache here again to avoid any
579 * cache-fill during the DMA operations such as the
580 * speculative pre-fetching etc.
582 if (data->flags & MMC_DATA_READ) {
583 check_and_invalidate_dcache_range(cmd, data);
584 #ifdef CONFIG_MCF5441x
585 sd_swap_dma_buff(data);
592 /* Reset CMD and DATA portions on error */
594 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
596 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
600 esdhc_write32(®s->sysctl,
601 esdhc_read32(®s->sysctl) |
603 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
607 /* If this was CMD11, then notify that power cycle is needed */
608 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
609 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
612 esdhc_write32(®s->irqstat, -1);
617 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
619 struct fsl_esdhc *regs = priv->esdhc_regs;
623 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
624 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
631 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
632 int sdhc_clk = priv->sdhc_clk;
635 if (clock < mmc->cfg->f_min)
636 clock = mmc->cfg->f_min;
638 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
641 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
647 clk = (pre_div << 8) | (div << 4);
649 #ifdef CONFIG_FSL_USDHC
650 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
652 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
655 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
659 #ifdef CONFIG_FSL_USDHC
660 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
662 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
668 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
669 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
671 struct fsl_esdhc *regs = priv->esdhc_regs;
675 value = esdhc_read32(®s->sysctl);
678 value |= SYSCTL_CKEN;
680 value &= ~SYSCTL_CKEN;
682 esdhc_write32(®s->sysctl, value);
685 value = PRSSTAT_SDSTB;
686 while (!(esdhc_read32(®s->prsstat) & value)) {
688 printf("fsl_esdhc: Internal clock never stabilised.\n");
697 #ifdef MMC_SUPPORTS_TUNING
698 static int esdhc_change_pinstate(struct udevice *dev)
700 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
703 switch (priv->mode) {
706 ret = pinctrl_select_state(dev, "state_100mhz");
711 ret = pinctrl_select_state(dev, "state_200mhz");
714 ret = pinctrl_select_state(dev, "default");
719 printf("%s %d error\n", __func__, priv->mode);
724 static void esdhc_reset_tuning(struct mmc *mmc)
726 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
727 struct fsl_esdhc *regs = priv->esdhc_regs;
729 if (priv->flags & ESDHC_FLAG_USDHC) {
730 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
731 esdhc_clrbits32(®s->autoc12err,
732 MIX_CTRL_SMPCLK_SEL |
738 static void esdhc_set_strobe_dll(struct mmc *mmc)
740 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
741 struct fsl_esdhc *regs = priv->esdhc_regs;
744 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
745 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
748 * enable strobe dll ctrl and adjust the delay target
749 * for the uSDHC loopback read clock
751 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
752 (priv->strobe_dll_delay_target <<
753 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
754 writel(val, ®s->strobe_dllctrl);
755 /* wait 1us to make sure strobe dll status register stable */
757 val = readl(®s->strobe_dllstat);
758 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
759 pr_warn("HS400 strobe DLL status REF not lock!\n");
760 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
761 pr_warn("HS400 strobe DLL status SLV not lock!\n");
765 static int esdhc_set_timing(struct mmc *mmc)
767 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
768 struct fsl_esdhc *regs = priv->esdhc_regs;
771 mixctrl = readl(®s->mixctrl);
772 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
774 switch (mmc->selected_mode) {
777 esdhc_reset_tuning(mmc);
778 writel(mixctrl, ®s->mixctrl);
781 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
782 writel(mixctrl, ®s->mixctrl);
783 esdhc_set_strobe_dll(mmc);
793 writel(mixctrl, ®s->mixctrl);
797 mixctrl |= MIX_CTRL_DDREN;
798 writel(mixctrl, ®s->mixctrl);
801 printf("Not supported %d\n", mmc->selected_mode);
805 priv->mode = mmc->selected_mode;
807 return esdhc_change_pinstate(mmc->dev);
810 static int esdhc_set_voltage(struct mmc *mmc)
812 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
813 struct fsl_esdhc *regs = priv->esdhc_regs;
816 priv->signal_voltage = mmc->signal_voltage;
817 switch (mmc->signal_voltage) {
818 case MMC_SIGNAL_VOLTAGE_330:
819 if (priv->vs18_enable)
821 #if CONFIG_IS_ENABLED(DM_REGULATOR)
822 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
823 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
825 printf("Setting to 3.3V error");
833 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
834 if (!(esdhc_read32(®s->vendorspec) &
835 ESDHC_VENDORSPEC_VSELECT))
839 case MMC_SIGNAL_VOLTAGE_180:
840 #if CONFIG_IS_ENABLED(DM_REGULATOR)
841 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
842 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
844 printf("Setting to 1.8V error");
849 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
850 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
854 case MMC_SIGNAL_VOLTAGE_120:
861 static void esdhc_stop_tuning(struct mmc *mmc)
865 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
867 cmd.resp_type = MMC_RSP_R1b;
869 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
872 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
874 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
875 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
876 struct fsl_esdhc *regs = priv->esdhc_regs;
877 struct mmc *mmc = &plat->mmc;
878 u32 irqstaten = readl(®s->irqstaten);
879 u32 irqsigen = readl(®s->irqsigen);
880 int i, ret = -ETIMEDOUT;
883 /* clock tuning is not needed for upto 52MHz */
884 if (mmc->clock <= 52000000)
887 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
888 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
889 val = readl(®s->autoc12err);
890 mixctrl = readl(®s->mixctrl);
891 val &= ~MIX_CTRL_SMPCLK_SEL;
892 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
894 val |= MIX_CTRL_EXE_TUNE;
895 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
897 writel(val, ®s->autoc12err);
898 writel(mixctrl, ®s->mixctrl);
901 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
902 mixctrl = readl(®s->mixctrl);
903 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
904 writel(mixctrl, ®s->mixctrl);
906 writel(IRQSTATEN_BRR, ®s->irqstaten);
907 writel(IRQSTATEN_BRR, ®s->irqsigen);
910 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
911 * of loops reaches 40 times.
913 for (i = 0; i < MAX_TUNING_LOOP; i++) {
916 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
917 if (mmc->bus_width == 8)
918 writel(0x7080, ®s->blkattr);
919 else if (mmc->bus_width == 4)
920 writel(0x7040, ®s->blkattr);
922 writel(0x7040, ®s->blkattr);
925 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
926 val = readl(®s->mixctrl);
927 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
928 writel(val, ®s->mixctrl);
930 /* We are using STD tuning, no need to check return value */
931 mmc_send_tuning(mmc, opcode, NULL);
933 ctrl = readl(®s->autoc12err);
934 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
935 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
937 * need to wait some time, make sure sd/mmc fininsh
938 * send out tuning data, otherwise, the sd/mmc can't
939 * response to any command when the card still out
940 * put the tuning data.
947 /* Add 1ms delay for SD and eMMC */
951 writel(irqstaten, ®s->irqstaten);
952 writel(irqsigen, ®s->irqsigen);
954 esdhc_stop_tuning(mmc);
960 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
962 struct fsl_esdhc *regs = priv->esdhc_regs;
963 int ret __maybe_unused;
965 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
966 /* Select to use peripheral clock */
967 esdhc_clock_control(priv, false);
968 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
969 esdhc_clock_control(priv, true);
971 /* Set the clock speed */
972 if (priv->clock != mmc->clock)
973 set_sysctl(priv, mmc, mmc->clock);
975 #ifdef MMC_SUPPORTS_TUNING
976 if (mmc->clk_disable) {
977 #ifdef CONFIG_FSL_USDHC
978 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
980 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
983 #ifdef CONFIG_FSL_USDHC
984 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
987 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
991 if (priv->mode != mmc->selected_mode) {
992 ret = esdhc_set_timing(mmc);
994 printf("esdhc_set_timing error %d\n", ret);
999 if (priv->signal_voltage != mmc->signal_voltage) {
1000 ret = esdhc_set_voltage(mmc);
1002 printf("esdhc_set_voltage error %d\n", ret);
1008 /* Set the bus width */
1009 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1011 if (mmc->bus_width == 4)
1012 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1013 else if (mmc->bus_width == 8)
1014 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1019 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1021 struct fsl_esdhc *regs = priv->esdhc_regs;
1024 /* Reset the entire host controller */
1025 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1027 /* Wait until the controller is available */
1028 start = get_timer(0);
1029 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1030 if (get_timer(start) > 1000)
1034 #if defined(CONFIG_FSL_USDHC)
1035 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1036 esdhc_write32(®s->mmcboot, 0x0);
1037 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1038 esdhc_write32(®s->mixctrl, 0x0);
1039 esdhc_write32(®s->clktunectrlstatus, 0x0);
1041 /* Put VEND_SPEC to default value */
1042 if (priv->vs18_enable)
1043 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1044 ESDHC_VENDORSPEC_VSELECT));
1046 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1048 /* Disable DLL_CTRL delay line */
1049 esdhc_write32(®s->dllctrl, 0x0);
1053 /* Enable cache snooping */
1054 esdhc_write32(®s->scr, 0x00000040);
1057 #ifndef CONFIG_FSL_USDHC
1058 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1060 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1063 /* Set the initial clock speed */
1064 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1066 /* Disable the BRR and BWR bits in IRQSTAT */
1067 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1069 #ifdef CONFIG_MCF5441x
1070 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1072 /* Put the PROCTL reg back to the default */
1073 esdhc_write32(®s->proctl, PROCTL_INIT);
1076 /* Set timout to the maximum value */
1077 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1082 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1084 struct fsl_esdhc *regs = priv->esdhc_regs;
1087 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1088 if (CONFIG_ESDHC_DETECT_QUIRK)
1092 #if CONFIG_IS_ENABLED(DM_MMC)
1093 if (priv->non_removable)
1095 #ifdef CONFIG_DM_GPIO
1096 if (dm_gpio_is_valid(&priv->cd_gpio))
1097 return dm_gpio_get_value(&priv->cd_gpio);
1101 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1107 static int esdhc_reset(struct fsl_esdhc *regs)
1111 /* reset the controller */
1112 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1114 /* hardware clears the bit when it is done */
1115 start = get_timer(0);
1116 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1117 if (get_timer(start) > 100) {
1118 printf("MMC/SD: Reset never completed.\n");
1126 #if !CONFIG_IS_ENABLED(DM_MMC)
1127 static int esdhc_getcd(struct mmc *mmc)
1129 struct fsl_esdhc_priv *priv = mmc->priv;
1131 return esdhc_getcd_common(priv);
1134 static int esdhc_init(struct mmc *mmc)
1136 struct fsl_esdhc_priv *priv = mmc->priv;
1138 return esdhc_init_common(priv, mmc);
1141 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1142 struct mmc_data *data)
1144 struct fsl_esdhc_priv *priv = mmc->priv;
1146 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1149 static int esdhc_set_ios(struct mmc *mmc)
1151 struct fsl_esdhc_priv *priv = mmc->priv;
1153 return esdhc_set_ios_common(priv, mmc);
1156 static const struct mmc_ops esdhc_ops = {
1157 .getcd = esdhc_getcd,
1159 .send_cmd = esdhc_send_cmd,
1160 .set_ios = esdhc_set_ios,
1164 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1165 struct fsl_esdhc_plat *plat)
1167 struct mmc_config *cfg;
1168 struct fsl_esdhc *regs;
1169 u32 caps, voltage_caps;
1175 regs = priv->esdhc_regs;
1177 /* First reset the eSDHC controller */
1178 ret = esdhc_reset(regs);
1182 #ifdef CONFIG_MCF5441x
1183 /* ColdFire, using SDHC_DATA[3] for card detection */
1184 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1187 #ifndef CONFIG_FSL_USDHC
1188 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1189 | SYSCTL_IPGEN | SYSCTL_CKEN);
1190 /* Clearing tuning bits in case ROM has set it already */
1191 esdhc_write32(®s->mixctrl, 0);
1192 esdhc_write32(®s->autoc12err, 0);
1193 esdhc_write32(®s->clktunectrlstatus, 0);
1195 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1196 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1199 if (priv->vs18_enable)
1200 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1202 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1204 #ifndef CONFIG_DM_MMC
1205 memset(cfg, '\0', sizeof(*cfg));
1209 caps = esdhc_read32(®s->hostcapblt);
1211 #ifdef CONFIG_MCF5441x
1213 * MCF5441x RM declares in more points that sdhc clock speed must
1214 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1215 * from host capabilities.
1217 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1220 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1221 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1222 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1225 /* T4240 host controller capabilities register should have VS33 bit */
1226 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1227 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1230 if (caps & ESDHC_HOSTCAPBLT_VS18)
1231 voltage_caps |= MMC_VDD_165_195;
1232 if (caps & ESDHC_HOSTCAPBLT_VS30)
1233 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1234 if (caps & ESDHC_HOSTCAPBLT_VS33)
1235 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1237 cfg->name = "FSL_SDHC";
1238 #if !CONFIG_IS_ENABLED(DM_MMC)
1239 cfg->ops = &esdhc_ops;
1241 #ifdef CONFIG_SYS_SD_VOLTAGE
1242 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1244 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1246 if ((cfg->voltages & voltage_caps) == 0) {
1247 printf("voltage not supported by controller\n");
1251 if (priv->bus_width == 8)
1252 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1253 else if (priv->bus_width == 4)
1254 cfg->host_caps = MMC_MODE_4BIT;
1256 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1257 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1258 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1261 if (priv->bus_width > 0) {
1262 if (priv->bus_width < 8)
1263 cfg->host_caps &= ~MMC_MODE_8BIT;
1264 if (priv->bus_width < 4)
1265 cfg->host_caps &= ~MMC_MODE_4BIT;
1268 if (caps & ESDHC_HOSTCAPBLT_HSS)
1269 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1271 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1272 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1273 cfg->host_caps &= ~MMC_MODE_8BIT;
1276 cfg->host_caps |= priv->caps;
1278 cfg->f_min = 400000;
1279 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1281 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1283 writel(0, ®s->dllctrl);
1284 if (priv->flags & ESDHC_FLAG_USDHC) {
1285 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1286 u32 val = readl(®s->tuning_ctrl);
1288 val |= ESDHC_STD_TUNING_EN;
1289 val &= ~ESDHC_TUNING_START_TAP_MASK;
1290 val |= priv->tuning_start_tap;
1291 val &= ~ESDHC_TUNING_STEP_MASK;
1292 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1293 writel(val, ®s->tuning_ctrl);
1300 #if !CONFIG_IS_ENABLED(DM_MMC)
1301 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1302 struct fsl_esdhc_priv *priv)
1307 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1308 priv->bus_width = cfg->max_bus_width;
1309 priv->sdhc_clk = cfg->sdhc_clk;
1310 priv->wp_enable = cfg->wp_enable;
1311 priv->vs18_enable = cfg->vs18_enable;
1316 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1318 struct fsl_esdhc_plat *plat;
1319 struct fsl_esdhc_priv *priv;
1326 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1329 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1335 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1337 debug("%s xlate failure\n", __func__);
1343 ret = fsl_esdhc_init(priv, plat);
1345 debug("%s init failure\n", __func__);
1351 mmc = mmc_create(&plat->cfg, priv);
1360 int fsl_esdhc_mmc_init(bd_t *bis)
1362 struct fsl_esdhc_cfg *cfg;
1364 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1365 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1366 cfg->sdhc_clk = gd->arch.sdhc_clk;
1367 return fsl_esdhc_initialize(bis, cfg);
1371 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1372 void mmc_adapter_card_type_ident(void)
1377 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
1378 gd->arch.sdhc_adapter = card_id;
1381 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
1382 value = QIXIS_READ(brdcfg[5]);
1383 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
1384 QIXIS_WRITE(brdcfg[5], value);
1386 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
1387 value = QIXIS_READ(pwr_ctl[1]);
1388 value |= QIXIS_EVDD_BY_SDHC_VS;
1389 QIXIS_WRITE(pwr_ctl[1], value);
1391 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
1392 value = QIXIS_READ(brdcfg[5]);
1393 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
1394 QIXIS_WRITE(brdcfg[5], value);
1396 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
1398 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
1400 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
1402 case QIXIS_ESDHC_NO_ADAPTER:
1410 #ifdef CONFIG_OF_LIBFDT
1411 __weak int esdhc_status_fixup(void *blob, const char *compat)
1413 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1414 if (!hwconfig("esdhc")) {
1415 do_fixup_by_compat(blob, compat, "status", "disabled",
1416 sizeof("disabled"), 1);
1423 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1425 const char *compat = "fsl,esdhc";
1427 if (esdhc_status_fixup(blob, compat))
1430 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1431 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1432 gd->arch.sdhc_clk, 1);
1434 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1435 gd->arch.sdhc_clk, 1);
1437 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1438 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1439 (u32)(gd->arch.sdhc_adapter), 1);
1444 #if CONFIG_IS_ENABLED(DM_MMC)
1446 #include <asm/arch/clock.h>
1448 __weak void init_clk_usdhc(u32 index)
1452 static int fsl_esdhc_probe(struct udevice *dev)
1454 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1455 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1456 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1457 const void *fdt = gd->fdt_blob;
1458 int node = dev_of_offset(dev);
1459 struct esdhc_soc_data *data =
1460 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1461 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1462 struct udevice *vqmmc_dev;
1467 #if !CONFIG_IS_ENABLED(BLK)
1468 struct blk_desc *bdesc;
1472 addr = dev_read_addr(dev);
1473 if (addr == FDT_ADDR_T_NONE)
1476 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
1478 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1483 priv->flags = data->flags;
1484 priv->caps = data->caps;
1487 val = dev_read_u32_default(dev, "bus-width", -1);
1489 priv->bus_width = 8;
1491 priv->bus_width = 4;
1493 priv->bus_width = 1;
1495 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1496 priv->tuning_step = val;
1497 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1498 ESDHC_TUNING_START_TAP_DEFAULT);
1499 priv->tuning_start_tap = val;
1500 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1501 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1502 priv->strobe_dll_delay_target = val;
1504 if (dev_read_bool(dev, "non-removable")) {
1505 priv->non_removable = 1;
1507 priv->non_removable = 0;
1508 #ifdef CONFIG_DM_GPIO
1509 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1514 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1515 priv->wp_enable = 1;
1517 priv->wp_enable = 0;
1518 #ifdef CONFIG_DM_GPIO
1519 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1524 priv->vs18_enable = 0;
1526 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1528 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1529 * otherwise, emmc will work abnormally.
1531 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1533 dev_dbg(dev, "no vqmmc-supply\n");
1535 ret = regulator_set_enable(vqmmc_dev, true);
1537 dev_err(dev, "fail to enable vqmmc-supply\n");
1541 if (regulator_get_value(vqmmc_dev) == 1800000)
1542 priv->vs18_enable = 1;
1546 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1547 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
1551 * Because lack of clk driver, if SDHC clk is not enabled,
1552 * need to enable it first before this driver is invoked.
1554 * we use MXC_ESDHC_CLK to get clk freq.
1555 * If one would like to make this function work,
1556 * the aliases should be provided in dts as this:
1564 * Then if your board only supports mmc2 and mmc3, but we can
1565 * correctly get the seq as 2 and 3, then let mxc_get_clock
1569 init_clk_usdhc(dev->seq);
1571 if (IS_ENABLED(CONFIG_CLK)) {
1572 /* Assigned clock already set clock */
1573 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1575 printf("Failed to get per_clk\n");
1578 ret = clk_enable(&priv->per_clk);
1580 printf("Failed to enable per_clk\n");
1584 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1587 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1589 priv->sdhc_clk = gd->arch.sdhc_clk;
1591 if (priv->sdhc_clk <= 0) {
1592 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1597 ret = fsl_esdhc_init(priv, plat);
1599 dev_err(dev, "fsl_esdhc_init failure\n");
1604 mmc->cfg = &plat->cfg;
1606 #if !CONFIG_IS_ENABLED(BLK)
1609 /* Setup dsr related values */
1611 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1612 /* Setup the universal parts of the block interface just once */
1613 bdesc = mmc_get_blk_desc(mmc);
1614 bdesc->if_type = IF_TYPE_MMC;
1615 bdesc->removable = 1;
1616 bdesc->devnum = mmc_get_next_devnum();
1617 bdesc->block_read = mmc_bread;
1618 bdesc->block_write = mmc_bwrite;
1619 bdesc->block_erase = mmc_berase;
1621 /* setup initial part type */
1622 bdesc->part_type = mmc->cfg->part_type;
1628 return esdhc_init_common(priv, mmc);
1631 #if CONFIG_IS_ENABLED(DM_MMC)
1632 static int fsl_esdhc_get_cd(struct udevice *dev)
1634 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1636 return esdhc_getcd_common(priv);
1639 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1640 struct mmc_data *data)
1642 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1643 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1645 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1648 static int fsl_esdhc_set_ios(struct udevice *dev)
1650 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1651 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1653 return esdhc_set_ios_common(priv, &plat->mmc);
1656 static const struct dm_mmc_ops fsl_esdhc_ops = {
1657 .get_cd = fsl_esdhc_get_cd,
1658 .send_cmd = fsl_esdhc_send_cmd,
1659 .set_ios = fsl_esdhc_set_ios,
1660 #ifdef MMC_SUPPORTS_TUNING
1661 .execute_tuning = fsl_esdhc_execute_tuning,
1666 static struct esdhc_soc_data usdhc_imx7d_data = {
1667 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1668 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1670 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1671 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1674 static const struct udevice_id fsl_esdhc_ids[] = {
1675 { .compatible = "fsl,imx53-esdhc", },
1676 { .compatible = "fsl,imx6ul-usdhc", },
1677 { .compatible = "fsl,imx6sx-usdhc", },
1678 { .compatible = "fsl,imx6sl-usdhc", },
1679 { .compatible = "fsl,imx6q-usdhc", },
1680 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1681 { .compatible = "fsl,imx7ulp-usdhc", },
1682 { .compatible = "fsl,esdhc", },
1686 #if CONFIG_IS_ENABLED(BLK)
1687 static int fsl_esdhc_bind(struct udevice *dev)
1689 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1691 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1695 U_BOOT_DRIVER(fsl_esdhc) = {
1696 .name = "fsl-esdhc-mmc",
1698 .of_match = fsl_esdhc_ids,
1699 .ops = &fsl_esdhc_ops,
1700 #if CONFIG_IS_ENABLED(BLK)
1701 .bind = fsl_esdhc_bind,
1703 .probe = fsl_esdhc_probe,
1704 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1705 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),