1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
7 * Based vaguely on the pxa mmc code:
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
20 #include <power/regulator.h>
22 #include <fsl_esdhc.h>
23 #include <fdt_support.h>
26 #include <asm-generic/gpio.h>
27 #include <dm/pinctrl.h>
29 #if !CONFIG_IS_ENABLED(BLK)
30 #include "mmc_private.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
37 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
38 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
39 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
41 #define MAX_TUNING_LOOP 40
42 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
45 uint dsaddr; /* SDMA system address register */
46 uint blkattr; /* Block attributes register */
47 uint cmdarg; /* Command argument register */
48 uint xfertyp; /* Transfer type register */
49 uint cmdrsp0; /* Command response 0 register */
50 uint cmdrsp1; /* Command response 1 register */
51 uint cmdrsp2; /* Command response 2 register */
52 uint cmdrsp3; /* Command response 3 register */
53 uint datport; /* Buffer data port register */
54 uint prsstat; /* Present state register */
55 uint proctl; /* Protocol control register */
56 uint sysctl; /* System Control Register */
57 uint irqstat; /* Interrupt status register */
58 uint irqstaten; /* Interrupt status enable register */
59 uint irqsigen; /* Interrupt signal enable register */
60 uint autoc12err; /* Auto CMD error status register */
61 uint hostcapblt; /* Host controller capabilities register */
62 uint wml; /* Watermark level register */
63 uint mixctrl; /* For USDHC */
64 char reserved1[4]; /* reserved */
65 uint fevt; /* Force event register */
66 uint admaes; /* ADMA error status register */
67 uint adsaddr; /* ADMA system address register */
71 uint clktunectrlstatus;
79 uint tuning_ctrl; /* on i.MX6/7/8 */
81 uint hostver; /* Host controller version register */
82 char reserved6[4]; /* reserved */
83 uint dmaerraddr; /* DMA error address register */
84 char reserved7[4]; /* reserved */
85 uint dmaerrattr; /* DMA error attribute register */
86 char reserved8[4]; /* reserved */
87 uint hostcapblt2; /* Host controller capabilities register 2 */
88 char reserved9[8]; /* reserved */
89 uint tcr; /* Tuning control register */
90 char reserved10[28]; /* reserved */
91 uint sddirctl; /* SD direction control register */
92 char reserved11[712];/* reserved */
93 uint scr; /* eSDHC control register */
96 struct fsl_esdhc_plat {
97 struct mmc_config cfg;
101 struct esdhc_soc_data {
107 * struct fsl_esdhc_priv
109 * @esdhc_regs: registers of the sdhc controller
110 * @sdhc_clk: Current clk of the sdhc controller
111 * @bus_width: bus width, 1bit, 4bit or 8bit
114 * Following is used when Driver Model is enabled for MMC
115 * @dev: pointer for the device
116 * @non_removable: 0: removable; 1: non-removable
117 * @wp_enable: 1: enable checking wp; 0: no check
118 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
119 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
120 * @caps: controller capabilities
121 * @tuning_step: tuning step setting in tuning_ctrl register
122 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
123 * @strobe_dll_delay_target: settings in strobe_dllctrl
124 * @signal_voltage: indicating the current voltage
125 * @cd_gpio: gpio for card detection
126 * @wp_gpio: gpio for write protection
128 struct fsl_esdhc_priv {
129 struct fsl_esdhc *esdhc_regs;
130 unsigned int sdhc_clk;
134 unsigned int bus_width;
135 #if !CONFIG_IS_ENABLED(BLK)
145 u32 tuning_start_tap;
146 u32 strobe_dll_delay_target;
148 #if IS_ENABLED(CONFIG_DM_REGULATOR)
149 struct udevice *vqmmc_dev;
150 struct udevice *vmmc_dev;
152 #ifdef CONFIG_DM_GPIO
153 struct gpio_desc cd_gpio;
154 struct gpio_desc wp_gpio;
158 /* Return the XFERTYP flags for a given command and data packet */
159 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
164 xfertyp |= XFERTYP_DPSEL;
165 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
166 xfertyp |= XFERTYP_DMAEN;
168 if (data->blocks > 1) {
169 xfertyp |= XFERTYP_MSBSEL;
170 xfertyp |= XFERTYP_BCEN;
171 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
172 xfertyp |= XFERTYP_AC12EN;
176 if (data->flags & MMC_DATA_READ)
177 xfertyp |= XFERTYP_DTDSEL;
180 if (cmd->resp_type & MMC_RSP_CRC)
181 xfertyp |= XFERTYP_CCCEN;
182 if (cmd->resp_type & MMC_RSP_OPCODE)
183 xfertyp |= XFERTYP_CICEN;
184 if (cmd->resp_type & MMC_RSP_136)
185 xfertyp |= XFERTYP_RSPTYP_136;
186 else if (cmd->resp_type & MMC_RSP_BUSY)
187 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
188 else if (cmd->resp_type & MMC_RSP_PRESENT)
189 xfertyp |= XFERTYP_RSPTYP_48;
191 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
192 xfertyp |= XFERTYP_CMDTYP_ABORT;
194 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
197 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
199 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
201 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
202 struct mmc_data *data)
204 struct fsl_esdhc *regs = priv->esdhc_regs;
212 if (data->flags & MMC_DATA_READ) {
213 blocks = data->blocks;
216 start = get_timer(0);
217 size = data->blocksize;
218 irqstat = esdhc_read32(®s->irqstat);
219 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
220 if (get_timer(start) > PIO_TIMEOUT) {
221 printf("\nData Read Failed in PIO Mode.");
225 while (size && (!(irqstat & IRQSTAT_TC))) {
226 udelay(100); /* Wait before last byte transfer complete */
227 irqstat = esdhc_read32(®s->irqstat);
228 databuf = in_le32(®s->datport);
229 *((uint *)buffer) = databuf;
236 blocks = data->blocks;
237 buffer = (char *)data->src;
239 start = get_timer(0);
240 size = data->blocksize;
241 irqstat = esdhc_read32(®s->irqstat);
242 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
243 if (get_timer(start) > PIO_TIMEOUT) {
244 printf("\nData Write Failed in PIO Mode.");
248 while (size && (!(irqstat & IRQSTAT_TC))) {
249 udelay(100); /* Wait before last byte transfer complete */
250 databuf = *((uint *)buffer);
253 irqstat = esdhc_read32(®s->irqstat);
254 out_le32(®s->datport, databuf);
262 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
263 struct mmc_data *data)
266 struct fsl_esdhc *regs = priv->esdhc_regs;
267 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
268 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
273 wml_value = data->blocksize/4;
275 if (data->flags & MMC_DATA_READ) {
276 if (wml_value > WML_RD_WML_MAX)
277 wml_value = WML_RD_WML_MAX_VAL;
279 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
280 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
281 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
282 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
283 addr = virt_to_phys((void *)(data->dest));
284 if (upper_32_bits(addr))
285 printf("Error found for upper 32 bits\n");
287 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
289 esdhc_write32(®s->dsaddr, (u32)data->dest);
293 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
294 flush_dcache_range((ulong)data->src,
295 (ulong)data->src+data->blocks
298 if (wml_value > WML_WR_WML_MAX)
299 wml_value = WML_WR_WML_MAX_VAL;
300 if (priv->wp_enable) {
301 if ((esdhc_read32(®s->prsstat) &
302 PRSSTAT_WPSPL) == 0) {
303 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
307 #ifdef CONFIG_DM_GPIO
308 if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
309 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
315 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
317 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
318 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
319 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
320 addr = virt_to_phys((void *)(data->src));
321 if (upper_32_bits(addr))
322 printf("Error found for upper 32 bits\n");
324 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
326 esdhc_write32(®s->dsaddr, (u32)data->src);
331 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
333 /* Calculate the timeout period for data transactions */
335 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
336 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
337 * So, Number of SD Clock cycles for 0.25sec should be minimum
338 * (SD Clock/sec * 0.25 sec) SD Clock cycles
339 * = (mmc->clock * 1/4) SD Clock cycles
341 * => (2^(timeout+13)) >= mmc->clock * 1/4
342 * Taking log2 both the sides
343 * => timeout + 13 >= log2(mmc->clock/4)
344 * Rounding up to next power of 2
345 * => timeout + 13 = log2(mmc->clock/4) + 1
346 * => timeout + 13 = fls(mmc->clock/4)
348 * However, the MMC spec "It is strongly recommended for hosts to
349 * implement more than 500ms timeout value even if the card
350 * indicates the 250ms maximum busy length." Even the previous
351 * value of 300ms is known to be insufficient for some cards.
353 * => timeout + 13 = fls(mmc->clock/2)
355 timeout = fls(mmc->clock/2);
364 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
365 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
369 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
372 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
377 static void check_and_invalidate_dcache_range
378 (struct mmc_cmd *cmd,
379 struct mmc_data *data) {
382 unsigned size = roundup(ARCH_DMA_MINALIGN,
383 data->blocks*data->blocksize);
384 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
385 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
388 addr = virt_to_phys((void *)(data->dest));
389 if (upper_32_bits(addr))
390 printf("Error found for upper 32 bits\n");
392 start = lower_32_bits(addr);
394 start = (unsigned)data->dest;
397 invalidate_dcache_range(start, end);
400 #ifdef CONFIG_MCF5441x
402 * Swaps 32-bit words to little-endian byte order.
404 static inline void sd_swap_dma_buff(struct mmc_data *data)
406 int i, size = data->blocksize >> 2;
407 u32 *buffer = (u32 *)data->dest;
410 while (data->blocks--) {
411 for (i = 0; i < size; i++) {
412 sw = __sw32(*buffer);
420 * Sends a command out on the bus. Takes the mmc pointer,
421 * a command pointer, and an optional data pointer.
423 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
424 struct mmc_cmd *cmd, struct mmc_data *data)
429 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
430 struct fsl_esdhc *regs = priv->esdhc_regs;
433 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
434 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
438 esdhc_write32(®s->irqstat, -1);
442 /* Wait for the bus to be idle */
443 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
444 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
447 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
450 /* Wait at least 8 SD clock cycles before the next command */
452 * Note: This is way more than 8 cycles, but 1ms seems to
453 * resolve timing issues with some cards
457 /* Set up for a data transfer if we have one */
459 err = esdhc_setup_data(priv, mmc, data);
463 if (data->flags & MMC_DATA_READ)
464 check_and_invalidate_dcache_range(cmd, data);
467 /* Figure out the transfer arguments */
468 xfertyp = esdhc_xfertyp(cmd, data);
471 esdhc_write32(®s->irqsigen, 0);
473 /* Send the command */
474 esdhc_write32(®s->cmdarg, cmd->cmdarg);
475 #if defined(CONFIG_FSL_USDHC)
476 esdhc_write32(®s->mixctrl,
477 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
478 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
479 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
481 esdhc_write32(®s->xfertyp, xfertyp);
484 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
485 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
488 /* Wait for the command to complete */
489 start = get_timer(0);
490 while (!(esdhc_read32(®s->irqstat) & flags)) {
491 if (get_timer(start) > 1000) {
497 irqstat = esdhc_read32(®s->irqstat);
499 if (irqstat & CMD_ERR) {
504 if (irqstat & IRQSTAT_CTOE) {
509 /* Switch voltage to 1.8V if CMD11 succeeded */
510 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
511 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
513 printf("Run CMD11 1.8V switch\n");
514 /* Sleep for 5 ms - max time for card to switch to 1.8V */
518 /* Workaround for ESDHC errata ENGcm03648 */
519 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
522 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
523 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
530 printf("Timeout waiting for DAT0 to go high!\n");
536 /* Copy the response to the response buffer */
537 if (cmd->resp_type & MMC_RSP_136) {
538 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
540 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
541 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
542 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
543 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
544 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
545 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
546 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
547 cmd->response[3] = (cmdrsp0 << 8);
549 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
551 /* Wait until all of the blocks are transferred */
553 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
554 esdhc_pio_read_write(priv, data);
556 flags = DATA_COMPLETE;
557 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
558 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
563 irqstat = esdhc_read32(®s->irqstat);
565 if (irqstat & IRQSTAT_DTOE) {
570 if (irqstat & DATA_ERR) {
574 } while ((irqstat & flags) != flags);
577 * Need invalidate the dcache here again to avoid any
578 * cache-fill during the DMA operations such as the
579 * speculative pre-fetching etc.
581 if (data->flags & MMC_DATA_READ) {
582 check_and_invalidate_dcache_range(cmd, data);
583 #ifdef CONFIG_MCF5441x
584 sd_swap_dma_buff(data);
591 /* Reset CMD and DATA portions on error */
593 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
595 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
599 esdhc_write32(®s->sysctl,
600 esdhc_read32(®s->sysctl) |
602 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
606 /* If this was CMD11, then notify that power cycle is needed */
607 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
608 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
611 esdhc_write32(®s->irqstat, -1);
616 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
618 struct fsl_esdhc *regs = priv->esdhc_regs;
622 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
623 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
630 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
631 int sdhc_clk = priv->sdhc_clk;
634 if (clock < mmc->cfg->f_min)
635 clock = mmc->cfg->f_min;
637 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
640 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
646 clk = (pre_div << 8) | (div << 4);
648 #ifdef CONFIG_FSL_USDHC
649 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
651 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
654 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
658 #ifdef CONFIG_FSL_USDHC
659 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
661 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
667 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
668 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
670 struct fsl_esdhc *regs = priv->esdhc_regs;
674 value = esdhc_read32(®s->sysctl);
677 value |= SYSCTL_CKEN;
679 value &= ~SYSCTL_CKEN;
681 esdhc_write32(®s->sysctl, value);
684 value = PRSSTAT_SDSTB;
685 while (!(esdhc_read32(®s->prsstat) & value)) {
687 printf("fsl_esdhc: Internal clock never stabilised.\n");
696 #ifdef MMC_SUPPORTS_TUNING
697 static int esdhc_change_pinstate(struct udevice *dev)
699 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
702 switch (priv->mode) {
705 ret = pinctrl_select_state(dev, "state_100mhz");
710 ret = pinctrl_select_state(dev, "state_200mhz");
713 ret = pinctrl_select_state(dev, "default");
718 printf("%s %d error\n", __func__, priv->mode);
723 static void esdhc_reset_tuning(struct mmc *mmc)
725 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
726 struct fsl_esdhc *regs = priv->esdhc_regs;
728 if (priv->flags & ESDHC_FLAG_USDHC) {
729 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
730 esdhc_clrbits32(®s->autoc12err,
731 MIX_CTRL_SMPCLK_SEL |
737 static void esdhc_set_strobe_dll(struct mmc *mmc)
739 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
740 struct fsl_esdhc *regs = priv->esdhc_regs;
743 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
744 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
747 * enable strobe dll ctrl and adjust the delay target
748 * for the uSDHC loopback read clock
750 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
751 (priv->strobe_dll_delay_target <<
752 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
753 writel(val, ®s->strobe_dllctrl);
754 /* wait 1us to make sure strobe dll status register stable */
756 val = readl(®s->strobe_dllstat);
757 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
758 pr_warn("HS400 strobe DLL status REF not lock!\n");
759 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
760 pr_warn("HS400 strobe DLL status SLV not lock!\n");
764 static int esdhc_set_timing(struct mmc *mmc)
766 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
767 struct fsl_esdhc *regs = priv->esdhc_regs;
770 mixctrl = readl(®s->mixctrl);
771 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
773 switch (mmc->selected_mode) {
776 esdhc_reset_tuning(mmc);
777 writel(mixctrl, ®s->mixctrl);
780 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
781 writel(mixctrl, ®s->mixctrl);
782 esdhc_set_strobe_dll(mmc);
792 writel(mixctrl, ®s->mixctrl);
796 mixctrl |= MIX_CTRL_DDREN;
797 writel(mixctrl, ®s->mixctrl);
800 printf("Not supported %d\n", mmc->selected_mode);
804 priv->mode = mmc->selected_mode;
806 return esdhc_change_pinstate(mmc->dev);
809 static int esdhc_set_voltage(struct mmc *mmc)
811 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
812 struct fsl_esdhc *regs = priv->esdhc_regs;
815 priv->signal_voltage = mmc->signal_voltage;
816 switch (mmc->signal_voltage) {
817 case MMC_SIGNAL_VOLTAGE_330:
818 if (priv->vs18_enable)
820 #if CONFIG_IS_ENABLED(DM_REGULATOR)
821 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
822 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
824 printf("Setting to 3.3V error");
832 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
833 if (!(esdhc_read32(®s->vendorspec) &
834 ESDHC_VENDORSPEC_VSELECT))
838 case MMC_SIGNAL_VOLTAGE_180:
839 #if CONFIG_IS_ENABLED(DM_REGULATOR)
840 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
841 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
843 printf("Setting to 1.8V error");
848 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
849 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
853 case MMC_SIGNAL_VOLTAGE_120:
860 static void esdhc_stop_tuning(struct mmc *mmc)
864 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
866 cmd.resp_type = MMC_RSP_R1b;
868 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
871 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
873 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
874 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
875 struct fsl_esdhc *regs = priv->esdhc_regs;
876 struct mmc *mmc = &plat->mmc;
877 u32 irqstaten = readl(®s->irqstaten);
878 u32 irqsigen = readl(®s->irqsigen);
879 int i, ret = -ETIMEDOUT;
882 /* clock tuning is not needed for upto 52MHz */
883 if (mmc->clock <= 52000000)
886 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
887 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
888 val = readl(®s->autoc12err);
889 mixctrl = readl(®s->mixctrl);
890 val &= ~MIX_CTRL_SMPCLK_SEL;
891 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
893 val |= MIX_CTRL_EXE_TUNE;
894 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
896 writel(val, ®s->autoc12err);
897 writel(mixctrl, ®s->mixctrl);
900 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
901 mixctrl = readl(®s->mixctrl);
902 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
903 writel(mixctrl, ®s->mixctrl);
905 writel(IRQSTATEN_BRR, ®s->irqstaten);
906 writel(IRQSTATEN_BRR, ®s->irqsigen);
909 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
910 * of loops reaches 40 times.
912 for (i = 0; i < MAX_TUNING_LOOP; i++) {
915 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
916 if (mmc->bus_width == 8)
917 writel(0x7080, ®s->blkattr);
918 else if (mmc->bus_width == 4)
919 writel(0x7040, ®s->blkattr);
921 writel(0x7040, ®s->blkattr);
924 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
925 val = readl(®s->mixctrl);
926 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
927 writel(val, ®s->mixctrl);
929 /* We are using STD tuning, no need to check return value */
930 mmc_send_tuning(mmc, opcode, NULL);
932 ctrl = readl(®s->autoc12err);
933 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
934 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
936 * need to wait some time, make sure sd/mmc fininsh
937 * send out tuning data, otherwise, the sd/mmc can't
938 * response to any command when the card still out
939 * put the tuning data.
946 /* Add 1ms delay for SD and eMMC */
950 writel(irqstaten, ®s->irqstaten);
951 writel(irqsigen, ®s->irqsigen);
953 esdhc_stop_tuning(mmc);
959 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
961 struct fsl_esdhc *regs = priv->esdhc_regs;
962 int ret __maybe_unused;
964 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
965 /* Select to use peripheral clock */
966 esdhc_clock_control(priv, false);
967 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
968 esdhc_clock_control(priv, true);
970 /* Set the clock speed */
971 if (priv->clock != mmc->clock)
972 set_sysctl(priv, mmc, mmc->clock);
974 #ifdef MMC_SUPPORTS_TUNING
975 if (mmc->clk_disable) {
976 #ifdef CONFIG_FSL_USDHC
977 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
979 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
982 #ifdef CONFIG_FSL_USDHC
983 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
986 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
990 if (priv->mode != mmc->selected_mode) {
991 ret = esdhc_set_timing(mmc);
993 printf("esdhc_set_timing error %d\n", ret);
998 if (priv->signal_voltage != mmc->signal_voltage) {
999 ret = esdhc_set_voltage(mmc);
1001 printf("esdhc_set_voltage error %d\n", ret);
1007 /* Set the bus width */
1008 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1010 if (mmc->bus_width == 4)
1011 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1012 else if (mmc->bus_width == 8)
1013 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1018 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1020 struct fsl_esdhc *regs = priv->esdhc_regs;
1023 /* Reset the entire host controller */
1024 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1026 /* Wait until the controller is available */
1027 start = get_timer(0);
1028 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1029 if (get_timer(start) > 1000)
1033 #if defined(CONFIG_FSL_USDHC)
1034 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1035 esdhc_write32(®s->mmcboot, 0x0);
1036 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1037 esdhc_write32(®s->mixctrl, 0x0);
1038 esdhc_write32(®s->clktunectrlstatus, 0x0);
1040 /* Put VEND_SPEC to default value */
1041 if (priv->vs18_enable)
1042 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1043 ESDHC_VENDORSPEC_VSELECT));
1045 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1047 /* Disable DLL_CTRL delay line */
1048 esdhc_write32(®s->dllctrl, 0x0);
1052 /* Enable cache snooping */
1053 esdhc_write32(®s->scr, 0x00000040);
1056 #ifndef CONFIG_FSL_USDHC
1057 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1059 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1062 /* Set the initial clock speed */
1063 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1065 /* Disable the BRR and BWR bits in IRQSTAT */
1066 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1068 #ifdef CONFIG_MCF5441x
1069 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1071 /* Put the PROCTL reg back to the default */
1072 esdhc_write32(®s->proctl, PROCTL_INIT);
1075 /* Set timout to the maximum value */
1076 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1081 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1083 struct fsl_esdhc *regs = priv->esdhc_regs;
1086 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1087 if (CONFIG_ESDHC_DETECT_QUIRK)
1091 #if CONFIG_IS_ENABLED(DM_MMC)
1092 if (priv->non_removable)
1094 #ifdef CONFIG_DM_GPIO
1095 if (dm_gpio_is_valid(&priv->cd_gpio))
1096 return dm_gpio_get_value(&priv->cd_gpio);
1100 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1106 static int esdhc_reset(struct fsl_esdhc *regs)
1110 /* reset the controller */
1111 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1113 /* hardware clears the bit when it is done */
1114 start = get_timer(0);
1115 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1116 if (get_timer(start) > 100) {
1117 printf("MMC/SD: Reset never completed.\n");
1125 #if !CONFIG_IS_ENABLED(DM_MMC)
1126 static int esdhc_getcd(struct mmc *mmc)
1128 struct fsl_esdhc_priv *priv = mmc->priv;
1130 return esdhc_getcd_common(priv);
1133 static int esdhc_init(struct mmc *mmc)
1135 struct fsl_esdhc_priv *priv = mmc->priv;
1137 return esdhc_init_common(priv, mmc);
1140 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1141 struct mmc_data *data)
1143 struct fsl_esdhc_priv *priv = mmc->priv;
1145 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1148 static int esdhc_set_ios(struct mmc *mmc)
1150 struct fsl_esdhc_priv *priv = mmc->priv;
1152 return esdhc_set_ios_common(priv, mmc);
1155 static const struct mmc_ops esdhc_ops = {
1156 .getcd = esdhc_getcd,
1158 .send_cmd = esdhc_send_cmd,
1159 .set_ios = esdhc_set_ios,
1163 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1164 struct fsl_esdhc_plat *plat)
1166 struct mmc_config *cfg;
1167 struct fsl_esdhc *regs;
1168 u32 caps, voltage_caps;
1174 regs = priv->esdhc_regs;
1176 /* First reset the eSDHC controller */
1177 ret = esdhc_reset(regs);
1181 #ifdef CONFIG_MCF5441x
1182 /* ColdFire, using SDHC_DATA[3] for card detection */
1183 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1186 #ifndef CONFIG_FSL_USDHC
1187 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1188 | SYSCTL_IPGEN | SYSCTL_CKEN);
1189 /* Clearing tuning bits in case ROM has set it already */
1190 esdhc_write32(®s->mixctrl, 0);
1191 esdhc_write32(®s->autoc12err, 0);
1192 esdhc_write32(®s->clktunectrlstatus, 0);
1194 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1195 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1198 if (priv->vs18_enable)
1199 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1201 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1203 #ifndef CONFIG_DM_MMC
1204 memset(cfg, '\0', sizeof(*cfg));
1208 caps = esdhc_read32(®s->hostcapblt);
1210 #ifdef CONFIG_MCF5441x
1212 * MCF5441x RM declares in more points that sdhc clock speed must
1213 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1214 * from host capabilities.
1216 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1219 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1220 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1221 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1224 /* T4240 host controller capabilities register should have VS33 bit */
1225 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1226 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1229 if (caps & ESDHC_HOSTCAPBLT_VS18)
1230 voltage_caps |= MMC_VDD_165_195;
1231 if (caps & ESDHC_HOSTCAPBLT_VS30)
1232 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1233 if (caps & ESDHC_HOSTCAPBLT_VS33)
1234 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1236 cfg->name = "FSL_SDHC";
1237 #if !CONFIG_IS_ENABLED(DM_MMC)
1238 cfg->ops = &esdhc_ops;
1240 #ifdef CONFIG_SYS_SD_VOLTAGE
1241 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1243 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1245 if ((cfg->voltages & voltage_caps) == 0) {
1246 printf("voltage not supported by controller\n");
1250 if (priv->bus_width == 8)
1251 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1252 else if (priv->bus_width == 4)
1253 cfg->host_caps = MMC_MODE_4BIT;
1255 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1256 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1257 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1260 if (priv->bus_width > 0) {
1261 if (priv->bus_width < 8)
1262 cfg->host_caps &= ~MMC_MODE_8BIT;
1263 if (priv->bus_width < 4)
1264 cfg->host_caps &= ~MMC_MODE_4BIT;
1267 if (caps & ESDHC_HOSTCAPBLT_HSS)
1268 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1270 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1271 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1272 cfg->host_caps &= ~MMC_MODE_8BIT;
1275 cfg->host_caps |= priv->caps;
1277 cfg->f_min = 400000;
1278 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1280 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1282 writel(0, ®s->dllctrl);
1283 if (priv->flags & ESDHC_FLAG_USDHC) {
1284 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1285 u32 val = readl(®s->tuning_ctrl);
1287 val |= ESDHC_STD_TUNING_EN;
1288 val &= ~ESDHC_TUNING_START_TAP_MASK;
1289 val |= priv->tuning_start_tap;
1290 val &= ~ESDHC_TUNING_STEP_MASK;
1291 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1292 writel(val, ®s->tuning_ctrl);
1299 #if !CONFIG_IS_ENABLED(DM_MMC)
1300 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1301 struct fsl_esdhc_priv *priv)
1306 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1307 priv->bus_width = cfg->max_bus_width;
1308 priv->sdhc_clk = cfg->sdhc_clk;
1309 priv->wp_enable = cfg->wp_enable;
1310 priv->vs18_enable = cfg->vs18_enable;
1315 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1317 struct fsl_esdhc_plat *plat;
1318 struct fsl_esdhc_priv *priv;
1325 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1328 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1334 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1336 debug("%s xlate failure\n", __func__);
1342 ret = fsl_esdhc_init(priv, plat);
1344 debug("%s init failure\n", __func__);
1350 mmc = mmc_create(&plat->cfg, priv);
1359 int fsl_esdhc_mmc_init(bd_t *bis)
1361 struct fsl_esdhc_cfg *cfg;
1363 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1364 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1365 cfg->sdhc_clk = gd->arch.sdhc_clk;
1366 return fsl_esdhc_initialize(bis, cfg);
1370 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1371 void mmc_adapter_card_type_ident(void)
1376 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
1377 gd->arch.sdhc_adapter = card_id;
1380 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
1381 value = QIXIS_READ(brdcfg[5]);
1382 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
1383 QIXIS_WRITE(brdcfg[5], value);
1385 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
1386 value = QIXIS_READ(pwr_ctl[1]);
1387 value |= QIXIS_EVDD_BY_SDHC_VS;
1388 QIXIS_WRITE(pwr_ctl[1], value);
1390 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
1391 value = QIXIS_READ(brdcfg[5]);
1392 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
1393 QIXIS_WRITE(brdcfg[5], value);
1395 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
1397 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
1399 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
1401 case QIXIS_ESDHC_NO_ADAPTER:
1409 #ifdef CONFIG_OF_LIBFDT
1410 __weak int esdhc_status_fixup(void *blob, const char *compat)
1412 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1413 if (!hwconfig("esdhc")) {
1414 do_fixup_by_compat(blob, compat, "status", "disabled",
1415 sizeof("disabled"), 1);
1422 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1424 const char *compat = "fsl,esdhc";
1426 if (esdhc_status_fixup(blob, compat))
1429 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1430 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1431 gd->arch.sdhc_clk, 1);
1433 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1434 gd->arch.sdhc_clk, 1);
1436 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1437 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1438 (u32)(gd->arch.sdhc_adapter), 1);
1443 #if CONFIG_IS_ENABLED(DM_MMC)
1445 #include <asm/arch/clock.h>
1447 __weak void init_clk_usdhc(u32 index)
1451 static int fsl_esdhc_probe(struct udevice *dev)
1453 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1454 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1455 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1456 const void *fdt = gd->fdt_blob;
1457 int node = dev_of_offset(dev);
1458 struct esdhc_soc_data *data =
1459 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1460 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1461 struct udevice *vqmmc_dev;
1466 #if !CONFIG_IS_ENABLED(BLK)
1467 struct blk_desc *bdesc;
1471 addr = dev_read_addr(dev);
1472 if (addr == FDT_ADDR_T_NONE)
1475 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
1477 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1482 priv->flags = data->flags;
1483 priv->caps = data->caps;
1486 val = dev_read_u32_default(dev, "bus-width", -1);
1488 priv->bus_width = 8;
1490 priv->bus_width = 4;
1492 priv->bus_width = 1;
1494 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1495 priv->tuning_step = val;
1496 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1497 ESDHC_TUNING_START_TAP_DEFAULT);
1498 priv->tuning_start_tap = val;
1499 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1500 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1501 priv->strobe_dll_delay_target = val;
1503 if (dev_read_bool(dev, "non-removable")) {
1504 priv->non_removable = 1;
1506 priv->non_removable = 0;
1507 #ifdef CONFIG_DM_GPIO
1508 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1513 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1514 priv->wp_enable = 1;
1516 priv->wp_enable = 0;
1517 #ifdef CONFIG_DM_GPIO
1518 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1523 priv->vs18_enable = 0;
1525 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1527 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1528 * otherwise, emmc will work abnormally.
1530 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1532 dev_dbg(dev, "no vqmmc-supply\n");
1534 ret = regulator_set_enable(vqmmc_dev, true);
1536 dev_err(dev, "fail to enable vqmmc-supply\n");
1540 if (regulator_get_value(vqmmc_dev) == 1800000)
1541 priv->vs18_enable = 1;
1545 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1546 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
1550 * Because lack of clk driver, if SDHC clk is not enabled,
1551 * need to enable it first before this driver is invoked.
1553 * we use MXC_ESDHC_CLK to get clk freq.
1554 * If one would like to make this function work,
1555 * the aliases should be provided in dts as this:
1563 * Then if your board only supports mmc2 and mmc3, but we can
1564 * correctly get the seq as 2 and 3, then let mxc_get_clock
1568 init_clk_usdhc(dev->seq);
1570 if (IS_ENABLED(CONFIG_CLK)) {
1571 /* Assigned clock already set clock */
1572 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1574 printf("Failed to get per_clk\n");
1577 ret = clk_enable(&priv->per_clk);
1579 printf("Failed to enable per_clk\n");
1583 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1586 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1588 priv->sdhc_clk = gd->arch.sdhc_clk;
1590 if (priv->sdhc_clk <= 0) {
1591 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1596 ret = fsl_esdhc_init(priv, plat);
1598 dev_err(dev, "fsl_esdhc_init failure\n");
1603 mmc->cfg = &plat->cfg;
1605 #if !CONFIG_IS_ENABLED(BLK)
1608 /* Setup dsr related values */
1610 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1611 /* Setup the universal parts of the block interface just once */
1612 bdesc = mmc_get_blk_desc(mmc);
1613 bdesc->if_type = IF_TYPE_MMC;
1614 bdesc->removable = 1;
1615 bdesc->devnum = mmc_get_next_devnum();
1616 bdesc->block_read = mmc_bread;
1617 bdesc->block_write = mmc_bwrite;
1618 bdesc->block_erase = mmc_berase;
1620 /* setup initial part type */
1621 bdesc->part_type = mmc->cfg->part_type;
1627 return esdhc_init_common(priv, mmc);
1630 #if CONFIG_IS_ENABLED(DM_MMC)
1631 static int fsl_esdhc_get_cd(struct udevice *dev)
1633 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1635 return esdhc_getcd_common(priv);
1638 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1639 struct mmc_data *data)
1641 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1642 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1644 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1647 static int fsl_esdhc_set_ios(struct udevice *dev)
1649 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1650 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1652 return esdhc_set_ios_common(priv, &plat->mmc);
1655 static const struct dm_mmc_ops fsl_esdhc_ops = {
1656 .get_cd = fsl_esdhc_get_cd,
1657 .send_cmd = fsl_esdhc_send_cmd,
1658 .set_ios = fsl_esdhc_set_ios,
1659 #ifdef MMC_SUPPORTS_TUNING
1660 .execute_tuning = fsl_esdhc_execute_tuning,
1665 static struct esdhc_soc_data usdhc_imx7d_data = {
1666 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1667 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1669 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1670 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1673 static const struct udevice_id fsl_esdhc_ids[] = {
1674 { .compatible = "fsl,imx53-esdhc", },
1675 { .compatible = "fsl,imx6ul-usdhc", },
1676 { .compatible = "fsl,imx6sx-usdhc", },
1677 { .compatible = "fsl,imx6sl-usdhc", },
1678 { .compatible = "fsl,imx6q-usdhc", },
1679 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1680 { .compatible = "fsl,imx7ulp-usdhc", },
1681 { .compatible = "fsl,esdhc", },
1685 #if CONFIG_IS_ENABLED(BLK)
1686 static int fsl_esdhc_bind(struct udevice *dev)
1688 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1690 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1694 U_BOOT_DRIVER(fsl_esdhc) = {
1695 .name = "fsl-esdhc-mmc",
1697 .of_match = fsl_esdhc_ids,
1698 .ops = &fsl_esdhc_ops,
1699 #if CONFIG_IS_ENABLED(BLK)
1700 .bind = fsl_esdhc_bind,
1702 .probe = fsl_esdhc_probe,
1703 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1704 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),