drivers/mmc/dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2012 SAMSUNG Electronics
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   6  */
   7
   8 #include <bouncebuf.h>
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <memalign.h>
  15 #include <mmc.h>
  16 #include <dwmmc.h>
  17 #include <wait_bit.h>
  18 #include <asm/cache.h>
  19 #include <power/regulator.h>
  20
  21 #define PAGE_SIZE 4096
  22
  23 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  24 {
  25         unsigned long timeout = 1000;
  26         u32 ctrl;
  27
  28         dwmci_writel(host, DWMCI_CTRL, value);
  29
  30         while (timeout--) {
  31                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  32                 if (!(ctrl & DWMCI_RESET_ALL))
  33                         return 1;
  34         }
  35         return 0;
  36 }
  37
  38 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  39                 u32 desc0, u32 desc1, u32 desc2)
  40 {
  41         struct dwmci_idmac *desc = idmac;
  42
  43         desc->flags = desc0;
  44         desc->cnt = desc1;
  45         desc->addr = desc2;
  46         desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
  47 }
  48
  49 static void dwmci_prepare_data(struct dwmci_host *host,
  50                                struct mmc_data *data,
  51                                struct dwmci_idmac *cur_idmac,
  52                                void *bounce_buffer)
  53 {
  54         unsigned long ctrl;
  55         unsigned int i = 0, flags, cnt, blk_cnt;
  56         ulong data_start, data_end;
  57
  58
  59         blk_cnt = data->blocks;
  60
  61         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  62
  63         /* Clear IDMAC interrupt */
  64         dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
  65
  66         data_start = (ulong)cur_idmac;
  67         dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
  68
  69         do {
  70                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  71                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  72                 if (blk_cnt <= 8) {
  73                         flags |= DWMCI_IDMAC_LD;
  74                         cnt = data->blocksize * blk_cnt;
  75                 } else
  76                         cnt = data->blocksize * 8;
  77
  78                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  79                                     (ulong)bounce_buffer + (i * PAGE_SIZE));
  80
  81                 cur_idmac++;
  82                 if (blk_cnt <= 8)
  83                         break;
  84                 blk_cnt -= 8;
  85                 i++;
  86         } while(1);
  87
  88         data_end = (ulong)cur_idmac;
  89         flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
  90
  91         ctrl = dwmci_readl(host, DWMCI_CTRL);
  92         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  93         dwmci_writel(host, DWMCI_CTRL, ctrl);
  94
  95         ctrl = dwmci_readl(host, DWMCI_BMOD);
  96         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  97         dwmci_writel(host, DWMCI_BMOD, ctrl);
  98
  99         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
 100         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
 101 }
 102
 103 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
 104 {
 105         u32 timeout = 20000;
 106
 107         *len = dwmci_readl(host, DWMCI_STATUS);
 108         while (--timeout && (*len & bit)) {
 109                 udelay(200);
 110                 *len = dwmci_readl(host, DWMCI_STATUS);
 111         }
 112
 113         if (!timeout) {
 114                 debug("%s: FIFO underflow timeout\n", __func__);
 115                 return -ETIMEDOUT;
 116         }
 117
 118         return 0;
 119 }
 120
 121 static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
 122 {
 123         unsigned int timeout;
 124
 125         timeout = size * 8;     /* counting in bits */
 126         timeout *= 10;          /* wait 10 times as long */
 127         timeout /= mmc->clock;
 128         timeout /= mmc->bus_width;
 129         timeout /= mmc->ddr_mode ? 2 : 1;
 130         timeout *= 1000;        /* counting in msec */
 131         timeout = (timeout < 1000) ? 1000 : timeout;
 132
 133         return timeout;
 134 }
 135
 136 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
 137 {
 138         struct mmc *mmc = host->mmc;
 139         int ret = 0;
 140         u32 timeout, mask, size, i, len = 0;
 141         u32 *buf = NULL;
 142         ulong start = get_timer(0);
 143         u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
 144                             RX_WMARK_SHIFT) + 1) * 2;
 145
 146         size = data->blocksize * data->blocks;
 147         if (data->flags == MMC_DATA_READ)
 148                 buf = (unsigned int *)data->dest;
 149         else
 150                 buf = (unsigned int *)data->src;
 151
 152         timeout = dwmci_get_timeout(mmc, size);
 153
 154         size /= 4;
 155
 156         for (;;) {
 157                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 158                 /* Error during data transfer. */
 159                 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 160                         debug("%s: DATA ERROR!\n", __func__);
 161                         ret = -EINVAL;
 162                         break;
 163                 }
 164
 165                 if (host->fifo_mode && size) {
 166                         len = 0;
 167                         if (data->flags == MMC_DATA_READ &&
 168                             (mask & DWMCI_INTMSK_RXDR)) {
 169                                 while (size) {
 170                                         ret = dwmci_fifo_ready(host,
 171                                                         DWMCI_FIFO_EMPTY,
 172                                                         &len);
 173                                         if (ret < 0)
 174                                                 break;
 175
 176                                         len = (len >> DWMCI_FIFO_SHIFT) &
 177                                                     DWMCI_FIFO_MASK;
 178                                         len = min(size, len);
 179                                         for (i = 0; i < len; i++)
 180                                                 *buf++ =
 181                                                 dwmci_readl(host, DWMCI_DATA);
 182                                         size = size > len ? (size - len) : 0;
 183                                 }
 184                                 dwmci_writel(host, DWMCI_RINTSTS,
 185                                              DWMCI_INTMSK_RXDR);
 186                         } else if (data->flags == MMC_DATA_WRITE &&
 187                                    (mask & DWMCI_INTMSK_TXDR)) {
 188                                 while (size) {
 189                                         ret = dwmci_fifo_ready(host,
 190                                                         DWMCI_FIFO_FULL,
 191                                                         &len);
 192                                         if (ret < 0)
 193                                                 break;
 194
 195                                         len = fifo_depth - ((len >>
 196                                                    DWMCI_FIFO_SHIFT) &
 197                                                    DWMCI_FIFO_MASK);
 198                                         len = min(size, len);
 199                                         for (i = 0; i < len; i++)
 200                                                 dwmci_writel(host, DWMCI_DATA,
 201                                                              *buf++);
 202                                         size = size > len ? (size - len) : 0;
 203                                 }
 204                                 dwmci_writel(host, DWMCI_RINTSTS,
 205                                              DWMCI_INTMSK_TXDR);
 206                         }
 207                 }
 208
 209                 /* Data arrived correctly. */
 210                 if (mask & DWMCI_INTMSK_DTO) {
 211                         ret = 0;
 212                         break;
 213                 }
 214
 215                 /* Check for timeout. */
 216                 if (get_timer(start) > timeout) {
 217                         debug("%s: Timeout waiting for data!\n",
 218                               __func__);
 219                         ret = -ETIMEDOUT;
 220                         break;
 221                 }
 222         }
 223
 224         dwmci_writel(host, DWMCI_RINTSTS, mask);
 225
 226         return ret;
 227 }
 228
 229 static int dwmci_set_transfer_mode(struct dwmci_host *host,
 230                 struct mmc_data *data)
 231 {
 232         unsigned long mode;
 233
 234         mode = DWMCI_CMD_DATA_EXP;
 235         if (data->flags & MMC_DATA_WRITE)
 236                 mode |= DWMCI_CMD_RW;
 237
 238         return mode;
 239 }
 240
 241 #ifdef CONFIG_DM_MMC
 242 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 243                    struct mmc_data *data)
 244 {
 245         struct mmc *mmc = mmc_get_mmc_dev(dev);
 246 #else
 247 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 248                 struct mmc_data *data)
 249 {
 250 #endif
 251         struct dwmci_host *host = mmc->priv;
 252         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 253                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 254         int ret = 0, flags = 0, i;
 255         unsigned int timeout = 500;
 256         u32 retry = 100000;
 257         u32 mask, ctrl;
 258         ulong start = get_timer(0);
 259         struct bounce_buffer bbstate;
 260
 261         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 262                 if (get_timer(start) > timeout) {
 263                         debug("%s: Timeout on data busy\n", __func__);
 264                         return -ETIMEDOUT;
 265                 }
 266         }
 267
 268         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 269
 270         if (data) {
 271                 if (host->fifo_mode) {
 272                         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
 273                         dwmci_writel(host, DWMCI_BYTCNT,
 274                                      data->blocksize * data->blocks);
 275                         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
 276                 } else {
 277                         if (data->flags == MMC_DATA_READ) {
 278                                 ret = bounce_buffer_start(&bbstate,
 279                                                 (void*)data->dest,
 280                                                 data->blocksize *
 281                                                 data->blocks, GEN_BB_WRITE);
 282                         } else {
 283                                 ret = bounce_buffer_start(&bbstate,
 284                                                 (void*)data->src,
 285                                                 data->blocksize *
 286                                                 data->blocks, GEN_BB_READ);
 287                         }
 288
 289                         if (ret)
 290                                 return ret;
 291
 292                         dwmci_prepare_data(host, data, cur_idmac,
 293                                            bbstate.bounce_buffer);
 294                 }
 295         }
 296
 297         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 298
 299         if (data)
 300                 flags = dwmci_set_transfer_mode(host, data);
 301
 302         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 303                 return -1;
 304
 305         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 306                 flags |= DWMCI_CMD_ABORT_STOP;
 307         else
 308                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 309
 310         if (cmd->resp_type & MMC_RSP_PRESENT) {
 311                 flags |= DWMCI_CMD_RESP_EXP;
 312                 if (cmd->resp_type & MMC_RSP_136)
 313                         flags |= DWMCI_CMD_RESP_LENGTH;
 314         }
 315
 316         if (cmd->resp_type & MMC_RSP_CRC)
 317                 flags |= DWMCI_CMD_CHECK_CRC;
 318
 319         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 320
 321         debug("Sending CMD%d\n",cmd->cmdidx);
 322
 323         dwmci_writel(host, DWMCI_CMD, flags);
 324
 325         for (i = 0; i < retry; i++) {
 326                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 327                 if (mask & DWMCI_INTMSK_CDONE) {
 328                         if (!data)
 329                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 330                         break;
 331                 }
 332         }
 333
 334         if (i == retry) {
 335                 debug("%s: Timeout.\n", __func__);
 336                 return -ETIMEDOUT;
 337         }
 338
 339         if (mask & DWMCI_INTMSK_RTO) {
 340                 /*
 341                  * Timeout here is not necessarily fatal. (e)MMC cards
 342                  * will splat here when they receive CMD55 as they do
 343                  * not support this command and that is exactly the way
 344                  * to tell them apart from SD cards. Thus, this output
 345                  * below shall be debug(). eMMC cards also do not favor
 346                  * CMD8, please keep that in mind.
 347                  */
 348                 debug("%s: Response Timeout.\n", __func__);
 349                 return -ETIMEDOUT;
 350         } else if (mask & DWMCI_INTMSK_RE) {
 351                 debug("%s: Response Error.\n", __func__);
 352                 return -EIO;
 353         } else if ((cmd->resp_type & MMC_RSP_CRC) &&
 354                    (mask & DWMCI_INTMSK_RCRC)) {
 355                 debug("%s: Response CRC Error.\n", __func__);
 356                 return -EIO;
 357         }
 358
 359
 360         if (cmd->resp_type & MMC_RSP_PRESENT) {
 361                 if (cmd->resp_type & MMC_RSP_136) {
 362                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 363                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 364                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 365                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 366                 } else {
 367                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 368                 }
 369         }
 370
 371         if (data) {
 372                 ret = dwmci_data_transfer(host, data);
 373
 374                 /* only dma mode need it */
 375                 if (!host->fifo_mode) {
 376                         if (data->flags == MMC_DATA_READ)
 377                                 mask = DWMCI_IDINTEN_RI;
 378                         else
 379                                 mask = DWMCI_IDINTEN_TI;
 380                         ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
 381                                                 mask, true, 1000, false);
 382                         if (ret)
 383                                 debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
 384                                       __func__, mask);
 385                         /* clear interrupts */
 386                         dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
 387
 388                         ctrl = dwmci_readl(host, DWMCI_CTRL);
 389                         ctrl &= ~(DWMCI_DMA_EN);
 390                         dwmci_writel(host, DWMCI_CTRL, ctrl);
 391                         bounce_buffer_stop(&bbstate);
 392                 }
 393         }
 394
 395         udelay(100);
 396
 397         return ret;
 398 }
 399
 400 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 401 {
 402         u32 div, status;
 403         int timeout = 10000;
 404         unsigned long sclk;
 405
 406         if ((freq == host->clock) || (freq == 0))
 407                 return 0;
 408         /*
 409          * If host->get_mmc_clk isn't defined,
 410          * then assume that host->bus_hz is source clock value.
 411          * host->bus_hz should be set by user.
 412          */
 413         if (host->get_mmc_clk)
 414                 sclk = host->get_mmc_clk(host, freq);
 415         else if (host->bus_hz)
 416                 sclk = host->bus_hz;
 417         else {
 418                 debug("%s: Didn't get source clock value.\n", __func__);
 419                 return -EINVAL;
 420         }
 421
 422         if (sclk == freq)
 423                 div = 0;        /* bypass mode */
 424         else
 425                 div = DIV_ROUND_UP(sclk, 2 * freq);
 426
 427         dwmci_writel(host, DWMCI_CLKENA, 0);
 428         dwmci_writel(host, DWMCI_CLKSRC, 0);
 429
 430         dwmci_writel(host, DWMCI_CLKDIV, div);
 431         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 432                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 433
 434         do {
 435                 status = dwmci_readl(host, DWMCI_CMD);
 436                 if (timeout-- < 0) {
 437                         debug("%s: Timeout!\n", __func__);
 438                         return -ETIMEDOUT;
 439                 }
 440         } while (status & DWMCI_CMD_START);
 441
 442         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 443                         DWMCI_CLKEN_LOW_PWR);
 444
 445         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 446                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 447
 448         timeout = 10000;
 449         do {
 450                 status = dwmci_readl(host, DWMCI_CMD);
 451                 if (timeout-- < 0) {
 452                         debug("%s: Timeout!\n", __func__);
 453                         return -ETIMEDOUT;
 454                 }
 455         } while (status & DWMCI_CMD_START);
 456
 457         host->clock = freq;
 458
 459         return 0;
 460 }
 461
 462 #ifdef CONFIG_DM_MMC
 463 static int dwmci_set_ios(struct udevice *dev)
 464 {
 465         struct mmc *mmc = mmc_get_mmc_dev(dev);
 466 #else
 467 static int dwmci_set_ios(struct mmc *mmc)
 468 {
 469 #endif
 470         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 471         u32 ctype, regs;
 472
 473         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 474
 475         dwmci_setup_bus(host, mmc->clock);
 476         switch (mmc->bus_width) {
 477         case 8:
 478                 ctype = DWMCI_CTYPE_8BIT;
 479                 break;
 480         case 4:
 481                 ctype = DWMCI_CTYPE_4BIT;
 482                 break;
 483         default:
 484                 ctype = DWMCI_CTYPE_1BIT;
 485                 break;
 486         }
 487
 488         dwmci_writel(host, DWMCI_CTYPE, ctype);
 489
 490         regs = dwmci_readl(host, DWMCI_UHS_REG);
 491         if (mmc->ddr_mode)
 492                 regs |= DWMCI_DDR_MODE;
 493         else
 494                 regs &= ~DWMCI_DDR_MODE;
 495
 496         dwmci_writel(host, DWMCI_UHS_REG, regs);
 497
 498         if (host->clksel)
 499                 host->clksel(host);
 500
 501 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 502         if (mmc->vqmmc_supply) {
 503                 int ret;
 504
 505                 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
 506                         regulator_set_value(mmc->vqmmc_supply, 1800000);
 507                 else
 508                         regulator_set_value(mmc->vqmmc_supply, 3300000);
 509
 510                 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 511                 if (ret)
 512                         return ret;
 513         }
 514 #endif
 515
 516         return 0;
 517 }
 518
 519 static int dwmci_init(struct mmc *mmc)
 520 {
 521         struct dwmci_host *host = mmc->priv;
 522
 523         if (host->board_init)
 524                 host->board_init(host);
 525
 526         dwmci_writel(host, DWMCI_PWREN, 1);
 527
 528         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 529                 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 530                 return -EIO;
 531         }
 532
 533         /* Enumerate at 400KHz */
 534         dwmci_setup_bus(host, mmc->cfg->f_min);
 535
 536         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 537         dwmci_writel(host, DWMCI_INTMASK, 0);
 538
 539         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 540
 541         dwmci_writel(host, DWMCI_IDINTEN, 0);
 542         dwmci_writel(host, DWMCI_BMOD, 1);
 543
 544         if (!host->fifoth_val) {
 545                 uint32_t fifo_size;
 546
 547                 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
 548                 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
 549                 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
 550                                 TX_WMARK(fifo_size / 2);
 551         }
 552         dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 553
 554         dwmci_writel(host, DWMCI_CLKENA, 0);
 555         dwmci_writel(host, DWMCI_CLKSRC, 0);
 556
 557         if (!host->fifo_mode)
 558                 dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
 559
 560         return 0;
 561 }
 562
 563 #ifdef CONFIG_DM_MMC
 564 int dwmci_probe(struct udevice *dev)
 565 {
 566         struct mmc *mmc = mmc_get_mmc_dev(dev);
 567
 568         return dwmci_init(mmc);
 569 }
 570
 571 const struct dm_mmc_ops dm_dwmci_ops = {
 572         .send_cmd       = dwmci_send_cmd,
 573         .set_ios        = dwmci_set_ios,
 574 };
 575
 576 #else
 577 static const struct mmc_ops dwmci_ops = {
 578         .send_cmd       = dwmci_send_cmd,
 579         .set_ios        = dwmci_set_ios,
 580         .init           = dwmci_init,
 581 };
 582 #endif
 583
 584 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
 585                 u32 max_clk, u32 min_clk)
 586 {
 587         cfg->name = host->name;
 588 #ifndef CONFIG_DM_MMC
 589         cfg->ops = &dwmci_ops;
 590 #endif
 591         cfg->f_min = min_clk;
 592         cfg->f_max = max_clk;
 593
 594         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 595
 596         cfg->host_caps = host->caps;
 597
 598         if (host->buswidth == 8) {
 599                 cfg->host_caps |= MMC_MODE_8BIT;
 600                 cfg->host_caps &= ~MMC_MODE_4BIT;
 601         } else {
 602                 cfg->host_caps |= MMC_MODE_4BIT;
 603                 cfg->host_caps &= ~MMC_MODE_8BIT;
 604         }
 605         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 606
 607         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 608 }
 609
 610 #ifdef CONFIG_BLK
 611 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 612 {
 613         return mmc_bind(dev, mmc, cfg);
 614 }
 615 #else
 616 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 617 {
 618         dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
 619
 620         host->mmc = mmc_create(&host->cfg, host);
 621         if (host->mmc == NULL)
 622                 return -1;
 623
 624         return 0;
 625 }
 626 #endif