drivers/mmc/ca_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Cortina Access
   4  * Arthur Li <arthur.li@cortina-access.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dwmmc.h>
   9 #include <fdtdec.h>
  10 #include <linux/libfdt.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <dm.h>
  14 #include <mapmem.h>
  15
  16 #define SD_CLK_SEL_MASK (0x3)
  17 #define SD_DLL_DEFAULT  (0x143000)
  18 #define SD_SCLK_MAX (200000000)
  19
  20 #define SD_CLK_SEL_200MHZ (0x2)
  21 #define SD_CLK_SEL_100MHZ (0x1)
  22 #define SD_CLK_SEL_50MHZ (0x0)
  23
  24 #define IO_DRV_SD_DS_OFFSET (16)
  25 #define IO_DRV_SD_DS_MASK   (0xff << IO_DRV_SD_DS_OFFSET)
  26
  27 #define MIN_FREQ (400000)
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 struct ca_mmc_plat {
  32         struct mmc_config cfg;
  33         struct mmc mmc;
  34 };
  35
  36 struct ca_dwmmc_priv_data {
  37         struct dwmci_host host;
  38         void __iomem *sd_dll_reg;
  39         void __iomem *io_drv_reg;
  40         u8 ds;
  41 };
  42
  43 static void ca_dwmci_clksel(struct dwmci_host *host)
  44 {
  45         struct ca_dwmmc_priv_data *priv = host->priv;
  46         u32 val = readl(priv->sd_dll_reg);
  47
  48         val &= ~SD_CLK_SEL_MASK;
  49         if (host->bus_hz >= 200000000)
  50                 val |= SD_CLK_SEL_200MHZ;
  51         else if (host->bus_hz >= 100000000)
  52                 val |= SD_CLK_SEL_100MHZ;
  53
  54         writel(val, priv->sd_dll_reg);
  55 }
  56
  57 static void ca_dwmci_board_init(struct dwmci_host *host)
  58 {
  59         struct ca_dwmmc_priv_data *priv = host->priv;
  60         u32 val = readl(priv->io_drv_reg);
  61
  62         writel(SD_DLL_DEFAULT, priv->sd_dll_reg);
  63
  64         val &= ~IO_DRV_SD_DS_MASK;
  65         if (priv && priv->ds)
  66                 val |= priv->ds << IO_DRV_SD_DS_OFFSET;
  67         writel(val, priv->io_drv_reg);
  68 }
  69
  70 unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq)
  71 {
  72         struct ca_dwmmc_priv_data *priv = host->priv;
  73         u8 sd_clk_sel = readl(priv->sd_dll_reg) & SD_CLK_SEL_MASK;
  74         u8 clk_div;
  75
  76         switch (sd_clk_sel) {
  77         case SD_CLK_SEL_50MHZ:
  78                 clk_div = 4;
  79                 break;
  80         case SD_CLK_SEL_100MHZ:
  81                 clk_div = 2;
  82                 break;
  83         default:
  84                 clk_div = 1;
  85         }
  86
  87         return SD_SCLK_MAX / clk_div / (host->div + 1);
  88 }
  89
  90 static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
  91 {
  92         struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
  93         struct dwmci_host *host = &priv->host;
  94         u32 tmp;
  95
  96         host->name = dev->name;
  97         host->dev_index = 0;
  98
  99         host->buswidth = dev_read_u32_default(dev, "bus-width", 1);
 100         host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000);
 101         priv->ds = dev_read_u32_default(dev, "io_ds", 0x33);
 102         host->fifo_mode = dev_read_bool(dev, "fifo-mode");
 103
 104         dev_read_u32(dev, "sd_dll_ctrl", &tmp);
 105         priv->sd_dll_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
 106         if (!priv->sd_dll_reg)
 107                 return -EINVAL;
 108
 109         dev_read_u32(dev, "io_drv_ctrl", &tmp);
 110         priv->io_drv_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
 111         if (!priv->io_drv_reg)
 112                 return -EINVAL;
 113
 114         host->ioaddr = dev_read_addr_ptr(dev);
 115         if (!host->ioaddr)
 116                 return -EINVAL;
 117
 118         host->priv = priv;
 119
 120         return 0;
 121 }
 122
 123 struct dm_mmc_ops ca_dwmci_dm_ops;
 124
 125 static int ca_dwmmc_probe(struct udevice *dev)
 126 {
 127         struct ca_mmc_plat *plat = dev_get_platdata(dev);
 128         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 129         struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
 130         struct dwmci_host *host = &priv->host;
 131
 132         memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
 133
 134         dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ);
 135         if (host->buswidth == 1)
 136                 (&plat->cfg)->host_caps &= ~(MMC_MODE_8BIT | MMC_MODE_4BIT);
 137
 138         host->mmc = &plat->mmc;
 139         host->mmc->priv = &priv->host;
 140         upriv->mmc = host->mmc;
 141         host->mmc->dev = dev;
 142         host->clksel = ca_dwmci_clksel;
 143         host->board_init = ca_dwmci_board_init;
 144         host->get_mmc_clk = ca_dwmci_get_mmc_clock;
 145
 146         return dwmci_probe(dev);
 147 }
 148
 149 static int ca_dwmmc_bind(struct udevice *dev)
 150 {
 151         struct ca_mmc_plat *plat = dev_get_platdata(dev);
 152
 153         return dwmci_bind(dev, &plat->mmc, &plat->cfg);
 154 }
 155
 156 static const struct udevice_id ca_dwmmc_ids[] = {
 157         { .compatible = "cortina,ca-mmc" },
 158         { }
 159 };
 160
 161 U_BOOT_DRIVER(ca_dwmmc_drv) = {
 162         .name           = "cortina_dwmmc",
 163         .id             = UCLASS_MMC,
 164         .of_match       = ca_dwmmc_ids,
 165         .ofdata_to_platdata = ca_dwmmc_ofdata_to_platdata,
 166         .bind           = ca_dwmmc_bind,
 167         .ops            = &ca_dwmci_dm_ops,
 168         .probe          = ca_dwmmc_probe,
 169         .priv_auto_alloc_size   = sizeof(struct ca_dwmmc_priv_data),
 170         .platdata_auto_alloc_size = sizeof(struct ca_mmc_plat),
 171 };