1 // SPDX-License-Identifier: GPL-2.0
3 * bcm2835 sdhost driver.
5 * The 2835 has two SD controllers: The Arasan sdhci controller
6 * (supported by the iproc driver) and a custom sdhost controller
7 * (supported by this driver).
9 * The sdhci controller supports both sdcard and sdio. The sdhost
10 * controller supports the sdcard only, but has better performance.
11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
12 * the sdhost controller allows to use the sdhci controller for wifi
15 * The configuration is done by devicetree via pin muxing. Both
16 * SD controller are available on the same pins (2 pin groups = pin 22
17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
18 * at the same time with different pin groups.
20 * This code was ported to U-Boot by
21 * Alexander Graf <agraf@suse.de>
22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
23 * Phil Elwell <phil@raspberrypi.org>
24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
26 * mmc-bcm2835.c by Gellert Weisz
27 * which is, in turn, based on
28 * sdhci-bcm2708.c by Broadcom
29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
30 * sdhci.c and sdhci-pci.c by Pierre Ossman
36 #include <asm/arch/msg.h>
37 #include <asm/arch/mbox.h>
38 #include <asm/unaligned.h>
39 #include <dm/device_compat.h>
40 #include <linux/bug.h>
41 #include <linux/compat.h>
42 #include <linux/delay.h>
44 #include <linux/iopoll.h>
45 #include <linux/sizes.h>
46 #include <mach/gpio.h>
47 #include <power/regulator.h>
49 #define msleep(a) udelay(a * 1000)
51 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
52 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
53 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
54 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
55 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
56 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
57 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
58 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
59 #define SDHSTS 0x20 /* SD host status - 11 R/W */
60 #define SDVDD 0x30 /* SD card power control - 1 R/W */
61 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
62 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
63 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
64 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
65 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
67 #define SDCMD_NEW_FLAG 0x8000
68 #define SDCMD_FAIL_FLAG 0x4000
69 #define SDCMD_BUSYWAIT 0x800
70 #define SDCMD_NO_RESPONSE 0x400
71 #define SDCMD_LONG_RESPONSE 0x200
72 #define SDCMD_WRITE_CMD 0x80
73 #define SDCMD_READ_CMD 0x40
74 #define SDCMD_CMD_MASK 0x3f
76 #define SDCDIV_MAX_CDIV 0x7ff
78 #define SDHSTS_BUSY_IRPT 0x400
79 #define SDHSTS_BLOCK_IRPT 0x200
80 #define SDHSTS_SDIO_IRPT 0x100
81 #define SDHSTS_REW_TIME_OUT 0x80
82 #define SDHSTS_CMD_TIME_OUT 0x40
83 #define SDHSTS_CRC16_ERROR 0x20
84 #define SDHSTS_CRC7_ERROR 0x10
85 #define SDHSTS_FIFO_ERROR 0x08
86 #define SDHSTS_DATA_FLAG 0x01
88 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
91 SDHSTS_REW_TIME_OUT | \
92 SDHSTS_CMD_TIME_OUT | \
93 SDHSTS_CRC16_ERROR | \
97 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
98 SDHSTS_CRC16_ERROR | \
99 SDHSTS_REW_TIME_OUT | \
102 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
103 SDHSTS_TRANSFER_ERROR_MASK)
105 #define SDHCFG_BUSY_IRPT_EN BIT(10)
106 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
107 #define SDHCFG_SDIO_IRPT_EN BIT(5)
108 #define SDHCFG_DATA_IRPT_EN BIT(4)
109 #define SDHCFG_SLOW_CARD BIT(3)
110 #define SDHCFG_WIDE_EXT_BUS BIT(2)
111 #define SDHCFG_WIDE_INT_BUS BIT(1)
112 #define SDHCFG_REL_CMD_LINE BIT(0)
114 #define SDVDD_POWER_OFF 0
115 #define SDVDD_POWER_ON 1
117 #define SDEDM_FORCE_DATA_MODE BIT(19)
118 #define SDEDM_CLOCK_PULSE BIT(20)
119 #define SDEDM_BYPASS BIT(21)
121 #define SDEDM_FIFO_FILL_SHIFT 4
122 #define SDEDM_FIFO_FILL_MASK 0x1f
123 static u32 edm_fifo_fill(u32 edm)
125 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
128 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
129 #define SDEDM_READ_THRESHOLD_SHIFT 14
130 #define SDEDM_THRESHOLD_MASK 0x1f
132 #define SDEDM_FSM_MASK 0xf
133 #define SDEDM_FSM_IDENTMODE 0x0
134 #define SDEDM_FSM_DATAMODE 0x1
135 #define SDEDM_FSM_READDATA 0x2
136 #define SDEDM_FSM_WRITEDATA 0x3
137 #define SDEDM_FSM_READWAIT 0x4
138 #define SDEDM_FSM_READCRC 0x5
139 #define SDEDM_FSM_WRITECRC 0x6
140 #define SDEDM_FSM_WRITEWAIT1 0x7
141 #define SDEDM_FSM_POWERDOWN 0x8
142 #define SDEDM_FSM_POWERUP 0x9
143 #define SDEDM_FSM_WRITESTART1 0xa
144 #define SDEDM_FSM_WRITESTART2 0xb
145 #define SDEDM_FSM_GENPULSES 0xc
146 #define SDEDM_FSM_WRITEWAIT2 0xd
147 #define SDEDM_FSM_STARTPOWDOWN 0xf
149 #define SDDATA_FIFO_WORDS 16
151 #define FIFO_READ_THRESHOLD 4
152 #define FIFO_WRITE_THRESHOLD 4
153 #define SDDATA_FIFO_PIO_BURST 8
155 #define SDHST_TIMEOUT_MAX_USEC 100000
157 struct bcm2835_plat {
158 struct mmc_config cfg;
162 struct bcm2835_host {
163 void __iomem *ioaddr;
166 int clock; /* Current clock speed */
167 unsigned int max_clk; /* Max possible freq */
168 unsigned int blocks; /* remaining PIO blocks */
170 u32 ns_per_fifo_word;
172 /* cached registers */
176 struct mmc_cmd *cmd; /* Current command */
177 struct mmc_data *data; /* Current data request */
178 bool use_busy:1; /* Wait for busy interrupt */
182 struct bcm2835_plat *plat;
185 static void bcm2835_dumpregs(struct bcm2835_host *host)
187 dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
188 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
189 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
190 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
191 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
192 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
193 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
194 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
195 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
196 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
197 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
198 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
199 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
200 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
201 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
202 dev_dbg(dev, "===========================================\n");
205 static void bcm2835_reset_internal(struct bcm2835_host *host)
209 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
210 writel(0, host->ioaddr + SDCMD);
211 writel(0, host->ioaddr + SDARG);
212 /* Set timeout to a big enough value so we don't hit it */
213 writel(0xf00000, host->ioaddr + SDTOUT);
214 writel(0, host->ioaddr + SDCDIV);
215 /* Clear status register */
216 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
217 writel(0, host->ioaddr + SDHCFG);
218 writel(0, host->ioaddr + SDHBCT);
219 writel(0, host->ioaddr + SDHBLC);
221 /* Limit fifo usage due to silicon bug */
222 temp = readl(host->ioaddr + SDEDM);
223 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
224 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
225 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
226 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
227 writel(temp, host->ioaddr + SDEDM);
228 /* Wait for FIFO threshold to populate */
230 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
231 /* Wait for all components to go through power on cycle */
234 writel(host->hcfg, host->ioaddr + SDHCFG);
235 writel(host->cdiv, host->ioaddr + SDCDIV);
238 static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
240 ulong tstart_ms = get_timer(0);
245 edm = readl(host->ioaddr + SDEDM);
246 fsm = edm & SDEDM_FSM_MASK;
248 if ((fsm == SDEDM_FSM_IDENTMODE) ||
249 (fsm == SDEDM_FSM_DATAMODE))
252 if ((fsm == SDEDM_FSM_READWAIT) ||
253 (fsm == SDEDM_FSM_WRITESTART1) ||
254 (fsm == SDEDM_FSM_READDATA)) {
255 writel(edm | SDEDM_FORCE_DATA_MODE,
256 host->ioaddr + SDEDM);
260 /* Error out after ~1s */
261 ulong tlapse_ms = get_timer(tstart_ms);
262 if ( tlapse_ms > 1000 /* ms */ ) {
265 "wait_transfer_complete - still waiting after %lu ms\n",
267 bcm2835_dumpregs(host);
275 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
277 struct mmc_data *data = host->data;
278 size_t blksize = data->blocksize;
283 if (blksize % sizeof(u32))
286 buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
289 data->dest += blksize;
291 data->src += blksize;
293 copy_words = blksize / sizeof(u32);
296 * Copy all contents from/to the FIFO as far as it reaches,
297 * then wait for it to fill/empty again and rewind.
300 int burst_words, words;
303 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
304 edm = readl(host->ioaddr + SDEDM);
306 words = edm_fifo_fill(edm);
308 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
310 if (words < burst_words) {
311 int fsm_state = (edm & SDEDM_FSM_MASK);
314 (fsm_state != SDEDM_FSM_READDATA &&
315 fsm_state != SDEDM_FSM_READWAIT &&
316 fsm_state != SDEDM_FSM_READCRC)) ||
318 (fsm_state != SDEDM_FSM_WRITEDATA &&
319 fsm_state != SDEDM_FSM_WRITEWAIT1 &&
320 fsm_state != SDEDM_FSM_WRITEWAIT2 &&
321 fsm_state != SDEDM_FSM_WRITECRC &&
322 fsm_state != SDEDM_FSM_WRITESTART1 &&
323 fsm_state != SDEDM_FSM_WRITESTART2))) {
324 hsts = readl(host->ioaddr + SDHSTS);
325 printf("fsm %x, hsts %08x\n", fsm_state, hsts);
326 if (hsts & SDHSTS_ERROR_MASK)
331 } else if (words > copy_words) {
337 /* Copy current chunk to/from the FIFO */
340 *(buf++) = readl(host->ioaddr + SDDATA);
342 writel(*(buf++), host->ioaddr + SDDATA);
350 static int bcm2835_transfer_pio(struct bcm2835_host *host)
356 is_read = (host->data->flags & MMC_DATA_READ) != 0;
357 ret = bcm2835_transfer_block_pio(host, is_read);
361 sdhsts = readl(host->ioaddr + SDHSTS);
362 if (sdhsts & (SDHSTS_CRC16_ERROR |
364 SDHSTS_FIFO_ERROR)) {
365 printf("%s transfer error - HSTS %08x\n",
366 is_read ? "read" : "write", sdhsts);
368 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
369 SDHSTS_REW_TIME_OUT))) {
370 printf("%s timeout error - HSTS %08x\n",
371 is_read ? "read" : "write", sdhsts);
378 static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
379 struct mmc_data *data)
388 host->blocks = data->blocks;
390 writel(data->blocksize, host->ioaddr + SDHBCT);
391 writel(data->blocks, host->ioaddr + SDHBLC);
394 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
398 int timeout_us = SDHST_TIMEOUT_MAX_USEC;
400 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
401 !(value & SDCMD_NEW_FLAG), timeout_us);
402 if (ret == -ETIMEDOUT)
403 printf("%s: timeout (%d us)\n", __func__, timeout_us);
408 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
409 struct mmc_data *data)
415 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
416 printf("unsupported response type!\n");
420 sdcmd = bcm2835_read_wait_sdcmd(host);
421 if (sdcmd & SDCMD_NEW_FLAG) {
422 printf("previous command never completed.\n");
423 bcm2835_dumpregs(host);
429 /* Clear any error flags */
430 sdhsts = readl(host->ioaddr + SDHSTS);
431 if (sdhsts & SDHSTS_ERROR_MASK)
432 writel(sdhsts, host->ioaddr + SDHSTS);
434 bcm2835_prepare_data(host, cmd, data);
436 writel(cmd->cmdarg, host->ioaddr + SDARG);
438 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
440 host->use_busy = false;
441 if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
442 sdcmd |= SDCMD_NO_RESPONSE;
444 if (cmd->resp_type & MMC_RSP_136)
445 sdcmd |= SDCMD_LONG_RESPONSE;
446 if (cmd->resp_type & MMC_RSP_BUSY) {
447 sdcmd |= SDCMD_BUSYWAIT;
448 host->use_busy = true;
453 if (data->flags & MMC_DATA_WRITE)
454 sdcmd |= SDCMD_WRITE_CMD;
455 if (data->flags & MMC_DATA_READ)
456 sdcmd |= SDCMD_READ_CMD;
459 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
464 static int bcm2835_finish_command(struct bcm2835_host *host)
466 struct mmc_cmd *cmd = host->cmd;
470 sdcmd = bcm2835_read_wait_sdcmd(host);
472 /* Check for errors */
473 if (sdcmd & SDCMD_NEW_FLAG) {
474 printf("command never completed.\n");
475 bcm2835_dumpregs(host);
477 } else if (sdcmd & SDCMD_FAIL_FLAG) {
478 u32 sdhsts = readl(host->ioaddr + SDHSTS);
480 /* Clear the errors */
481 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
483 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
484 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
485 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
488 printf("unexpected command %d error\n",
490 bcm2835_dumpregs(host);
498 if (cmd->resp_type & MMC_RSP_PRESENT) {
499 if (cmd->resp_type & MMC_RSP_136) {
502 for (i = 0; i < 4; i++) {
503 cmd->response[3 - i] =
504 readl(host->ioaddr + SDRSP0 + i * 4);
507 cmd->response[0] = readl(host->ioaddr + SDRSP0);
511 /* Processed actual command. */
517 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
521 if (!(intmask & SDHSTS_ERROR_MASK))
527 printf("sdhost_busy_irq: intmask %08x\n", intmask);
528 if (intmask & SDHSTS_CRC7_ERROR) {
530 } else if (intmask & (SDHSTS_CRC16_ERROR |
531 SDHSTS_FIFO_ERROR)) {
533 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
536 bcm2835_dumpregs(host);
540 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
546 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
548 if (intmask & SDHSTS_REW_TIME_OUT)
552 printf("%s:%d %d\n", __func__, __LINE__, ret);
557 static int bcm2835_transmit(struct bcm2835_host *host)
559 u32 intmask = readl(host->ioaddr + SDHSTS);
562 /* Check for errors */
563 ret = bcm2835_check_data_error(host, intmask);
567 ret = bcm2835_check_cmd_error(host, intmask);
571 /* Handle wait for busy end */
572 if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
573 writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
574 host->use_busy = false;
575 bcm2835_finish_command(host);
578 /* Handle PIO data transfer */
580 ret = bcm2835_transfer_pio(host);
584 if (host->blocks == 0) {
585 /* Wait for command to complete for real */
586 ret = bcm2835_wait_transfer_complete(host);
589 /* Transfer complete */
597 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
601 /* The SDCDIV register has 11 bits, and holds (div - 2). But
602 * in data mode the max is 50MHz wihout a minimum, and only
603 * the bottom 3 bits are used. Since the switch over is
604 * automatic (unless we have marked the card as slow...),
605 * chosen values have to make sense in both modes. Ident mode
606 * must be 100-400KHz, so can range check the requested
607 * clock. CMD15 must be used to return to data mode, so this
610 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
611 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
613 * 623->400KHz/27.8MHz
614 * reset value (507)->491159/50MHz
616 * BUT, the 3-bit clock divisor in data mode is too small if
617 * the core clock is higher than 250MHz, so instead use the
618 * SLOW_CARD configuration bit to force the use of the ident
619 * clock divisor at all times.
622 if (clock < 100000) {
623 /* Can't stop the clock, but make it as slow as possible
626 host->cdiv = SDCDIV_MAX_CDIV;
627 writel(host->cdiv, host->ioaddr + SDCDIV);
631 div = host->max_clk / clock;
634 if ((host->max_clk / div) > clock)
638 if (div > SDCDIV_MAX_CDIV)
639 div = SDCDIV_MAX_CDIV;
641 clock = host->max_clk / (div + 2);
642 host->mmc->clock = clock;
644 /* Calibrate some delays */
646 host->ns_per_fifo_word = (1000000000 / clock) *
647 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
650 writel(host->cdiv, host->ioaddr + SDCDIV);
652 /* Set the timeout to 500ms */
653 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
656 static inline int is_power_of_2(u64 x)
658 return !(x & (x - 1));
661 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
662 struct mmc_data *data)
664 struct bcm2835_host *host = dev_get_priv(dev);
668 if (data && !is_power_of_2(data->blocksize)) {
669 printf("unsupported block size (%d bytes)\n", data->blocksize);
675 edm = readl(host->ioaddr + SDEDM);
676 fsm = edm & SDEDM_FSM_MASK;
678 if ((fsm != SDEDM_FSM_IDENTMODE) &&
679 (fsm != SDEDM_FSM_DATAMODE) &&
680 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
681 printf("previous command (%d) not complete (EDM %08x)\n",
682 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
683 bcm2835_dumpregs(host);
692 ret = bcm2835_send_command(host, cmd, data);
693 if (!ret && !host->use_busy)
694 ret = bcm2835_finish_command(host);
697 /* Wait for completion of busy signal or data transfer */
698 while (host->use_busy || host->data) {
699 ret = bcm2835_transmit(host);
707 static int bcm2835_set_ios(struct udevice *dev)
709 struct bcm2835_host *host = dev_get_priv(dev);
710 struct mmc *mmc = mmc_get_mmc_dev(dev);
712 if (!mmc->clock || mmc->clock != host->clock) {
713 bcm2835_set_clock(host, mmc->clock);
714 host->clock = mmc->clock;
718 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
719 if (mmc->bus_width == 4)
720 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
722 host->hcfg |= SDHCFG_WIDE_INT_BUS;
724 /* Disable clever clock switching, to cope with fast core clocks */
725 host->hcfg |= SDHCFG_SLOW_CARD;
727 writel(host->hcfg, host->ioaddr + SDHCFG);
732 static void bcm2835_add_host(struct bcm2835_host *host)
734 struct mmc_config *cfg = &host->plat->cfg;
736 cfg->f_max = host->max_clk;
737 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
740 dev_dbg(dev, "f_max %d, f_min %d\n",
741 cfg->f_max, cfg->f_min);
743 /* host controller capabilities */
744 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
746 /* report supported voltage ranges */
747 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
749 /* Set interrupt enables */
750 host->hcfg = SDHCFG_BUSY_IRPT_EN;
752 bcm2835_reset_internal(host);
755 static int bcm2835_probe(struct udevice *dev)
757 struct bcm2835_plat *plat = dev_get_platdata(dev);
758 struct bcm2835_host *host = dev_get_priv(dev);
759 struct mmc *mmc = mmc_get_mmc_dev(dev);
760 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
765 upriv->mmc = &plat->mmc;
766 plat->cfg.name = dev->name;
768 host->phys_addr = devfdt_get_addr(dev);
769 if (host->phys_addr == FDT_ADDR_T_NONE)
772 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
776 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
778 bcm2835_add_host(host);
780 dev_dbg(dev, "%s -> OK\n", __func__);
785 static const struct udevice_id bcm2835_match[] = {
786 { .compatible = "brcm,bcm2835-sdhost" },
790 static const struct dm_mmc_ops bcm2835_ops = {
791 .send_cmd = bcm2835_send_cmd,
792 .set_ios = bcm2835_set_ios,
795 static int bcm2835_bind(struct udevice *dev)
797 struct bcm2835_plat *plat = dev_get_platdata(dev);
799 return mmc_bind(dev, &plat->mmc, &plat->cfg);
802 U_BOOT_DRIVER(bcm2835_sdhost) = {
803 .name = "bcm2835-sdhost",
805 .of_match = bcm2835_match,
806 .bind = bcm2835_bind,
807 .probe = bcm2835_probe,
808 .priv_auto_alloc_size = sizeof(struct bcm2835_host),
809 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),