drivers/misc/mxc_ocotp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 ADVANSEE
   4  * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
   5  *
   6  * Based on Dirk Behme's
   7  * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
   8  * which is based on Freescale's
   9  * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
  10  * which is:
  11  * Copyright (C) 2011 Freescale Semiconductor, Inc.
  12  */
  13
  14 #include <common.h>
  15 #include <fuse.h>
  16 #include <linux/errno.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/imx-regs.h>
  20 #include <asm/mach-imx/sys_proto.h>
  21
  22 #define BO_CTRL_WR_UNLOCK               16
  23 #define BM_CTRL_WR_UNLOCK               0xffff0000
  24 #define BV_CTRL_WR_UNLOCK_KEY           0x3e77
  25 #define BM_CTRL_ERROR                   0x00000200
  26 #define BM_CTRL_BUSY                    0x00000100
  27 #define BO_CTRL_ADDR                    0
  28 #ifdef CONFIG_MX7
  29 #define BM_CTRL_ADDR                    0x0000000f
  30 #define BM_CTRL_RELOAD                  0x00000400
  31 #elif defined(CONFIG_MX7ULP)
  32 #define BM_CTRL_ADDR                    0x000000FF
  33 #define BM_CTRL_RELOAD                  0x00000400
  34 #define BM_OUT_STATUS_DED                               0x00000400
  35 #define BM_OUT_STATUS_LOCKED                    0x00000800
  36 #define BM_OUT_STATUS_PROGFAIL                  0x00001000
  37 #elif defined(CONFIG_IMX8M)
  38 #ifdef CONFIG_IMX8MP
  39 #undef BM_CTRL_ADDR
  40 #undef BM_CTRL_ERROR
  41 #undef BM_CTRL_BUSY
  42 #define BM_CTRL_ADDR                    0x000001ff
  43 #define BM_CTRL_ERROR                   0x00000400
  44 #define BM_CTRL_BUSY                    0x00000200
  45 #else
  46 #define BM_CTRL_ADDR                    0x000000ff
  47 #endif
  48 #else
  49 #define BM_CTRL_ADDR                    0x0000007f
  50 #endif
  51
  52 #ifdef CONFIG_MX7
  53 #define BO_TIMING_FSOURCE               12
  54 #define BM_TIMING_FSOURCE               0x0007f000
  55 #define BV_TIMING_FSOURCE_NS            1001
  56 #define BO_TIMING_PROG                  0
  57 #define BM_TIMING_PROG                  0x00000fff
  58 #define BV_TIMING_PROG_US               10
  59 #else
  60 #define BO_TIMING_STROBE_READ           16
  61 #define BM_TIMING_STROBE_READ           0x003f0000
  62 #define BV_TIMING_STROBE_READ_NS        37
  63 #define BO_TIMING_RELAX                 12
  64 #define BM_TIMING_RELAX                 0x0000f000
  65 #define BV_TIMING_RELAX_NS              17
  66 #define BO_TIMING_STROBE_PROG           0
  67 #define BM_TIMING_STROBE_PROG           0x00000fff
  68 #define BV_TIMING_STROBE_PROG_US        10
  69 #endif
  70
  71 #define BM_READ_CTRL_READ_FUSE          0x00000001
  72
  73 #define BF(value, field)                (((value) << BO_##field) & BM_##field)
  74
  75 #define WRITE_POSTAMBLE_US              2
  76
  77 #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
  78 #define FUSE_BANK_SIZE  0x80
  79 #ifdef CONFIG_MX6SL
  80 #define FUSE_BANKS      8
  81 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
  82 #define FUSE_BANKS      9
  83 #else
  84 #define FUSE_BANKS      16
  85 #endif
  86 #elif defined CONFIG_MX7
  87 #define FUSE_BANK_SIZE  0x40
  88 #define FUSE_BANKS      16
  89 #elif defined(CONFIG_MX7ULP)
  90 #define FUSE_BANK_SIZE  0x80
  91 #define FUSE_BANKS      31
  92 #elif defined(CONFIG_IMX8M)
  93 #define FUSE_BANK_SIZE  0x40
  94 #ifdef CONFIG_IMX8MP
  95 #define FUSE_BANKS      96
  96 #else
  97 #define FUSE_BANKS      64
  98 #endif
  99 #else
 100 #error "Unsupported architecture\n"
 101 #endif
 102
 103 #if defined(CONFIG_MX6)
 104
 105 /*
 106  * There is a hole in shadow registers address map of size 0x100
 107  * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
 108  * iMX6UL, i.MX6ULL and i.MX6SLL.
 109  * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
 110  * we should account for this hole in address space.
 111  *
 112  * Similar hole exists between bank 14 and bank 15 of size
 113  * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
 114  * Note: iMX6SL has only 0-7 banks and there is no hole.
 115  * Note: iMX6UL doesn't have this one.
 116  *
 117  * This function is to covert user input to physical bank index.
 118  * Only needed when read fuse, because we use register offset, so
 119  * need to calculate real register offset.
 120  * When write, no need to consider hole, always use the bank/word
 121  * index from fuse map.
 122  */
 123 u32 fuse_bank_physical(int index)
 124 {
 125         u32 phy_index;
 126
 127         if (is_mx6sl() || is_mx7ulp()) {
 128                 phy_index = index;
 129         } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
 130                 if ((is_mx6ull() || is_mx6sll()) && index == 8)
 131                         index = 7;
 132
 133                 if (index >= 6)
 134                         phy_index = fuse_bank_physical(5) + (index - 6) + 3;
 135                 else
 136                         phy_index = index;
 137         } else {
 138                 if (index >= 15)
 139                         phy_index = fuse_bank_physical(14) + (index - 15) + 2;
 140                 else if (index >= 6)
 141                         phy_index = fuse_bank_physical(5) + (index - 6) + 3;
 142                 else
 143                         phy_index = index;
 144         }
 145         return phy_index;
 146 }
 147
 148 u32 fuse_word_physical(u32 bank, u32 word_index)
 149 {
 150         if (is_mx6ull() || is_mx6sll()) {
 151                 if (bank == 8)
 152                         word_index = word_index + 4;
 153         }
 154
 155         return word_index;
 156 }
 157 #else
 158 u32 fuse_bank_physical(int index)
 159 {
 160         return index;
 161 }
 162
 163 u32 fuse_word_physical(u32 bank, u32 word_index)
 164 {
 165         return word_index;
 166 }
 167
 168 #endif
 169
 170 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
 171 {
 172         while (readl(&regs->ctrl) & BM_CTRL_BUSY)
 173                 udelay(delay_us);
 174 }
 175
 176 static void clear_error(struct ocotp_regs *regs)
 177 {
 178         writel(BM_CTRL_ERROR, &regs->ctrl_clr);
 179 }
 180
 181 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
 182                                 int assert, const char *caller)
 183 {
 184         *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 185
 186         if (bank >= FUSE_BANKS ||
 187             word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
 188             !assert) {
 189                 printf("mxc_ocotp %s(): Invalid argument\n", caller);
 190                 return -EINVAL;
 191         }
 192
 193         if (is_mx6ull() || is_mx6sll()) {
 194                 if ((bank == 7 || bank == 8) &&
 195                     word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
 196                         printf("mxc_ocotp %s(): Invalid argument\n", caller);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         enable_ocotp_clk(1);
 202
 203         wait_busy(*regs, 1);
 204         clear_error(*regs);
 205
 206         return 0;
 207 }
 208
 209 static int finish_access(struct ocotp_regs *regs, const char *caller)
 210 {
 211         u32 err;
 212
 213         err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
 214         clear_error(regs);
 215
 216 #ifdef CONFIG_MX7ULP
 217         /* Need to power down the OTP memory */
 218         writel(1, &regs->pdn);
 219 #endif
 220         if (err) {
 221                 printf("mxc_ocotp %s(): Access protect error\n", caller);
 222                 return -EIO;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
 229                         const char *caller)
 230 {
 231         return prepare_access(regs, bank, word, val != NULL, caller);
 232 }
 233
 234 int fuse_read(u32 bank, u32 word, u32 *val)
 235 {
 236         struct ocotp_regs *regs;
 237         int ret;
 238         u32 phy_bank;
 239         u32 phy_word;
 240
 241         ret = prepare_read(&regs, bank, word, val, __func__);
 242         if (ret)
 243                 return ret;
 244
 245         phy_bank = fuse_bank_physical(bank);
 246         phy_word = fuse_word_physical(bank, word);
 247
 248         *val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 249
 250 #ifdef CONFIG_MX7ULP
 251         if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
 252                 writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
 253                 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
 254                 return -EIO;
 255         }
 256 #endif
 257         return finish_access(regs, __func__);
 258 }
 259
 260 #ifdef CONFIG_MX7
 261 static void set_timing(struct ocotp_regs *regs)
 262 {
 263         u32 ipg_clk;
 264         u32 fsource, prog;
 265         u32 timing;
 266
 267         ipg_clk = mxc_get_clock(MXC_IPG_CLK);
 268
 269         fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
 270                         +       1000000) + 1;
 271         prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
 272
 273         timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
 274
 275         clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
 276                         timing);
 277 }
 278 #elif defined(CONFIG_MX7ULP)
 279 static void set_timing(struct ocotp_regs *regs)
 280 {
 281         /* No timing set for MX7ULP */
 282 }
 283
 284 #else
 285 static void set_timing(struct ocotp_regs *regs)
 286 {
 287         u32 ipg_clk;
 288         u32 relax, strobe_read, strobe_prog;
 289         u32 timing;
 290
 291         ipg_clk = mxc_get_clock(MXC_IPG_CLK);
 292
 293         relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
 294         strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
 295                                         1000000000) + 2 * (relax + 1) - 1;
 296         strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
 297                                                 1000000) + 2 * (relax + 1) - 1;
 298
 299         timing = BF(strobe_read, TIMING_STROBE_READ) |
 300                         BF(relax, TIMING_RELAX) |
 301                         BF(strobe_prog, TIMING_STROBE_PROG);
 302
 303         clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
 304                         BM_TIMING_STROBE_PROG, timing);
 305 }
 306 #endif
 307
 308 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
 309                                 int write)
 310 {
 311         u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 312 #ifdef CONFIG_MX7
 313         u32 addr = bank;
 314 #elif defined CONFIG_IMX8M
 315         u32 addr = bank << 2 | word;
 316 #else
 317         u32 addr;
 318         /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
 319         if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
 320                 bank = bank - 1;
 321                 word += 4;
 322         }
 323         addr = bank << 3 | word;
 324 #endif
 325
 326         set_timing(regs);
 327         clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
 328                         BF(wr_unlock, CTRL_WR_UNLOCK) |
 329                         BF(addr, CTRL_ADDR));
 330 }
 331
 332 int fuse_sense(u32 bank, u32 word, u32 *val)
 333 {
 334         struct ocotp_regs *regs;
 335         int ret;
 336
 337         if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
 338                 printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
 339                 return -EPERM;
 340         }
 341
 342         ret = prepare_read(&regs, bank, word, val, __func__);
 343         if (ret)
 344                 return ret;
 345
 346         setup_direct_access(regs, bank, word, false);
 347         writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
 348         wait_busy(regs, 1);
 349 #ifdef CONFIG_MX7
 350         *val = readl((&regs->read_fuse_data0) + (word << 2));
 351 #else
 352         *val = readl(&regs->read_fuse_data);
 353 #endif
 354
 355 #ifdef CONFIG_MX7ULP
 356         if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
 357                 writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
 358                 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
 359                 return -EIO;
 360         }
 361 #endif
 362
 363         return finish_access(regs, __func__);
 364 }
 365
 366 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
 367                                 const char *caller)
 368 {
 369 #ifdef CONFIG_MX7ULP
 370         u32 val;
 371         int ret;
 372
 373         /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
 374         if (bank != 0 && bank != 1) {
 375                 if ((soc_rev() < CHIP_REV_2_0) ||
 376                     ((soc_rev() >= CHIP_REV_2_0) &&
 377                     bank != 9 && bank != 10 && bank != 28)) {
 378                         ret = fuse_sense(bank, word, &val);
 379                         if (ret)
 380                                 return ret;
 381
 382                         if (val != 0) {
 383                                 printf("mxc_ocotp: The word has been programmed, no more write\n");
 384                                 return -EPERM;
 385                         }
 386                 }
 387         }
 388 #endif
 389
 390         return prepare_access(regs, bank, word, true, caller);
 391 }
 392
 393 int fuse_prog(u32 bank, u32 word, u32 val)
 394 {
 395         struct ocotp_regs *regs;
 396         int ret;
 397
 398         ret = prepare_write(&regs, bank, word, __func__);
 399         if (ret)
 400                 return ret;
 401
 402         setup_direct_access(regs, bank, word, true);
 403 #ifdef CONFIG_MX7
 404         switch (word) {
 405         case 0:
 406                 writel(0, &regs->data1);
 407                 writel(0, &regs->data2);
 408                 writel(0, &regs->data3);
 409                 writel(val, &regs->data0);
 410                 break;
 411         case 1:
 412                 writel(val, &regs->data1);
 413                 writel(0, &regs->data2);
 414                 writel(0, &regs->data3);
 415                 writel(0, &regs->data0);
 416                 break;
 417         case 2:
 418                 writel(0, &regs->data1);
 419                 writel(val, &regs->data2);
 420                 writel(0, &regs->data3);
 421                 writel(0, &regs->data0);
 422                 break;
 423         case 3:
 424                 writel(0, &regs->data1);
 425                 writel(0, &regs->data2);
 426                 writel(val, &regs->data3);
 427                 writel(0, &regs->data0);
 428                 break;
 429         }
 430         wait_busy(regs, BV_TIMING_PROG_US);
 431 #else
 432         writel(val, &regs->data);
 433         wait_busy(regs, BV_TIMING_STROBE_PROG_US);
 434 #endif
 435         udelay(WRITE_POSTAMBLE_US);
 436
 437 #ifdef CONFIG_MX7ULP
 438         if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
 439                 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
 440                 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
 441                 return -EIO;
 442         }
 443 #endif
 444
 445         return finish_access(regs, __func__);
 446 }
 447
 448 int fuse_override(u32 bank, u32 word, u32 val)
 449 {
 450         struct ocotp_regs *regs;
 451         int ret;
 452         u32 phy_bank;
 453         u32 phy_word;
 454
 455         ret = prepare_write(&regs, bank, word, __func__);
 456         if (ret)
 457                 return ret;
 458
 459         phy_bank = fuse_bank_physical(bank);
 460         phy_word = fuse_word_physical(bank, word);
 461
 462         writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 463
 464 #ifdef CONFIG_MX7ULP
 465         if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
 466                 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
 467                 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
 468                 return -EIO;
 469         }
 470 #endif
 471
 472         return finish_access(regs, __func__);
 473 }