drivers/i2c/tegra_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
   4  * Copyright (c) 2010-2011 NVIDIA Corporation
   5  *  NVIDIA Corporation <www.nvidia.com>
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <i2c.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14 #include <clk.h>
  15 #include <reset.h>
  16 #ifndef CONFIG_TEGRA186
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/funcmux.h>
  19 #endif
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch-tegra/tegra_i2c.h>
  22 #include <linux/err.h>
  23
  24 enum i2c_type {
  25         TYPE_114,
  26         TYPE_STD,
  27         TYPE_DVC,
  28 };
  29
  30 /* Information about i2c controller */
  31 struct i2c_bus {
  32         int                     id;
  33         struct reset_ctl        reset_ctl;
  34         struct clk              clk;
  35         int                     speed;
  36         int                     pinmux_config;
  37         struct i2c_control      *control;
  38         struct i2c_ctlr         *regs;
  39         enum i2c_type           type;
  40         int                     inited; /* bus is inited */
  41 };
  42
  43 static void set_packet_mode(struct i2c_bus *i2c_bus)
  44 {
  45         u32 config;
  46
  47         config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
  48
  49         if (i2c_bus->type == TYPE_DVC) {
  50                 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
  51
  52                 writel(config, &dvc->cnfg);
  53         } else {
  54                 writel(config, &i2c_bus->regs->cnfg);
  55                 /*
  56                  * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
  57                  * issues, i.e., some slaves may be wrongly detected.
  58                  */
  59                 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
  60         }
  61 }
  62
  63 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
  64 {
  65         /* Reset I2C controller. */
  66         reset_assert(&i2c_bus->reset_ctl);
  67         udelay(1);
  68         reset_deassert(&i2c_bus->reset_ctl);
  69         udelay(1);
  70
  71         /* re-program config register to packet mode */
  72         set_packet_mode(i2c_bus);
  73 }
  74
  75 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
  76 {
  77         int ret;
  78
  79         ret = reset_assert(&i2c_bus->reset_ctl);
  80         if (ret)
  81                 return ret;
  82         ret = clk_enable(&i2c_bus->clk);
  83         if (ret)
  84                 return ret;
  85         ret = clk_set_rate(&i2c_bus->clk, rate);
  86         if (IS_ERR_VALUE(ret))
  87                 return ret;
  88         ret = reset_deassert(&i2c_bus->reset_ctl);
  89         if (ret)
  90                 return ret;
  91
  92         return 0;
  93 }
  94
  95 static void i2c_init_controller(struct i2c_bus *i2c_bus)
  96 {
  97         if (!i2c_bus->speed)
  98                 return;
  99         debug("%s: speed=%d\n", __func__, i2c_bus->speed);
 100         /*
 101          * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
 102          * here, in section 23.3.1, but in fact we seem to need a factor of
 103          * 16 to get the right frequency.
 104          */
 105         i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
 106
 107         if (i2c_bus->type == TYPE_114) {
 108                 /*
 109                  * T114 I2C went to a single clock source for standard/fast and
 110                  * HS clock speeds. The new clock rate setting calculation is:
 111                  *  SCL = CLK_SOURCE.I2C /
 112                  *   (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
 113                  *   I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
 114                  *
 115                  * NOTE: We do this here, after the initial clock/pll start,
 116                  * because if we read the clk_div reg before the controller
 117                  * is running, we hang, and we need it for the new calc.
 118                  */
 119                 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
 120                 unsigned rate = CLK_MULT_STD_FAST_MODE *
 121                                 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
 122                 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
 123                         clk_div_stdfst_mode);
 124
 125                 i2c_init_clock(i2c_bus, rate);
 126         }
 127
 128         /* Reset I2C controller. */
 129         i2c_reset_controller(i2c_bus);
 130
 131         /* Configure I2C controller. */
 132         if (i2c_bus->type == TYPE_DVC) {        /* only for DVC I2C */
 133                 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
 134
 135                 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
 136         }
 137
 138 #ifndef CONFIG_TEGRA186
 139         funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
 140 #endif
 141 }
 142
 143 static void send_packet_headers(
 144         struct i2c_bus *i2c_bus,
 145         struct i2c_trans_info *trans,
 146         u32 packet_id,
 147         bool end_with_repeated_start)
 148 {
 149         u32 data;
 150
 151         /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
 152         data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
 153         data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
 154         data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
 155         writel(data, &i2c_bus->control->tx_fifo);
 156         debug("pkt header 1 sent (0x%x)\n", data);
 157
 158         /* prepare header2 */
 159         data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
 160         writel(data, &i2c_bus->control->tx_fifo);
 161         debug("pkt header 2 sent (0x%x)\n", data);
 162
 163         /* prepare IO specific header: configure the slave address */
 164         data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
 165
 166         /* Enable Read if it is not a write transaction */
 167         if (!(trans->flags & I2C_IS_WRITE))
 168                 data |= PKT_HDR3_READ_MODE_MASK;
 169         if (end_with_repeated_start)
 170                 data |= PKT_HDR3_REPEAT_START_MASK;
 171
 172         /* Write I2C specific header */
 173         writel(data, &i2c_bus->control->tx_fifo);
 174         debug("pkt header 3 sent (0x%x)\n", data);
 175 }
 176
 177 static int wait_for_tx_fifo_empty(struct i2c_control *control)
 178 {
 179         u32 count;
 180         int timeout_us = I2C_TIMEOUT_USEC;
 181
 182         while (timeout_us >= 0) {
 183                 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
 184                                 >> TX_FIFO_EMPTY_CNT_SHIFT;
 185                 if (count == I2C_FIFO_DEPTH)
 186                         return 1;
 187                 udelay(10);
 188                 timeout_us -= 10;
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
 195 {
 196         u32 count;
 197         int timeout_us = I2C_TIMEOUT_USEC;
 198
 199         while (timeout_us >= 0) {
 200                 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
 201                                 >> TX_FIFO_FULL_CNT_SHIFT;
 202                 if (count)
 203                         return 1;
 204                 udelay(10);
 205                 timeout_us -= 10;
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int wait_for_transfer_complete(struct i2c_control *control)
 212 {
 213         int int_status;
 214         int timeout_us = I2C_TIMEOUT_USEC;
 215
 216         while (timeout_us >= 0) {
 217                 int_status = readl(&control->int_status);
 218                 if (int_status & I2C_INT_NO_ACK_MASK)
 219                         return -int_status;
 220                 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
 221                         return -int_status;
 222                 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
 223                         return 0;
 224
 225                 udelay(10);
 226                 timeout_us -= 10;
 227         }
 228
 229         return -1;
 230 }
 231
 232 static int send_recv_packets(struct i2c_bus *i2c_bus,
 233                              struct i2c_trans_info *trans)
 234 {
 235         struct i2c_control *control = i2c_bus->control;
 236         u32 int_status;
 237         u32 words;
 238         u8 *dptr;
 239         u32 local;
 240         uchar last_bytes;
 241         int error = 0;
 242         int is_write = trans->flags & I2C_IS_WRITE;
 243
 244         /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
 245         int_status = readl(&control->int_status);
 246         writel(int_status, &control->int_status);
 247
 248         send_packet_headers(i2c_bus, trans, 1,
 249                             trans->flags & I2C_USE_REPEATED_START);
 250
 251         words = DIV_ROUND_UP(trans->num_bytes, 4);
 252         last_bytes = trans->num_bytes & 3;
 253         dptr = trans->buf;
 254
 255         while (words) {
 256                 u32 *wptr = (u32 *)dptr;
 257
 258                 if (is_write) {
 259                         /* deal with word alignment */
 260                         if ((words == 1) && last_bytes) {
 261                                 local = 0;
 262                                 memcpy(&local, dptr, last_bytes);
 263                         } else if ((unsigned long)dptr & 3) {
 264                                 memcpy(&local, dptr, sizeof(u32));
 265                         } else {
 266                                 local = *wptr;
 267                         }
 268                         writel(local, &control->tx_fifo);
 269                         debug("pkt data sent (0x%x)\n", local);
 270                         if (!wait_for_tx_fifo_empty(control)) {
 271                                 error = -1;
 272                                 goto exit;
 273                         }
 274                 } else {
 275                         if (!wait_for_rx_fifo_notempty(control)) {
 276                                 error = -1;
 277                                 goto exit;
 278                         }
 279                         /*
 280                          * for the last word, we read into our local buffer,
 281                          * in case that caller did not provide enough buffer.
 282                          */
 283                         local = readl(&control->rx_fifo);
 284                         if ((words == 1) && last_bytes)
 285                                 memcpy(dptr, (char *)&local, last_bytes);
 286                         else if ((unsigned long)dptr & 3)
 287                                 memcpy(dptr, &local, sizeof(u32));
 288                         else
 289                                 *wptr = local;
 290                         debug("pkt data received (0x%x)\n", local);
 291                 }
 292                 words--;
 293                 dptr += sizeof(u32);
 294         }
 295
 296         if (wait_for_transfer_complete(control)) {
 297                 error = -1;
 298                 goto exit;
 299         }
 300         return 0;
 301 exit:
 302         /* error, reset the controller. */
 303         i2c_reset_controller(i2c_bus);
 304
 305         return error;
 306 }
 307
 308 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
 309                                 u32 len, bool end_with_repeated_start)
 310 {
 311         int error;
 312         struct i2c_trans_info trans_info;
 313
 314         trans_info.address = addr;
 315         trans_info.buf = data;
 316         trans_info.flags = I2C_IS_WRITE;
 317         if (end_with_repeated_start)
 318                 trans_info.flags |= I2C_USE_REPEATED_START;
 319         trans_info.num_bytes = len;
 320         trans_info.is_10bit_address = 0;
 321
 322         error = send_recv_packets(i2c_bus, &trans_info);
 323         if (error)
 324                 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
 325
 326         return error;
 327 }
 328
 329 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
 330                                u32 len)
 331 {
 332         int error;
 333         struct i2c_trans_info trans_info;
 334
 335         trans_info.address = addr | 1;
 336         trans_info.buf = data;
 337         trans_info.flags = 0;
 338         trans_info.num_bytes = len;
 339         trans_info.is_10bit_address = 0;
 340
 341         error = send_recv_packets(i2c_bus, &trans_info);
 342         if (error)
 343                 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
 344
 345         return error;
 346 }
 347
 348 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 349 {
 350         struct i2c_bus *i2c_bus = dev_get_priv(dev);
 351
 352         i2c_bus->speed = speed;
 353         i2c_init_controller(i2c_bus);
 354
 355         return 0;
 356 }
 357
 358 static int tegra_i2c_probe(struct udevice *dev)
 359 {
 360         struct i2c_bus *i2c_bus = dev_get_priv(dev);
 361         int ret;
 362         bool is_dvc;
 363
 364         i2c_bus->id = dev->seq;
 365         i2c_bus->type = dev_get_driver_data(dev);
 366         i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
 367         if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
 368                 debug("%s: Cannot get regs address\n", __func__);
 369                 return -EINVAL;
 370         }
 371
 372         ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
 373         if (ret) {
 374                 pr_err("reset_get_by_name() failed: %d\n", ret);
 375                 return ret;
 376         }
 377         ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
 378         if (ret) {
 379                 pr_err("clk_get_by_name() failed: %d\n", ret);
 380                 return ret;
 381         }
 382
 383 #ifndef CONFIG_TEGRA186
 384         /*
 385          * We don't have a binding for pinmux yet. Leave it out for now. So
 386          * far no one needs anything other than the default.
 387          */
 388         i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
 389
 390         /*
 391          * We can't specify the pinmux config in the fdt, so I2C2 will not
 392          * work on Seaboard. It normally has no devices on it anyway.
 393          * You could add in this little hack if you need to use it.
 394          * The correct solution is a pinmux binding in the fdt.
 395          *
 396          *      if (i2c_bus->clk.id == PERIPH_ID_I2C2)
 397          *              i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
 398          */
 399 #endif
 400
 401         is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
 402         if (is_dvc) {
 403                 i2c_bus->control =
 404                         &((struct dvc_ctlr *)i2c_bus->regs)->control;
 405         } else {
 406                 i2c_bus->control = &i2c_bus->regs->control;
 407         }
 408         i2c_init_controller(i2c_bus);
 409         debug("%s: controller bus %d at %p, speed %d: ",
 410               is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
 411
 412         return 0;
 413 }
 414
 415 /* i2c write version without the register address */
 416 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
 417                           int len, bool end_with_repeated_start)
 418 {
 419         int rc;
 420
 421         debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
 422         debug("write_data: ");
 423         /* use rc for counter */
 424         for (rc = 0; rc < len; ++rc)
 425                 debug(" 0x%02x", buffer[rc]);
 426         debug("\n");
 427
 428         /* Shift 7-bit address over for lower-level i2c functions */
 429         rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
 430                                   end_with_repeated_start);
 431         if (rc)
 432                 debug("i2c_write_data(): rc=%d\n", rc);
 433
 434         return rc;
 435 }
 436
 437 /* i2c read version without the register address */
 438 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
 439                          int len)
 440 {
 441         int rc;
 442
 443         debug("inside i2c_read_data():\n");
 444         /* Shift 7-bit address over for lower-level i2c functions */
 445         rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
 446         if (rc) {
 447                 debug("i2c_read_data(): rc=%d\n", rc);
 448                 return rc;
 449         }
 450
 451         debug("i2c_read_data: ");
 452         /* reuse rc for counter*/
 453         for (rc = 0; rc < len; ++rc)
 454                 debug(" 0x%02x", buffer[rc]);
 455         debug("\n");
 456
 457         return 0;
 458 }
 459
 460 /* Probe to see if a chip is present. */
 461 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 462                                 uint chip_flags)
 463 {
 464         struct i2c_bus *i2c_bus = dev_get_priv(bus);
 465         int rc;
 466         u8 reg;
 467
 468         /* Shift 7-bit address over for lower-level i2c functions */
 469         rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
 470                                   false);
 471
 472         return rc;
 473 }
 474
 475 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 476                           int nmsgs)
 477 {
 478         struct i2c_bus *i2c_bus = dev_get_priv(bus);
 479         int ret;
 480
 481         debug("i2c_xfer: %d messages\n", nmsgs);
 482         for (; nmsgs > 0; nmsgs--, msg++) {
 483                 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
 484
 485                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 486                 if (msg->flags & I2C_M_RD) {
 487                         ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
 488                                             msg->len);
 489                 } else {
 490                         ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
 491                                              msg->len, next_is_read);
 492                 }
 493                 if (ret) {
 494                         debug("i2c_write: error sending\n");
 495                         return -EREMOTEIO;
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int tegra_i2c_get_dvc_bus(struct udevice **busp)
 503 {
 504         return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
 505 }
 506
 507 static const struct dm_i2c_ops tegra_i2c_ops = {
 508         .xfer           = tegra_i2c_xfer,
 509         .probe_chip     = tegra_i2c_probe_chip,
 510         .set_bus_speed  = tegra_i2c_set_bus_speed,
 511 };
 512
 513 static const struct udevice_id tegra_i2c_ids[] = {
 514         { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
 515         { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
 516         { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
 517         { }
 518 };
 519
 520 U_BOOT_DRIVER(i2c_tegra) = {
 521         .name   = "i2c_tegra",
 522         .id     = UCLASS_I2C,
 523         .of_match = tegra_i2c_ids,
 524         .probe  = tegra_i2c_probe,
 525         .priv_auto_alloc_size = sizeof(struct i2c_bus),
 526         .ops    = &tegra_i2c_ops,
 527 };