drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <log.h>
  11 #include <reset.h>
  12 #include <linux/bitops.h>
  13 #include <linux/delay.h>
  14
  15 #include <dm/device.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 /* STM32 I2C registers */
  20 struct stm32_i2c_regs {
  21         u32 cr1;        /* I2C control register 1 */
  22         u32 cr2;        /* I2C control register 2 */
  23         u32 oar1;       /* I2C own address 1 register */
  24         u32 oar2;       /* I2C own address 2 register */
  25         u32 timingr;    /* I2C timing register */
  26         u32 timeoutr;   /* I2C timeout register */
  27         u32 isr;        /* I2C interrupt and status register */
  28         u32 icr;        /* I2C interrupt clear register */
  29         u32 pecr;       /* I2C packet error checking register */
  30         u32 rxdr;       /* I2C receive data register */
  31         u32 txdr;       /* I2C transmit data register */
  32 };
  33
  34 #define STM32_I2C_CR1                           0x00
  35 #define STM32_I2C_CR2                           0x04
  36 #define STM32_I2C_TIMINGR                       0x10
  37 #define STM32_I2C_ISR                           0x18
  38 #define STM32_I2C_ICR                           0x1C
  39 #define STM32_I2C_RXDR                          0x24
  40 #define STM32_I2C_TXDR                          0x28
  41
  42 /* STM32 I2C control 1 */
  43 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  44 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  45 #define STM32_I2C_CR1_TCIE                      BIT(6)
  46 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  47 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  48 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  49 #define STM32_I2C_CR1_RXIE                      BIT(2)
  50 #define STM32_I2C_CR1_TXIE                      BIT(1)
  51 #define STM32_I2C_CR1_PE                        BIT(0)
  52
  53 /* STM32 I2C control 2 */
  54 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  55 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  56 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  57 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  58 #define STM32_I2C_CR2_NACK                      BIT(15)
  59 #define STM32_I2C_CR2_STOP                      BIT(14)
  60 #define STM32_I2C_CR2_START                     BIT(13)
  61 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  62 #define STM32_I2C_CR2_ADD10                     BIT(11)
  63 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  64 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  65 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  66 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  67 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  68 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  69                                                 | STM32_I2C_CR2_NBYTES_MASK \
  70                                                 | STM32_I2C_CR2_SADD7_MASK \
  71                                                 | STM32_I2C_CR2_RELOAD \
  72                                                 | STM32_I2C_CR2_RD_WRN)
  73
  74 /* STM32 I2C Interrupt Status */
  75 #define STM32_I2C_ISR_BUSY                      BIT(15)
  76 #define STM32_I2C_ISR_ARLO                      BIT(9)
  77 #define STM32_I2C_ISR_BERR                      BIT(8)
  78 #define STM32_I2C_ISR_TCR                       BIT(7)
  79 #define STM32_I2C_ISR_TC                        BIT(6)
  80 #define STM32_I2C_ISR_STOPF                     BIT(5)
  81 #define STM32_I2C_ISR_NACKF                     BIT(4)
  82 #define STM32_I2C_ISR_ADDR                      BIT(3)
  83 #define STM32_I2C_ISR_RXNE                      BIT(2)
  84 #define STM32_I2C_ISR_TXIS                      BIT(1)
  85 #define STM32_I2C_ISR_TXE                       BIT(0)
  86 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  87                                                 | STM32_I2C_ISR_ARLO)
  88
  89 /* STM32 I2C Interrupt Clear */
  90 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  91 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  92 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  93 #define STM32_I2C_ICR_NACKCF                    BIT(4)
  94
  95 /* STM32 I2C Timing */
  96 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
  97 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
  98 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
  99 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
 100 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
 101
 102 #define STM32_I2C_MAX_LEN                       0xff
 103
 104 #define STM32_I2C_DNF_DEFAULT                   0
 105 #define STM32_I2C_DNF_MAX                       16
 106
 107 #define STM32_I2C_ANALOG_FILTER_ENABLE  1
 108 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 109 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 110
 111 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 112 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 113
 114 #define STM32_PRESC_MAX                         BIT(4)
 115 #define STM32_SCLDEL_MAX                        BIT(4)
 116 #define STM32_SDADEL_MAX                        BIT(4)
 117 #define STM32_SCLH_MAX                          BIT(8)
 118 #define STM32_SCLL_MAX                          BIT(8)
 119
 120 #define STM32_NSEC_PER_SEC                      1000000000L
 121
 122 /**
 123  * struct stm32_i2c_spec - private i2c specification timing
 124  * @rate: I2C bus speed (Hz)
 125  * @rate_min: 80% of I2C bus speed (Hz)
 126  * @rate_max: 120% of I2C bus speed (Hz)
 127  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 128  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 129  * @hddat_min: Min data hold time (ns)
 130  * @vddat_max: Max data valid time (ns)
 131  * @sudat_min: Min data setup time (ns)
 132  * @l_min: Min low period of the SCL clock (ns)
 133  * @h_min: Min high period of the SCL clock (ns)
 134  */
 135
 136 struct stm32_i2c_spec {
 137         u32 rate;
 138         u32 rate_min;
 139         u32 rate_max;
 140         u32 fall_max;
 141         u32 rise_max;
 142         u32 hddat_min;
 143         u32 vddat_max;
 144         u32 sudat_min;
 145         u32 l_min;
 146         u32 h_min;
 147 };
 148
 149 /**
 150  * struct stm32_i2c_setup - private I2C timing setup parameters
 151  * @speed_freq: I2C speed frequency  (Hz)
 152  * @clock_src: I2C clock source frequency (Hz)
 153  * @rise_time: Rise time (ns)
 154  * @fall_time: Fall time (ns)
 155  * @dnf: Digital filter coefficient (0-16)
 156  * @analog_filter: Analog filter delay (On/Off)
 157  */
 158 struct stm32_i2c_setup {
 159         u32 speed_freq;
 160         u32 clock_src;
 161         u32 rise_time;
 162         u32 fall_time;
 163         u8 dnf;
 164         bool analog_filter;
 165 };
 166
 167 /**
 168  * struct stm32_i2c_timings - private I2C output parameters
 169  * @prec: Prescaler value
 170  * @scldel: Data setup time
 171  * @sdadel: Data hold time
 172  * @sclh: SCL high period (master mode)
 173  * @sclh: SCL low period (master mode)
 174  */
 175 struct stm32_i2c_timings {
 176         struct list_head node;
 177         u8 presc;
 178         u8 scldel;
 179         u8 sdadel;
 180         u8 sclh;
 181         u8 scll;
 182 };
 183
 184 struct stm32_i2c_priv {
 185         struct stm32_i2c_regs *regs;
 186         struct clk clk;
 187         struct stm32_i2c_setup *setup;
 188         u32 speed;
 189 };
 190
 191 static const struct stm32_i2c_spec i2c_specs[] = {
 192         /* Standard speed - 100 KHz */
 193         [IC_SPEED_MODE_STANDARD] = {
 194                 .rate = I2C_SPEED_STANDARD_RATE,
 195                 .rate_min = 8000,
 196                 .rate_max = 120000,
 197                 .fall_max = 300,
 198                 .rise_max = 1000,
 199                 .hddat_min = 0,
 200                 .vddat_max = 3450,
 201                 .sudat_min = 250,
 202                 .l_min = 4700,
 203                 .h_min = 4000,
 204         },
 205         /* Fast speed - 400 KHz */
 206         [IC_SPEED_MODE_FAST] = {
 207                 .rate = I2C_SPEED_FAST_RATE,
 208                 .rate_min = 320000,
 209                 .rate_max = 480000,
 210                 .fall_max = 300,
 211                 .rise_max = 300,
 212                 .hddat_min = 0,
 213                 .vddat_max = 900,
 214                 .sudat_min = 100,
 215                 .l_min = 1300,
 216                 .h_min = 600,
 217         },
 218         /* Fast Plus Speed - 1 MHz */
 219         [IC_SPEED_MODE_FAST_PLUS] = {
 220                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 221                 .rate_min = 800000,
 222                 .rate_max = 1200000,
 223                 .fall_max = 100,
 224                 .rise_max = 120,
 225                 .hddat_min = 0,
 226                 .vddat_max = 450,
 227                 .sudat_min = 50,
 228                 .l_min = 500,
 229                 .h_min = 260,
 230         },
 231 };
 232
 233 static const struct stm32_i2c_setup stm32f7_setup = {
 234         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 235         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 236         .dnf = STM32_I2C_DNF_DEFAULT,
 237         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 238 };
 239
 240 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 241 {
 242         struct stm32_i2c_regs *regs = i2c_priv->regs;
 243         u32 status = readl(&regs->isr);
 244
 245         if (status & STM32_I2C_ISR_BUSY)
 246                 return -EBUSY;
 247
 248         return 0;
 249 }
 250
 251 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 252                                     struct i2c_msg *msg, bool stop)
 253 {
 254         struct stm32_i2c_regs *regs = i2c_priv->regs;
 255         u32 cr2 = readl(&regs->cr2);
 256
 257         /* Set transfer direction */
 258         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 259         if (msg->flags & I2C_M_RD)
 260                 cr2 |= STM32_I2C_CR2_RD_WRN;
 261
 262         /* Set slave address */
 263         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 264         if (msg->flags & I2C_M_TEN) {
 265                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 266                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 267                 cr2 |= STM32_I2C_CR2_ADD10;
 268         } else {
 269                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 270                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 271         }
 272
 273         /* Set nb bytes to transfer and reload or autoend bits */
 274         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 275                  STM32_I2C_CR2_AUTOEND);
 276         if (msg->len > STM32_I2C_MAX_LEN) {
 277                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 278                 cr2 |= STM32_I2C_CR2_RELOAD;
 279         } else {
 280                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 281         }
 282
 283         /* Write configurations register */
 284         writel(cr2, &regs->cr2);
 285
 286         /* START/ReSTART generation */
 287         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 288 }
 289
 290 /*
 291  * RELOAD mode must be selected if total number of data bytes to be
 292  * sent is greater than MAX_LEN
 293  */
 294
 295 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 296                                     struct i2c_msg *msg, bool stop)
 297 {
 298         struct stm32_i2c_regs *regs = i2c_priv->regs;
 299         u32 cr2 = readl(&regs->cr2);
 300
 301         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 302
 303         if (msg->len > STM32_I2C_MAX_LEN) {
 304                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 305         } else {
 306                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 307                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 308         }
 309
 310         writel(cr2, &regs->cr2);
 311 }
 312
 313 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 314                                 u32 flags, u32 *status)
 315 {
 316         struct stm32_i2c_regs *regs = i2c_priv->regs;
 317         u32 time_start = get_timer(0);
 318
 319         *status = readl(&regs->isr);
 320         while (!(*status & flags)) {
 321                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 322                         debug("%s: i2c timeout\n", __func__);
 323                         return -ETIMEDOUT;
 324                 }
 325
 326                 *status = readl(&regs->isr);
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 333 {
 334         struct stm32_i2c_regs *regs = i2c_priv->regs;
 335         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 336                    STM32_I2C_ISR_STOPF;
 337         u32 status;
 338         int ret;
 339
 340         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 341         if (ret)
 342                 return ret;
 343
 344         if (status & STM32_I2C_ISR_BERR) {
 345                 debug("%s: Bus error\n", __func__);
 346
 347                 /* Clear BERR flag */
 348                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 349
 350                 return -EIO;
 351         }
 352
 353         if (status & STM32_I2C_ISR_ARLO) {
 354                 debug("%s: Arbitration lost\n", __func__);
 355
 356                 /* Clear ARLO flag */
 357                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 358
 359                 return -EAGAIN;
 360         }
 361
 362         if (status & STM32_I2C_ISR_NACKF) {
 363                 debug("%s: Receive NACK\n", __func__);
 364
 365                 /* Clear NACK flag */
 366                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 367
 368                 /* Wait until STOPF flag is set */
 369                 mask = STM32_I2C_ISR_STOPF;
 370                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 371                 if (ret)
 372                         return ret;
 373
 374                 ret = -EIO;
 375         }
 376
 377         if (status & STM32_I2C_ISR_STOPF) {
 378                 /* Clear STOP flag */
 379                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 380
 381                 /* Clear control register 2 */
 382                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 383         }
 384
 385         return ret;
 386 }
 387
 388 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 389                                   struct i2c_msg *msg, bool stop)
 390 {
 391         struct stm32_i2c_regs *regs = i2c_priv->regs;
 392         u32 status;
 393         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 394                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 395         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 396                           STM32_I2C_MAX_LEN : msg->len;
 397         int ret = 0;
 398
 399         /* Add errors */
 400         mask |= STM32_I2C_ISR_ERRORS;
 401
 402         stm32_i2c_message_start(i2c_priv, msg, stop);
 403
 404         while (msg->len) {
 405                 /*
 406                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 407                  * RXNE/BERR/ARLO flags are set
 408                  */
 409                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 410                 if (ret)
 411                         break;
 412
 413                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 414                         break;
 415
 416                 if (status & STM32_I2C_ISR_RXNE) {
 417                         *msg->buf++ = readb(&regs->rxdr);
 418                         msg->len--;
 419                         bytes_to_rw--;
 420                 }
 421
 422                 if (status & STM32_I2C_ISR_TXIS) {
 423                         writeb(*msg->buf++, &regs->txdr);
 424                         msg->len--;
 425                         bytes_to_rw--;
 426                 }
 427
 428                 if (!bytes_to_rw && msg->len) {
 429                         /* Wait until TCR flag is set */
 430                         mask = STM32_I2C_ISR_TCR;
 431                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 432                         if (ret)
 433                                 break;
 434
 435                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 436                                       STM32_I2C_MAX_LEN : msg->len;
 437                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 438                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 439
 440                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 441                 } else if (!bytes_to_rw) {
 442                         /* Wait until TC flag is set */
 443                         mask = STM32_I2C_ISR_TC;
 444                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 445                         if (ret)
 446                                 break;
 447
 448                         if (!stop)
 449                                 /* Message sent, new message has to be sent */
 450                                 return 0;
 451                 }
 452         }
 453
 454         /* End of transfer, send stop condition */
 455         mask = STM32_I2C_CR2_STOP;
 456         setbits_le32(&regs->cr2, mask);
 457
 458         return stm32_i2c_check_end_of_message(i2c_priv);
 459 }
 460
 461 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 462                           int nmsgs)
 463 {
 464         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 465         int ret;
 466
 467         ret = stm32_i2c_check_device_busy(i2c_priv);
 468         if (ret)
 469                 return ret;
 470
 471         for (; nmsgs > 0; nmsgs--, msg++) {
 472                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 473                 if (ret)
 474                         return ret;
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 481                                        const struct stm32_i2c_spec *specs,
 482                                        struct list_head *solutions)
 483 {
 484         struct stm32_i2c_timings *v;
 485         u32 p_prev = STM32_PRESC_MAX;
 486         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 487                                        setup->clock_src);
 488         u32 af_delay_min, af_delay_max;
 489         u16 p, l, a;
 490         int sdadel_min, sdadel_max, scldel_min;
 491         int ret = 0;
 492
 493         af_delay_min = setup->analog_filter ?
 494                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 495         af_delay_max = setup->analog_filter ?
 496                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 497
 498         sdadel_min = specs->hddat_min + setup->fall_time -
 499                      af_delay_min - (setup->dnf + 3) * i2cclk;
 500
 501         sdadel_max = specs->vddat_max - setup->rise_time -
 502                      af_delay_max - (setup->dnf + 4) * i2cclk;
 503
 504         scldel_min = setup->rise_time + specs->sudat_min;
 505
 506         if (sdadel_min < 0)
 507                 sdadel_min = 0;
 508         if (sdadel_max < 0)
 509                 sdadel_max = 0;
 510
 511         debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
 512               sdadel_min, sdadel_max, scldel_min);
 513
 514         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 515         for (p = 0; p < STM32_PRESC_MAX; p++) {
 516                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 517                         int scldel = (l + 1) * (p + 1) * i2cclk;
 518
 519                         if (scldel < scldel_min)
 520                                 continue;
 521
 522                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 523                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 524
 525                                 if (((sdadel >= sdadel_min) &&
 526                                      (sdadel <= sdadel_max)) &&
 527                                     (p != p_prev)) {
 528                                         v = calloc(1, sizeof(*v));
 529                                         if (!v)
 530                                                 return -ENOMEM;
 531
 532                                         v->presc = p;
 533                                         v->scldel = l;
 534                                         v->sdadel = a;
 535                                         p_prev = p;
 536
 537                                         list_add_tail(&v->node, solutions);
 538                                         break;
 539                                 }
 540                         }
 541
 542                         if (p_prev == p)
 543                                 break;
 544                 }
 545         }
 546
 547         if (list_empty(solutions)) {
 548                 pr_err("%s: no Prescaler solution\n", __func__);
 549                 ret = -EPERM;
 550         }
 551
 552         return ret;
 553 }
 554
 555 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 556                                      const struct stm32_i2c_spec *specs,
 557                                      struct list_head *solutions,
 558                                      struct stm32_i2c_timings *s)
 559 {
 560         struct stm32_i2c_timings *v;
 561         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 562                                        setup->speed_freq);
 563         u32 clk_error_prev = i2cbus;
 564         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 565                                        setup->clock_src);
 566         u32 clk_min, clk_max;
 567         u32 af_delay_min;
 568         u32 dnf_delay;
 569         u32 tsync;
 570         u16 l, h;
 571         bool sol_found = false;
 572         int ret = 0;
 573
 574         af_delay_min = setup->analog_filter ?
 575                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 576         dnf_delay = setup->dnf * i2cclk;
 577
 578         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 579         clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
 580         clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
 581
 582         /*
 583          * Among Prescaler possibilities discovered above figures out SCL Low
 584          * and High Period. Provided:
 585          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 586          *   defined by I2C Specification. I2C Clock has to be lower than
 587          *   (SCL Low Period - Analog/Digital filters) / 4.
 588          * - SCL High Period has to be lower than High Period of the SCL Clock
 589          *   defined by I2C Specification
 590          * - I2C Clock has to be lower than SCL High Period
 591          */
 592         list_for_each_entry(v, solutions, node) {
 593                 u32 prescaler = (v->presc + 1) * i2cclk;
 594
 595                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 596                         u32 tscl_l = (l + 1) * prescaler + tsync;
 597
 598                         if (tscl_l < specs->l_min ||
 599                             (i2cclk >=
 600                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 601                                 continue;
 602                         }
 603
 604                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 605                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 606                                 u32 tscl = tscl_l + tscl_h +
 607                                            setup->rise_time + setup->fall_time;
 608
 609                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 610                                     (tscl_h >= specs->h_min) &&
 611                                     (i2cclk < tscl_h)) {
 612                                         u32 clk_error;
 613
 614                                         if (tscl > i2cbus)
 615                                                 clk_error = tscl - i2cbus;
 616                                         else
 617                                                 clk_error = i2cbus - tscl;
 618
 619                                         if (clk_error < clk_error_prev) {
 620                                                 clk_error_prev = clk_error;
 621                                                 v->scll = l;
 622                                                 v->sclh = h;
 623                                                 sol_found = true;
 624                                                 memcpy(s, v, sizeof(*s));
 625                                         }
 626                                 }
 627                         }
 628                 }
 629         }
 630
 631         if (!sol_found) {
 632                 pr_err("%s: no solution at all\n", __func__);
 633                 ret = -EPERM;
 634         }
 635
 636         return ret;
 637 }
 638
 639 static const struct stm32_i2c_spec *get_specs(u32 rate)
 640 {
 641         unsigned int i;
 642
 643         for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
 644                 if (rate <= i2c_specs[i].rate)
 645                         return &i2c_specs[i];
 646
 647         /* NOT REACHED */
 648         return ERR_PTR(-EINVAL);
 649 }
 650
 651 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 652                                     struct stm32_i2c_setup *setup,
 653                                     struct stm32_i2c_timings *output)
 654 {
 655         const struct stm32_i2c_spec *specs;
 656         struct stm32_i2c_timings *v, *_v;
 657         struct list_head solutions;
 658         int ret;
 659
 660         specs = get_specs(setup->speed_freq);
 661         if (specs == ERR_PTR(-EINVAL)) {
 662                 pr_err("%s: speed out of bound {%d}\n", __func__,
 663                        setup->speed_freq);
 664                 return -EINVAL;
 665         }
 666
 667         if (setup->rise_time > specs->rise_max ||
 668             setup->fall_time > specs->fall_max) {
 669                 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 670                        __func__,
 671                        setup->rise_time, specs->rise_max,
 672                        setup->fall_time, specs->fall_max);
 673                 return -EINVAL;
 674         }
 675
 676         if (setup->dnf > STM32_I2C_DNF_MAX) {
 677                 pr_err("%s: DNF out of bound %d/%d\n", __func__,
 678                        setup->dnf, STM32_I2C_DNF_MAX);
 679                 return -EINVAL;
 680         }
 681
 682         INIT_LIST_HEAD(&solutions);
 683         ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
 684         if (ret)
 685                 goto exit;
 686
 687         ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
 688         if (ret)
 689                 goto exit;
 690
 691         debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 692               __func__, output->presc,
 693               output->scldel, output->sdadel,
 694               output->scll, output->sclh);
 695
 696 exit:
 697         /* Release list and memory */
 698         list_for_each_entry_safe(v, _v, &solutions, node) {
 699                 list_del(&v->node);
 700                 free(v);
 701         }
 702
 703         return ret;
 704 }
 705
 706 static u32 get_lower_rate(u32 rate)
 707 {
 708         int i;
 709
 710         for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
 711                 if (rate > i2c_specs[i].rate)
 712                         return i2c_specs[i].rate;
 713
 714         return i2c_specs[0].rate;
 715 }
 716
 717 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 718                                   struct stm32_i2c_timings *timing)
 719 {
 720         struct stm32_i2c_setup *setup = i2c_priv->setup;
 721         int ret = 0;
 722
 723         setup->speed_freq = i2c_priv->speed;
 724         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 725
 726         if (!setup->clock_src) {
 727                 pr_err("%s: clock rate is 0\n", __func__);
 728                 return -EINVAL;
 729         }
 730
 731         do {
 732                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 733                 if (ret) {
 734                         debug("%s: failed to compute I2C timings.\n",
 735                               __func__);
 736                         if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
 737                                 setup->speed_freq =
 738                                         get_lower_rate(setup->speed_freq);
 739                                 debug("%s: downgrade I2C Speed Freq to (%i)\n",
 740                                       __func__, setup->speed_freq);
 741                         } else {
 742                                 break;
 743                         }
 744                 }
 745         } while (ret);
 746
 747         if (ret) {
 748                 pr_err("%s: impossible to compute I2C timings.\n", __func__);
 749                 return ret;
 750         }
 751
 752         debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
 753               setup->speed_freq, setup->clock_src);
 754         debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
 755               setup->rise_time, setup->fall_time);
 756         debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
 757               setup->analog_filter ? "On" : "Off", setup->dnf);
 758
 759         i2c_priv->speed = setup->speed_freq;
 760
 761         return 0;
 762 }
 763
 764 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 765 {
 766         struct stm32_i2c_regs *regs = i2c_priv->regs;
 767         struct stm32_i2c_timings t;
 768         int ret;
 769         u32 timing = 0;
 770
 771         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 772         if (ret)
 773                 return ret;
 774
 775         /* Disable I2C */
 776         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 777
 778         /* Timing settings */
 779         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 780         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 781         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 782         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 783         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 784         writel(timing, &regs->timingr);
 785
 786         /* Enable I2C */
 787         if (i2c_priv->setup->analog_filter)
 788                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 789         else
 790                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 791         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 792
 793         return 0;
 794 }
 795
 796 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 797 {
 798         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 799
 800         if (speed > I2C_SPEED_FAST_PLUS_RATE) {
 801                 debug("%s: Speed %d not supported\n", __func__, speed);
 802                 return -EINVAL;
 803         }
 804
 805         i2c_priv->speed = speed;
 806
 807         return stm32_i2c_hw_config(i2c_priv);
 808 }
 809
 810 static int stm32_i2c_probe(struct udevice *dev)
 811 {
 812         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 813         struct reset_ctl reset_ctl;
 814         fdt_addr_t addr;
 815         int ret;
 816
 817         addr = dev_read_addr(dev);
 818         if (addr == FDT_ADDR_T_NONE)
 819                 return -EINVAL;
 820
 821         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 822
 823         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 824         if (ret)
 825                 return ret;
 826
 827         ret = clk_enable(&i2c_priv->clk);
 828         if (ret)
 829                 goto clk_free;
 830
 831         ret = reset_get_by_index(dev, 0, &reset_ctl);
 832         if (ret)
 833                 goto clk_disable;
 834
 835         reset_assert(&reset_ctl);
 836         udelay(2);
 837         reset_deassert(&reset_ctl);
 838
 839         return 0;
 840
 841 clk_disable:
 842         clk_disable(&i2c_priv->clk);
 843 clk_free:
 844         clk_free(&i2c_priv->clk);
 845
 846         return ret;
 847 }
 848
 849 static int stm32_ofdata_to_platdata(struct udevice *dev)
 850 {
 851         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 852         u32 rise_time, fall_time;
 853
 854         i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
 855         if (!i2c_priv->setup)
 856                 return -EINVAL;
 857
 858         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
 859         if (rise_time)
 860                 i2c_priv->setup->rise_time = rise_time;
 861
 862         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
 863         if (fall_time)
 864                 i2c_priv->setup->fall_time = fall_time;
 865
 866         return 0;
 867 }
 868
 869 static const struct dm_i2c_ops stm32_i2c_ops = {
 870         .xfer = stm32_i2c_xfer,
 871         .set_bus_speed = stm32_i2c_set_bus_speed,
 872 };
 873
 874 static const struct udevice_id stm32_i2c_of_match[] = {
 875         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
 876         {}
 877 };
 878
 879 U_BOOT_DRIVER(stm32f7_i2c) = {
 880         .name = "stm32f7-i2c",
 881         .id = UCLASS_I2C,
 882         .of_match = stm32_i2c_of_match,
 883         .ofdata_to_platdata = stm32_ofdata_to_platdata,
 884         .probe = stm32_i2c_probe,
 885         .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
 886         .ops = &stm32_i2c_ops,
 887 };