drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <log.h>
  11 #include <reset.h>
  12
  13 #include <dm/device.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16
  17 /* STM32 I2C registers */
  18 struct stm32_i2c_regs {
  19         u32 cr1;        /* I2C control register 1 */
  20         u32 cr2;        /* I2C control register 2 */
  21         u32 oar1;       /* I2C own address 1 register */
  22         u32 oar2;       /* I2C own address 2 register */
  23         u32 timingr;    /* I2C timing register */
  24         u32 timeoutr;   /* I2C timeout register */
  25         u32 isr;        /* I2C interrupt and status register */
  26         u32 icr;        /* I2C interrupt clear register */
  27         u32 pecr;       /* I2C packet error checking register */
  28         u32 rxdr;       /* I2C receive data register */
  29         u32 txdr;       /* I2C transmit data register */
  30 };
  31
  32 #define STM32_I2C_CR1                           0x00
  33 #define STM32_I2C_CR2                           0x04
  34 #define STM32_I2C_TIMINGR                       0x10
  35 #define STM32_I2C_ISR                           0x18
  36 #define STM32_I2C_ICR                           0x1C
  37 #define STM32_I2C_RXDR                          0x24
  38 #define STM32_I2C_TXDR                          0x28
  39
  40 /* STM32 I2C control 1 */
  41 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  42 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  43 #define STM32_I2C_CR1_TCIE                      BIT(6)
  44 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  45 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  46 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  47 #define STM32_I2C_CR1_RXIE                      BIT(2)
  48 #define STM32_I2C_CR1_TXIE                      BIT(1)
  49 #define STM32_I2C_CR1_PE                        BIT(0)
  50
  51 /* STM32 I2C control 2 */
  52 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  53 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  54 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  55 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  56 #define STM32_I2C_CR2_NACK                      BIT(15)
  57 #define STM32_I2C_CR2_STOP                      BIT(14)
  58 #define STM32_I2C_CR2_START                     BIT(13)
  59 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  60 #define STM32_I2C_CR2_ADD10                     BIT(11)
  61 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  62 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  63 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  64 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  65 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  66 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  67                                                 | STM32_I2C_CR2_NBYTES_MASK \
  68                                                 | STM32_I2C_CR2_SADD7_MASK \
  69                                                 | STM32_I2C_CR2_RELOAD \
  70                                                 | STM32_I2C_CR2_RD_WRN)
  71
  72 /* STM32 I2C Interrupt Status */
  73 #define STM32_I2C_ISR_BUSY                      BIT(15)
  74 #define STM32_I2C_ISR_ARLO                      BIT(9)
  75 #define STM32_I2C_ISR_BERR                      BIT(8)
  76 #define STM32_I2C_ISR_TCR                       BIT(7)
  77 #define STM32_I2C_ISR_TC                        BIT(6)
  78 #define STM32_I2C_ISR_STOPF                     BIT(5)
  79 #define STM32_I2C_ISR_NACKF                     BIT(4)
  80 #define STM32_I2C_ISR_ADDR                      BIT(3)
  81 #define STM32_I2C_ISR_RXNE                      BIT(2)
  82 #define STM32_I2C_ISR_TXIS                      BIT(1)
  83 #define STM32_I2C_ISR_TXE                       BIT(0)
  84 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  85                                                 | STM32_I2C_ISR_ARLO)
  86
  87 /* STM32 I2C Interrupt Clear */
  88 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  89 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  90 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  91 #define STM32_I2C_ICR_NACKCF                    BIT(4)
  92
  93 /* STM32 I2C Timing */
  94 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
  95 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
  96 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
  97 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
  98 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
  99
 100 #define STM32_I2C_MAX_LEN                       0xff
 101
 102 #define STM32_I2C_DNF_DEFAULT                   0
 103 #define STM32_I2C_DNF_MAX                       16
 104
 105 #define STM32_I2C_ANALOG_FILTER_ENABLE  1
 106 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 107 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 108
 109 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 110 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 111
 112 #define STM32_PRESC_MAX                         BIT(4)
 113 #define STM32_SCLDEL_MAX                        BIT(4)
 114 #define STM32_SDADEL_MAX                        BIT(4)
 115 #define STM32_SCLH_MAX                          BIT(8)
 116 #define STM32_SCLL_MAX                          BIT(8)
 117
 118 #define STM32_NSEC_PER_SEC                      1000000000L
 119
 120 /**
 121  * struct stm32_i2c_spec - private i2c specification timing
 122  * @rate: I2C bus speed (Hz)
 123  * @rate_min: 80% of I2C bus speed (Hz)
 124  * @rate_max: 120% of I2C bus speed (Hz)
 125  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 126  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 127  * @hddat_min: Min data hold time (ns)
 128  * @vddat_max: Max data valid time (ns)
 129  * @sudat_min: Min data setup time (ns)
 130  * @l_min: Min low period of the SCL clock (ns)
 131  * @h_min: Min high period of the SCL clock (ns)
 132  */
 133
 134 struct stm32_i2c_spec {
 135         u32 rate;
 136         u32 rate_min;
 137         u32 rate_max;
 138         u32 fall_max;
 139         u32 rise_max;
 140         u32 hddat_min;
 141         u32 vddat_max;
 142         u32 sudat_min;
 143         u32 l_min;
 144         u32 h_min;
 145 };
 146
 147 /**
 148  * struct stm32_i2c_setup - private I2C timing setup parameters
 149  * @speed_freq: I2C speed frequency  (Hz)
 150  * @clock_src: I2C clock source frequency (Hz)
 151  * @rise_time: Rise time (ns)
 152  * @fall_time: Fall time (ns)
 153  * @dnf: Digital filter coefficient (0-16)
 154  * @analog_filter: Analog filter delay (On/Off)
 155  */
 156 struct stm32_i2c_setup {
 157         u32 speed_freq;
 158         u32 clock_src;
 159         u32 rise_time;
 160         u32 fall_time;
 161         u8 dnf;
 162         bool analog_filter;
 163 };
 164
 165 /**
 166  * struct stm32_i2c_timings - private I2C output parameters
 167  * @prec: Prescaler value
 168  * @scldel: Data setup time
 169  * @sdadel: Data hold time
 170  * @sclh: SCL high period (master mode)
 171  * @sclh: SCL low period (master mode)
 172  */
 173 struct stm32_i2c_timings {
 174         struct list_head node;
 175         u8 presc;
 176         u8 scldel;
 177         u8 sdadel;
 178         u8 sclh;
 179         u8 scll;
 180 };
 181
 182 struct stm32_i2c_priv {
 183         struct stm32_i2c_regs *regs;
 184         struct clk clk;
 185         struct stm32_i2c_setup *setup;
 186         u32 speed;
 187 };
 188
 189 static const struct stm32_i2c_spec i2c_specs[] = {
 190         /* Standard speed - 100 KHz */
 191         [IC_SPEED_MODE_STANDARD] = {
 192                 .rate = I2C_SPEED_STANDARD_RATE,
 193                 .rate_min = 8000,
 194                 .rate_max = 120000,
 195                 .fall_max = 300,
 196                 .rise_max = 1000,
 197                 .hddat_min = 0,
 198                 .vddat_max = 3450,
 199                 .sudat_min = 250,
 200                 .l_min = 4700,
 201                 .h_min = 4000,
 202         },
 203         /* Fast speed - 400 KHz */
 204         [IC_SPEED_MODE_FAST] = {
 205                 .rate = I2C_SPEED_FAST_RATE,
 206                 .rate_min = 320000,
 207                 .rate_max = 480000,
 208                 .fall_max = 300,
 209                 .rise_max = 300,
 210                 .hddat_min = 0,
 211                 .vddat_max = 900,
 212                 .sudat_min = 100,
 213                 .l_min = 1300,
 214                 .h_min = 600,
 215         },
 216         /* Fast Plus Speed - 1 MHz */
 217         [IC_SPEED_MODE_FAST_PLUS] = {
 218                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 219                 .rate_min = 800000,
 220                 .rate_max = 1200000,
 221                 .fall_max = 100,
 222                 .rise_max = 120,
 223                 .hddat_min = 0,
 224                 .vddat_max = 450,
 225                 .sudat_min = 50,
 226                 .l_min = 500,
 227                 .h_min = 260,
 228         },
 229 };
 230
 231 static const struct stm32_i2c_setup stm32f7_setup = {
 232         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 233         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 234         .dnf = STM32_I2C_DNF_DEFAULT,
 235         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 236 };
 237
 238 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 239 {
 240         struct stm32_i2c_regs *regs = i2c_priv->regs;
 241         u32 status = readl(&regs->isr);
 242
 243         if (status & STM32_I2C_ISR_BUSY)
 244                 return -EBUSY;
 245
 246         return 0;
 247 }
 248
 249 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 250                                     struct i2c_msg *msg, bool stop)
 251 {
 252         struct stm32_i2c_regs *regs = i2c_priv->regs;
 253         u32 cr2 = readl(&regs->cr2);
 254
 255         /* Set transfer direction */
 256         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 257         if (msg->flags & I2C_M_RD)
 258                 cr2 |= STM32_I2C_CR2_RD_WRN;
 259
 260         /* Set slave address */
 261         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 262         if (msg->flags & I2C_M_TEN) {
 263                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 264                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 265                 cr2 |= STM32_I2C_CR2_ADD10;
 266         } else {
 267                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 268                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 269         }
 270
 271         /* Set nb bytes to transfer and reload or autoend bits */
 272         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 273                  STM32_I2C_CR2_AUTOEND);
 274         if (msg->len > STM32_I2C_MAX_LEN) {
 275                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 276                 cr2 |= STM32_I2C_CR2_RELOAD;
 277         } else {
 278                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 279         }
 280
 281         /* Write configurations register */
 282         writel(cr2, &regs->cr2);
 283
 284         /* START/ReSTART generation */
 285         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 286 }
 287
 288 /*
 289  * RELOAD mode must be selected if total number of data bytes to be
 290  * sent is greater than MAX_LEN
 291  */
 292
 293 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 294                                     struct i2c_msg *msg, bool stop)
 295 {
 296         struct stm32_i2c_regs *regs = i2c_priv->regs;
 297         u32 cr2 = readl(&regs->cr2);
 298
 299         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 300
 301         if (msg->len > STM32_I2C_MAX_LEN) {
 302                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 303         } else {
 304                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 305                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 306         }
 307
 308         writel(cr2, &regs->cr2);
 309 }
 310
 311 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 312                                 u32 flags, u32 *status)
 313 {
 314         struct stm32_i2c_regs *regs = i2c_priv->regs;
 315         u32 time_start = get_timer(0);
 316
 317         *status = readl(&regs->isr);
 318         while (!(*status & flags)) {
 319                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 320                         debug("%s: i2c timeout\n", __func__);
 321                         return -ETIMEDOUT;
 322                 }
 323
 324                 *status = readl(&regs->isr);
 325         }
 326
 327         return 0;
 328 }
 329
 330 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 331 {
 332         struct stm32_i2c_regs *regs = i2c_priv->regs;
 333         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 334                    STM32_I2C_ISR_STOPF;
 335         u32 status;
 336         int ret;
 337
 338         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 339         if (ret)
 340                 return ret;
 341
 342         if (status & STM32_I2C_ISR_BERR) {
 343                 debug("%s: Bus error\n", __func__);
 344
 345                 /* Clear BERR flag */
 346                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 347
 348                 return -EIO;
 349         }
 350
 351         if (status & STM32_I2C_ISR_ARLO) {
 352                 debug("%s: Arbitration lost\n", __func__);
 353
 354                 /* Clear ARLO flag */
 355                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 356
 357                 return -EAGAIN;
 358         }
 359
 360         if (status & STM32_I2C_ISR_NACKF) {
 361                 debug("%s: Receive NACK\n", __func__);
 362
 363                 /* Clear NACK flag */
 364                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 365
 366                 /* Wait until STOPF flag is set */
 367                 mask = STM32_I2C_ISR_STOPF;
 368                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 369                 if (ret)
 370                         return ret;
 371
 372                 ret = -EIO;
 373         }
 374
 375         if (status & STM32_I2C_ISR_STOPF) {
 376                 /* Clear STOP flag */
 377                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 378
 379                 /* Clear control register 2 */
 380                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 381         }
 382
 383         return ret;
 384 }
 385
 386 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 387                                   struct i2c_msg *msg, bool stop)
 388 {
 389         struct stm32_i2c_regs *regs = i2c_priv->regs;
 390         u32 status;
 391         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 392                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 393         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 394                           STM32_I2C_MAX_LEN : msg->len;
 395         int ret = 0;
 396
 397         /* Add errors */
 398         mask |= STM32_I2C_ISR_ERRORS;
 399
 400         stm32_i2c_message_start(i2c_priv, msg, stop);
 401
 402         while (msg->len) {
 403                 /*
 404                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 405                  * RXNE/BERR/ARLO flags are set
 406                  */
 407                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 408                 if (ret)
 409                         break;
 410
 411                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 412                         break;
 413
 414                 if (status & STM32_I2C_ISR_RXNE) {
 415                         *msg->buf++ = readb(&regs->rxdr);
 416                         msg->len--;
 417                         bytes_to_rw--;
 418                 }
 419
 420                 if (status & STM32_I2C_ISR_TXIS) {
 421                         writeb(*msg->buf++, &regs->txdr);
 422                         msg->len--;
 423                         bytes_to_rw--;
 424                 }
 425
 426                 if (!bytes_to_rw && msg->len) {
 427                         /* Wait until TCR flag is set */
 428                         mask = STM32_I2C_ISR_TCR;
 429                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 430                         if (ret)
 431                                 break;
 432
 433                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 434                                       STM32_I2C_MAX_LEN : msg->len;
 435                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 436                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 437
 438                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 439                 } else if (!bytes_to_rw) {
 440                         /* Wait until TC flag is set */
 441                         mask = STM32_I2C_ISR_TC;
 442                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 443                         if (ret)
 444                                 break;
 445
 446                         if (!stop)
 447                                 /* Message sent, new message has to be sent */
 448                                 return 0;
 449                 }
 450         }
 451
 452         /* End of transfer, send stop condition */
 453         mask = STM32_I2C_CR2_STOP;
 454         setbits_le32(&regs->cr2, mask);
 455
 456         return stm32_i2c_check_end_of_message(i2c_priv);
 457 }
 458
 459 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 460                           int nmsgs)
 461 {
 462         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 463         int ret;
 464
 465         ret = stm32_i2c_check_device_busy(i2c_priv);
 466         if (ret)
 467                 return ret;
 468
 469         for (; nmsgs > 0; nmsgs--, msg++) {
 470                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 471                 if (ret)
 472                         return ret;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 479                                        const struct stm32_i2c_spec *specs,
 480                                        struct list_head *solutions)
 481 {
 482         struct stm32_i2c_timings *v;
 483         u32 p_prev = STM32_PRESC_MAX;
 484         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 485                                        setup->clock_src);
 486         u32 af_delay_min, af_delay_max;
 487         u16 p, l, a;
 488         int sdadel_min, sdadel_max, scldel_min;
 489         int ret = 0;
 490
 491         af_delay_min = setup->analog_filter ?
 492                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 493         af_delay_max = setup->analog_filter ?
 494                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 495
 496         sdadel_min = specs->hddat_min + setup->fall_time -
 497                      af_delay_min - (setup->dnf + 3) * i2cclk;
 498
 499         sdadel_max = specs->vddat_max - setup->rise_time -
 500                      af_delay_max - (setup->dnf + 4) * i2cclk;
 501
 502         scldel_min = setup->rise_time + specs->sudat_min;
 503
 504         if (sdadel_min < 0)
 505                 sdadel_min = 0;
 506         if (sdadel_max < 0)
 507                 sdadel_max = 0;
 508
 509         debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
 510               sdadel_min, sdadel_max, scldel_min);
 511
 512         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 513         for (p = 0; p < STM32_PRESC_MAX; p++) {
 514                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 515                         int scldel = (l + 1) * (p + 1) * i2cclk;
 516
 517                         if (scldel < scldel_min)
 518                                 continue;
 519
 520                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 521                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 522
 523                                 if (((sdadel >= sdadel_min) &&
 524                                      (sdadel <= sdadel_max)) &&
 525                                     (p != p_prev)) {
 526                                         v = calloc(1, sizeof(*v));
 527                                         if (!v)
 528                                                 return -ENOMEM;
 529
 530                                         v->presc = p;
 531                                         v->scldel = l;
 532                                         v->sdadel = a;
 533                                         p_prev = p;
 534
 535                                         list_add_tail(&v->node, solutions);
 536                                         break;
 537                                 }
 538                         }
 539
 540                         if (p_prev == p)
 541                                 break;
 542                 }
 543         }
 544
 545         if (list_empty(solutions)) {
 546                 pr_err("%s: no Prescaler solution\n", __func__);
 547                 ret = -EPERM;
 548         }
 549
 550         return ret;
 551 }
 552
 553 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 554                                      const struct stm32_i2c_spec *specs,
 555                                      struct list_head *solutions,
 556                                      struct stm32_i2c_timings *s)
 557 {
 558         struct stm32_i2c_timings *v;
 559         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 560                                        setup->speed_freq);
 561         u32 clk_error_prev = i2cbus;
 562         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 563                                        setup->clock_src);
 564         u32 clk_min, clk_max;
 565         u32 af_delay_min;
 566         u32 dnf_delay;
 567         u32 tsync;
 568         u16 l, h;
 569         bool sol_found = false;
 570         int ret = 0;
 571
 572         af_delay_min = setup->analog_filter ?
 573                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 574         dnf_delay = setup->dnf * i2cclk;
 575
 576         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 577         clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
 578         clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
 579
 580         /*
 581          * Among Prescaler possibilities discovered above figures out SCL Low
 582          * and High Period. Provided:
 583          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 584          *   defined by I2C Specification. I2C Clock has to be lower than
 585          *   (SCL Low Period - Analog/Digital filters) / 4.
 586          * - SCL High Period has to be lower than High Period of the SCL Clock
 587          *   defined by I2C Specification
 588          * - I2C Clock has to be lower than SCL High Period
 589          */
 590         list_for_each_entry(v, solutions, node) {
 591                 u32 prescaler = (v->presc + 1) * i2cclk;
 592
 593                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 594                         u32 tscl_l = (l + 1) * prescaler + tsync;
 595
 596                         if (tscl_l < specs->l_min ||
 597                             (i2cclk >=
 598                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 599                                 continue;
 600                         }
 601
 602                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 603                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 604                                 u32 tscl = tscl_l + tscl_h +
 605                                            setup->rise_time + setup->fall_time;
 606
 607                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 608                                     (tscl_h >= specs->h_min) &&
 609                                     (i2cclk < tscl_h)) {
 610                                         u32 clk_error;
 611
 612                                         if (tscl > i2cbus)
 613                                                 clk_error = tscl - i2cbus;
 614                                         else
 615                                                 clk_error = i2cbus - tscl;
 616
 617                                         if (clk_error < clk_error_prev) {
 618                                                 clk_error_prev = clk_error;
 619                                                 v->scll = l;
 620                                                 v->sclh = h;
 621                                                 sol_found = true;
 622                                                 memcpy(s, v, sizeof(*s));
 623                                         }
 624                                 }
 625                         }
 626                 }
 627         }
 628
 629         if (!sol_found) {
 630                 pr_err("%s: no solution at all\n", __func__);
 631                 ret = -EPERM;
 632         }
 633
 634         return ret;
 635 }
 636
 637 static const struct stm32_i2c_spec *get_specs(u32 rate)
 638 {
 639         unsigned int i;
 640
 641         for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
 642                 if (rate <= i2c_specs[i].rate)
 643                         return &i2c_specs[i];
 644
 645         /* NOT REACHED */
 646         return ERR_PTR(-EINVAL);
 647 }
 648
 649 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 650                                     struct stm32_i2c_setup *setup,
 651                                     struct stm32_i2c_timings *output)
 652 {
 653         const struct stm32_i2c_spec *specs;
 654         struct stm32_i2c_timings *v, *_v;
 655         struct list_head solutions;
 656         int ret;
 657
 658         specs = get_specs(setup->speed_freq);
 659         if (specs == ERR_PTR(-EINVAL)) {
 660                 pr_err("%s: speed out of bound {%d}\n", __func__,
 661                        setup->speed_freq);
 662                 return -EINVAL;
 663         }
 664
 665         if (setup->rise_time > specs->rise_max ||
 666             setup->fall_time > specs->fall_max) {
 667                 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 668                        __func__,
 669                        setup->rise_time, specs->rise_max,
 670                        setup->fall_time, specs->fall_max);
 671                 return -EINVAL;
 672         }
 673
 674         if (setup->dnf > STM32_I2C_DNF_MAX) {
 675                 pr_err("%s: DNF out of bound %d/%d\n", __func__,
 676                        setup->dnf, STM32_I2C_DNF_MAX);
 677                 return -EINVAL;
 678         }
 679
 680         INIT_LIST_HEAD(&solutions);
 681         ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
 682         if (ret)
 683                 goto exit;
 684
 685         ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
 686         if (ret)
 687                 goto exit;
 688
 689         debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 690               __func__, output->presc,
 691               output->scldel, output->sdadel,
 692               output->scll, output->sclh);
 693
 694 exit:
 695         /* Release list and memory */
 696         list_for_each_entry_safe(v, _v, &solutions, node) {
 697                 list_del(&v->node);
 698                 free(v);
 699         }
 700
 701         return ret;
 702 }
 703
 704 static u32 get_lower_rate(u32 rate)
 705 {
 706         int i;
 707
 708         for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
 709                 if (rate > i2c_specs[i].rate)
 710                         return i2c_specs[i].rate;
 711
 712         return i2c_specs[0].rate;
 713 }
 714
 715 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 716                                   struct stm32_i2c_timings *timing)
 717 {
 718         struct stm32_i2c_setup *setup = i2c_priv->setup;
 719         int ret = 0;
 720
 721         setup->speed_freq = i2c_priv->speed;
 722         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 723
 724         if (!setup->clock_src) {
 725                 pr_err("%s: clock rate is 0\n", __func__);
 726                 return -EINVAL;
 727         }
 728
 729         do {
 730                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 731                 if (ret) {
 732                         debug("%s: failed to compute I2C timings.\n",
 733                               __func__);
 734                         if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
 735                                 setup->speed_freq =
 736                                         get_lower_rate(setup->speed_freq);
 737                                 debug("%s: downgrade I2C Speed Freq to (%i)\n",
 738                                       __func__, setup->speed_freq);
 739                         } else {
 740                                 break;
 741                         }
 742                 }
 743         } while (ret);
 744
 745         if (ret) {
 746                 pr_err("%s: impossible to compute I2C timings.\n", __func__);
 747                 return ret;
 748         }
 749
 750         debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
 751               setup->speed_freq, setup->clock_src);
 752         debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
 753               setup->rise_time, setup->fall_time);
 754         debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
 755               setup->analog_filter ? "On" : "Off", setup->dnf);
 756
 757         i2c_priv->speed = setup->speed_freq;
 758
 759         return 0;
 760 }
 761
 762 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 763 {
 764         struct stm32_i2c_regs *regs = i2c_priv->regs;
 765         struct stm32_i2c_timings t;
 766         int ret;
 767         u32 timing = 0;
 768
 769         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 770         if (ret)
 771                 return ret;
 772
 773         /* Disable I2C */
 774         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 775
 776         /* Timing settings */
 777         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 778         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 779         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 780         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 781         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 782         writel(timing, &regs->timingr);
 783
 784         /* Enable I2C */
 785         if (i2c_priv->setup->analog_filter)
 786                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 787         else
 788                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 789         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 790
 791         return 0;
 792 }
 793
 794 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 795 {
 796         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 797
 798         if (speed > I2C_SPEED_FAST_PLUS_RATE) {
 799                 debug("%s: Speed %d not supported\n", __func__, speed);
 800                 return -EINVAL;
 801         }
 802
 803         i2c_priv->speed = speed;
 804
 805         return stm32_i2c_hw_config(i2c_priv);
 806 }
 807
 808 static int stm32_i2c_probe(struct udevice *dev)
 809 {
 810         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 811         struct reset_ctl reset_ctl;
 812         fdt_addr_t addr;
 813         int ret;
 814
 815         addr = dev_read_addr(dev);
 816         if (addr == FDT_ADDR_T_NONE)
 817                 return -EINVAL;
 818
 819         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 820
 821         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 822         if (ret)
 823                 return ret;
 824
 825         ret = clk_enable(&i2c_priv->clk);
 826         if (ret)
 827                 goto clk_free;
 828
 829         ret = reset_get_by_index(dev, 0, &reset_ctl);
 830         if (ret)
 831                 goto clk_disable;
 832
 833         reset_assert(&reset_ctl);
 834         udelay(2);
 835         reset_deassert(&reset_ctl);
 836
 837         return 0;
 838
 839 clk_disable:
 840         clk_disable(&i2c_priv->clk);
 841 clk_free:
 842         clk_free(&i2c_priv->clk);
 843
 844         return ret;
 845 }
 846
 847 static int stm32_ofdata_to_platdata(struct udevice *dev)
 848 {
 849         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 850         u32 rise_time, fall_time;
 851
 852         i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
 853         if (!i2c_priv->setup)
 854                 return -EINVAL;
 855
 856         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
 857         if (rise_time)
 858                 i2c_priv->setup->rise_time = rise_time;
 859
 860         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
 861         if (fall_time)
 862                 i2c_priv->setup->fall_time = fall_time;
 863
 864         return 0;
 865 }
 866
 867 static const struct dm_i2c_ops stm32_i2c_ops = {
 868         .xfer = stm32_i2c_xfer,
 869         .set_bus_speed = stm32_i2c_set_bus_speed,
 870 };
 871
 872 static const struct udevice_id stm32_i2c_of_match[] = {
 873         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
 874         {}
 875 };
 876
 877 U_BOOT_DRIVER(stm32f7_i2c) = {
 878         .name = "stm32f7-i2c",
 879         .id = UCLASS_I2C,
 880         .of_match = stm32_i2c_of_match,
 881         .ofdata_to_platdata = stm32_ofdata_to_platdata,
 882         .probe = stm32_i2c_probe,
 883         .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
 884         .ops = &stm32_i2c_ops,
 885 };