drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <log.h>
  11 #include <reset.h>
  12 #include <linux/delay.h>
  13
  14 #include <dm/device.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17
  18 /* STM32 I2C registers */
  19 struct stm32_i2c_regs {
  20         u32 cr1;        /* I2C control register 1 */
  21         u32 cr2;        /* I2C control register 2 */
  22         u32 oar1;       /* I2C own address 1 register */
  23         u32 oar2;       /* I2C own address 2 register */
  24         u32 timingr;    /* I2C timing register */
  25         u32 timeoutr;   /* I2C timeout register */
  26         u32 isr;        /* I2C interrupt and status register */
  27         u32 icr;        /* I2C interrupt clear register */
  28         u32 pecr;       /* I2C packet error checking register */
  29         u32 rxdr;       /* I2C receive data register */
  30         u32 txdr;       /* I2C transmit data register */
  31 };
  32
  33 #define STM32_I2C_CR1                           0x00
  34 #define STM32_I2C_CR2                           0x04
  35 #define STM32_I2C_TIMINGR                       0x10
  36 #define STM32_I2C_ISR                           0x18
  37 #define STM32_I2C_ICR                           0x1C
  38 #define STM32_I2C_RXDR                          0x24
  39 #define STM32_I2C_TXDR                          0x28
  40
  41 /* STM32 I2C control 1 */
  42 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  43 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  44 #define STM32_I2C_CR1_TCIE                      BIT(6)
  45 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  46 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  47 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  48 #define STM32_I2C_CR1_RXIE                      BIT(2)
  49 #define STM32_I2C_CR1_TXIE                      BIT(1)
  50 #define STM32_I2C_CR1_PE                        BIT(0)
  51
  52 /* STM32 I2C control 2 */
  53 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  54 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  55 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  56 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  57 #define STM32_I2C_CR2_NACK                      BIT(15)
  58 #define STM32_I2C_CR2_STOP                      BIT(14)
  59 #define STM32_I2C_CR2_START                     BIT(13)
  60 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  61 #define STM32_I2C_CR2_ADD10                     BIT(11)
  62 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  63 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  64 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  65 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  66 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  67 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  68                                                 | STM32_I2C_CR2_NBYTES_MASK \
  69                                                 | STM32_I2C_CR2_SADD7_MASK \
  70                                                 | STM32_I2C_CR2_RELOAD \
  71                                                 | STM32_I2C_CR2_RD_WRN)
  72
  73 /* STM32 I2C Interrupt Status */
  74 #define STM32_I2C_ISR_BUSY                      BIT(15)
  75 #define STM32_I2C_ISR_ARLO                      BIT(9)
  76 #define STM32_I2C_ISR_BERR                      BIT(8)
  77 #define STM32_I2C_ISR_TCR                       BIT(7)
  78 #define STM32_I2C_ISR_TC                        BIT(6)
  79 #define STM32_I2C_ISR_STOPF                     BIT(5)
  80 #define STM32_I2C_ISR_NACKF                     BIT(4)
  81 #define STM32_I2C_ISR_ADDR                      BIT(3)
  82 #define STM32_I2C_ISR_RXNE                      BIT(2)
  83 #define STM32_I2C_ISR_TXIS                      BIT(1)
  84 #define STM32_I2C_ISR_TXE                       BIT(0)
  85 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  86                                                 | STM32_I2C_ISR_ARLO)
  87
  88 /* STM32 I2C Interrupt Clear */
  89 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  90 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  91 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  92 #define STM32_I2C_ICR_NACKCF                    BIT(4)
  93
  94 /* STM32 I2C Timing */
  95 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
  96 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
  97 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
  98 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
  99 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
 100
 101 #define STM32_I2C_MAX_LEN                       0xff
 102
 103 #define STM32_I2C_DNF_DEFAULT                   0
 104 #define STM32_I2C_DNF_MAX                       16
 105
 106 #define STM32_I2C_ANALOG_FILTER_ENABLE  1
 107 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 108 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 109
 110 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 111 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 112
 113 #define STM32_PRESC_MAX                         BIT(4)
 114 #define STM32_SCLDEL_MAX                        BIT(4)
 115 #define STM32_SDADEL_MAX                        BIT(4)
 116 #define STM32_SCLH_MAX                          BIT(8)
 117 #define STM32_SCLL_MAX                          BIT(8)
 118
 119 #define STM32_NSEC_PER_SEC                      1000000000L
 120
 121 /**
 122  * struct stm32_i2c_spec - private i2c specification timing
 123  * @rate: I2C bus speed (Hz)
 124  * @rate_min: 80% of I2C bus speed (Hz)
 125  * @rate_max: 120% of I2C bus speed (Hz)
 126  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 127  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 128  * @hddat_min: Min data hold time (ns)
 129  * @vddat_max: Max data valid time (ns)
 130  * @sudat_min: Min data setup time (ns)
 131  * @l_min: Min low period of the SCL clock (ns)
 132  * @h_min: Min high period of the SCL clock (ns)
 133  */
 134
 135 struct stm32_i2c_spec {
 136         u32 rate;
 137         u32 rate_min;
 138         u32 rate_max;
 139         u32 fall_max;
 140         u32 rise_max;
 141         u32 hddat_min;
 142         u32 vddat_max;
 143         u32 sudat_min;
 144         u32 l_min;
 145         u32 h_min;
 146 };
 147
 148 /**
 149  * struct stm32_i2c_setup - private I2C timing setup parameters
 150  * @speed_freq: I2C speed frequency  (Hz)
 151  * @clock_src: I2C clock source frequency (Hz)
 152  * @rise_time: Rise time (ns)
 153  * @fall_time: Fall time (ns)
 154  * @dnf: Digital filter coefficient (0-16)
 155  * @analog_filter: Analog filter delay (On/Off)
 156  */
 157 struct stm32_i2c_setup {
 158         u32 speed_freq;
 159         u32 clock_src;
 160         u32 rise_time;
 161         u32 fall_time;
 162         u8 dnf;
 163         bool analog_filter;
 164 };
 165
 166 /**
 167  * struct stm32_i2c_timings - private I2C output parameters
 168  * @prec: Prescaler value
 169  * @scldel: Data setup time
 170  * @sdadel: Data hold time
 171  * @sclh: SCL high period (master mode)
 172  * @sclh: SCL low period (master mode)
 173  */
 174 struct stm32_i2c_timings {
 175         struct list_head node;
 176         u8 presc;
 177         u8 scldel;
 178         u8 sdadel;
 179         u8 sclh;
 180         u8 scll;
 181 };
 182
 183 struct stm32_i2c_priv {
 184         struct stm32_i2c_regs *regs;
 185         struct clk clk;
 186         struct stm32_i2c_setup *setup;
 187         u32 speed;
 188 };
 189
 190 static const struct stm32_i2c_spec i2c_specs[] = {
 191         /* Standard speed - 100 KHz */
 192         [IC_SPEED_MODE_STANDARD] = {
 193                 .rate = I2C_SPEED_STANDARD_RATE,
 194                 .rate_min = 8000,
 195                 .rate_max = 120000,
 196                 .fall_max = 300,
 197                 .rise_max = 1000,
 198                 .hddat_min = 0,
 199                 .vddat_max = 3450,
 200                 .sudat_min = 250,
 201                 .l_min = 4700,
 202                 .h_min = 4000,
 203         },
 204         /* Fast speed - 400 KHz */
 205         [IC_SPEED_MODE_FAST] = {
 206                 .rate = I2C_SPEED_FAST_RATE,
 207                 .rate_min = 320000,
 208                 .rate_max = 480000,
 209                 .fall_max = 300,
 210                 .rise_max = 300,
 211                 .hddat_min = 0,
 212                 .vddat_max = 900,
 213                 .sudat_min = 100,
 214                 .l_min = 1300,
 215                 .h_min = 600,
 216         },
 217         /* Fast Plus Speed - 1 MHz */
 218         [IC_SPEED_MODE_FAST_PLUS] = {
 219                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 220                 .rate_min = 800000,
 221                 .rate_max = 1200000,
 222                 .fall_max = 100,
 223                 .rise_max = 120,
 224                 .hddat_min = 0,
 225                 .vddat_max = 450,
 226                 .sudat_min = 50,
 227                 .l_min = 500,
 228                 .h_min = 260,
 229         },
 230 };
 231
 232 static const struct stm32_i2c_setup stm32f7_setup = {
 233         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 234         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 235         .dnf = STM32_I2C_DNF_DEFAULT,
 236         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 237 };
 238
 239 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 240 {
 241         struct stm32_i2c_regs *regs = i2c_priv->regs;
 242         u32 status = readl(&regs->isr);
 243
 244         if (status & STM32_I2C_ISR_BUSY)
 245                 return -EBUSY;
 246
 247         return 0;
 248 }
 249
 250 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 251                                     struct i2c_msg *msg, bool stop)
 252 {
 253         struct stm32_i2c_regs *regs = i2c_priv->regs;
 254         u32 cr2 = readl(&regs->cr2);
 255
 256         /* Set transfer direction */
 257         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 258         if (msg->flags & I2C_M_RD)
 259                 cr2 |= STM32_I2C_CR2_RD_WRN;
 260
 261         /* Set slave address */
 262         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 263         if (msg->flags & I2C_M_TEN) {
 264                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 265                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 266                 cr2 |= STM32_I2C_CR2_ADD10;
 267         } else {
 268                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 269                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 270         }
 271
 272         /* Set nb bytes to transfer and reload or autoend bits */
 273         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 274                  STM32_I2C_CR2_AUTOEND);
 275         if (msg->len > STM32_I2C_MAX_LEN) {
 276                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 277                 cr2 |= STM32_I2C_CR2_RELOAD;
 278         } else {
 279                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 280         }
 281
 282         /* Write configurations register */
 283         writel(cr2, &regs->cr2);
 284
 285         /* START/ReSTART generation */
 286         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 287 }
 288
 289 /*
 290  * RELOAD mode must be selected if total number of data bytes to be
 291  * sent is greater than MAX_LEN
 292  */
 293
 294 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 295                                     struct i2c_msg *msg, bool stop)
 296 {
 297         struct stm32_i2c_regs *regs = i2c_priv->regs;
 298         u32 cr2 = readl(&regs->cr2);
 299
 300         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 301
 302         if (msg->len > STM32_I2C_MAX_LEN) {
 303                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 304         } else {
 305                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 306                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 307         }
 308
 309         writel(cr2, &regs->cr2);
 310 }
 311
 312 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 313                                 u32 flags, u32 *status)
 314 {
 315         struct stm32_i2c_regs *regs = i2c_priv->regs;
 316         u32 time_start = get_timer(0);
 317
 318         *status = readl(&regs->isr);
 319         while (!(*status & flags)) {
 320                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 321                         debug("%s: i2c timeout\n", __func__);
 322                         return -ETIMEDOUT;
 323                 }
 324
 325                 *status = readl(&regs->isr);
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 332 {
 333         struct stm32_i2c_regs *regs = i2c_priv->regs;
 334         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 335                    STM32_I2C_ISR_STOPF;
 336         u32 status;
 337         int ret;
 338
 339         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 340         if (ret)
 341                 return ret;
 342
 343         if (status & STM32_I2C_ISR_BERR) {
 344                 debug("%s: Bus error\n", __func__);
 345
 346                 /* Clear BERR flag */
 347                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 348
 349                 return -EIO;
 350         }
 351
 352         if (status & STM32_I2C_ISR_ARLO) {
 353                 debug("%s: Arbitration lost\n", __func__);
 354
 355                 /* Clear ARLO flag */
 356                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 357
 358                 return -EAGAIN;
 359         }
 360
 361         if (status & STM32_I2C_ISR_NACKF) {
 362                 debug("%s: Receive NACK\n", __func__);
 363
 364                 /* Clear NACK flag */
 365                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 366
 367                 /* Wait until STOPF flag is set */
 368                 mask = STM32_I2C_ISR_STOPF;
 369                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 370                 if (ret)
 371                         return ret;
 372
 373                 ret = -EIO;
 374         }
 375
 376         if (status & STM32_I2C_ISR_STOPF) {
 377                 /* Clear STOP flag */
 378                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 379
 380                 /* Clear control register 2 */
 381                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 382         }
 383
 384         return ret;
 385 }
 386
 387 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 388                                   struct i2c_msg *msg, bool stop)
 389 {
 390         struct stm32_i2c_regs *regs = i2c_priv->regs;
 391         u32 status;
 392         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 393                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 394         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 395                           STM32_I2C_MAX_LEN : msg->len;
 396         int ret = 0;
 397
 398         /* Add errors */
 399         mask |= STM32_I2C_ISR_ERRORS;
 400
 401         stm32_i2c_message_start(i2c_priv, msg, stop);
 402
 403         while (msg->len) {
 404                 /*
 405                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 406                  * RXNE/BERR/ARLO flags are set
 407                  */
 408                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 409                 if (ret)
 410                         break;
 411
 412                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 413                         break;
 414
 415                 if (status & STM32_I2C_ISR_RXNE) {
 416                         *msg->buf++ = readb(&regs->rxdr);
 417                         msg->len--;
 418                         bytes_to_rw--;
 419                 }
 420
 421                 if (status & STM32_I2C_ISR_TXIS) {
 422                         writeb(*msg->buf++, &regs->txdr);
 423                         msg->len--;
 424                         bytes_to_rw--;
 425                 }
 426
 427                 if (!bytes_to_rw && msg->len) {
 428                         /* Wait until TCR flag is set */
 429                         mask = STM32_I2C_ISR_TCR;
 430                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 431                         if (ret)
 432                                 break;
 433
 434                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 435                                       STM32_I2C_MAX_LEN : msg->len;
 436                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 437                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 438
 439                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 440                 } else if (!bytes_to_rw) {
 441                         /* Wait until TC flag is set */
 442                         mask = STM32_I2C_ISR_TC;
 443                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 444                         if (ret)
 445                                 break;
 446
 447                         if (!stop)
 448                                 /* Message sent, new message has to be sent */
 449                                 return 0;
 450                 }
 451         }
 452
 453         /* End of transfer, send stop condition */
 454         mask = STM32_I2C_CR2_STOP;
 455         setbits_le32(&regs->cr2, mask);
 456
 457         return stm32_i2c_check_end_of_message(i2c_priv);
 458 }
 459
 460 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 461                           int nmsgs)
 462 {
 463         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 464         int ret;
 465
 466         ret = stm32_i2c_check_device_busy(i2c_priv);
 467         if (ret)
 468                 return ret;
 469
 470         for (; nmsgs > 0; nmsgs--, msg++) {
 471                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 472                 if (ret)
 473                         return ret;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 480                                        const struct stm32_i2c_spec *specs,
 481                                        struct list_head *solutions)
 482 {
 483         struct stm32_i2c_timings *v;
 484         u32 p_prev = STM32_PRESC_MAX;
 485         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 486                                        setup->clock_src);
 487         u32 af_delay_min, af_delay_max;
 488         u16 p, l, a;
 489         int sdadel_min, sdadel_max, scldel_min;
 490         int ret = 0;
 491
 492         af_delay_min = setup->analog_filter ?
 493                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 494         af_delay_max = setup->analog_filter ?
 495                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 496
 497         sdadel_min = specs->hddat_min + setup->fall_time -
 498                      af_delay_min - (setup->dnf + 3) * i2cclk;
 499
 500         sdadel_max = specs->vddat_max - setup->rise_time -
 501                      af_delay_max - (setup->dnf + 4) * i2cclk;
 502
 503         scldel_min = setup->rise_time + specs->sudat_min;
 504
 505         if (sdadel_min < 0)
 506                 sdadel_min = 0;
 507         if (sdadel_max < 0)
 508                 sdadel_max = 0;
 509
 510         debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
 511               sdadel_min, sdadel_max, scldel_min);
 512
 513         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 514         for (p = 0; p < STM32_PRESC_MAX; p++) {
 515                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 516                         int scldel = (l + 1) * (p + 1) * i2cclk;
 517
 518                         if (scldel < scldel_min)
 519                                 continue;
 520
 521                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 522                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 523
 524                                 if (((sdadel >= sdadel_min) &&
 525                                      (sdadel <= sdadel_max)) &&
 526                                     (p != p_prev)) {
 527                                         v = calloc(1, sizeof(*v));
 528                                         if (!v)
 529                                                 return -ENOMEM;
 530
 531                                         v->presc = p;
 532                                         v->scldel = l;
 533                                         v->sdadel = a;
 534                                         p_prev = p;
 535
 536                                         list_add_tail(&v->node, solutions);
 537                                         break;
 538                                 }
 539                         }
 540
 541                         if (p_prev == p)
 542                                 break;
 543                 }
 544         }
 545
 546         if (list_empty(solutions)) {
 547                 pr_err("%s: no Prescaler solution\n", __func__);
 548                 ret = -EPERM;
 549         }
 550
 551         return ret;
 552 }
 553
 554 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 555                                      const struct stm32_i2c_spec *specs,
 556                                      struct list_head *solutions,
 557                                      struct stm32_i2c_timings *s)
 558 {
 559         struct stm32_i2c_timings *v;
 560         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 561                                        setup->speed_freq);
 562         u32 clk_error_prev = i2cbus;
 563         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 564                                        setup->clock_src);
 565         u32 clk_min, clk_max;
 566         u32 af_delay_min;
 567         u32 dnf_delay;
 568         u32 tsync;
 569         u16 l, h;
 570         bool sol_found = false;
 571         int ret = 0;
 572
 573         af_delay_min = setup->analog_filter ?
 574                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 575         dnf_delay = setup->dnf * i2cclk;
 576
 577         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 578         clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
 579         clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
 580
 581         /*
 582          * Among Prescaler possibilities discovered above figures out SCL Low
 583          * and High Period. Provided:
 584          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 585          *   defined by I2C Specification. I2C Clock has to be lower than
 586          *   (SCL Low Period - Analog/Digital filters) / 4.
 587          * - SCL High Period has to be lower than High Period of the SCL Clock
 588          *   defined by I2C Specification
 589          * - I2C Clock has to be lower than SCL High Period
 590          */
 591         list_for_each_entry(v, solutions, node) {
 592                 u32 prescaler = (v->presc + 1) * i2cclk;
 593
 594                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 595                         u32 tscl_l = (l + 1) * prescaler + tsync;
 596
 597                         if (tscl_l < specs->l_min ||
 598                             (i2cclk >=
 599                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 600                                 continue;
 601                         }
 602
 603                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 604                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 605                                 u32 tscl = tscl_l + tscl_h +
 606                                            setup->rise_time + setup->fall_time;
 607
 608                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 609                                     (tscl_h >= specs->h_min) &&
 610                                     (i2cclk < tscl_h)) {
 611                                         u32 clk_error;
 612
 613                                         if (tscl > i2cbus)
 614                                                 clk_error = tscl - i2cbus;
 615                                         else
 616                                                 clk_error = i2cbus - tscl;
 617
 618                                         if (clk_error < clk_error_prev) {
 619                                                 clk_error_prev = clk_error;
 620                                                 v->scll = l;
 621                                                 v->sclh = h;
 622                                                 sol_found = true;
 623                                                 memcpy(s, v, sizeof(*s));
 624                                         }
 625                                 }
 626                         }
 627                 }
 628         }
 629
 630         if (!sol_found) {
 631                 pr_err("%s: no solution at all\n", __func__);
 632                 ret = -EPERM;
 633         }
 634
 635         return ret;
 636 }
 637
 638 static const struct stm32_i2c_spec *get_specs(u32 rate)
 639 {
 640         unsigned int i;
 641
 642         for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
 643                 if (rate <= i2c_specs[i].rate)
 644                         return &i2c_specs[i];
 645
 646         /* NOT REACHED */
 647         return ERR_PTR(-EINVAL);
 648 }
 649
 650 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 651                                     struct stm32_i2c_setup *setup,
 652                                     struct stm32_i2c_timings *output)
 653 {
 654         const struct stm32_i2c_spec *specs;
 655         struct stm32_i2c_timings *v, *_v;
 656         struct list_head solutions;
 657         int ret;
 658
 659         specs = get_specs(setup->speed_freq);
 660         if (specs == ERR_PTR(-EINVAL)) {
 661                 pr_err("%s: speed out of bound {%d}\n", __func__,
 662                        setup->speed_freq);
 663                 return -EINVAL;
 664         }
 665
 666         if (setup->rise_time > specs->rise_max ||
 667             setup->fall_time > specs->fall_max) {
 668                 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 669                        __func__,
 670                        setup->rise_time, specs->rise_max,
 671                        setup->fall_time, specs->fall_max);
 672                 return -EINVAL;
 673         }
 674
 675         if (setup->dnf > STM32_I2C_DNF_MAX) {
 676                 pr_err("%s: DNF out of bound %d/%d\n", __func__,
 677                        setup->dnf, STM32_I2C_DNF_MAX);
 678                 return -EINVAL;
 679         }
 680
 681         INIT_LIST_HEAD(&solutions);
 682         ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
 683         if (ret)
 684                 goto exit;
 685
 686         ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
 687         if (ret)
 688                 goto exit;
 689
 690         debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 691               __func__, output->presc,
 692               output->scldel, output->sdadel,
 693               output->scll, output->sclh);
 694
 695 exit:
 696         /* Release list and memory */
 697         list_for_each_entry_safe(v, _v, &solutions, node) {
 698                 list_del(&v->node);
 699                 free(v);
 700         }
 701
 702         return ret;
 703 }
 704
 705 static u32 get_lower_rate(u32 rate)
 706 {
 707         int i;
 708
 709         for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
 710                 if (rate > i2c_specs[i].rate)
 711                         return i2c_specs[i].rate;
 712
 713         return i2c_specs[0].rate;
 714 }
 715
 716 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 717                                   struct stm32_i2c_timings *timing)
 718 {
 719         struct stm32_i2c_setup *setup = i2c_priv->setup;
 720         int ret = 0;
 721
 722         setup->speed_freq = i2c_priv->speed;
 723         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 724
 725         if (!setup->clock_src) {
 726                 pr_err("%s: clock rate is 0\n", __func__);
 727                 return -EINVAL;
 728         }
 729
 730         do {
 731                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 732                 if (ret) {
 733                         debug("%s: failed to compute I2C timings.\n",
 734                               __func__);
 735                         if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
 736                                 setup->speed_freq =
 737                                         get_lower_rate(setup->speed_freq);
 738                                 debug("%s: downgrade I2C Speed Freq to (%i)\n",
 739                                       __func__, setup->speed_freq);
 740                         } else {
 741                                 break;
 742                         }
 743                 }
 744         } while (ret);
 745
 746         if (ret) {
 747                 pr_err("%s: impossible to compute I2C timings.\n", __func__);
 748                 return ret;
 749         }
 750
 751         debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
 752               setup->speed_freq, setup->clock_src);
 753         debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
 754               setup->rise_time, setup->fall_time);
 755         debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
 756               setup->analog_filter ? "On" : "Off", setup->dnf);
 757
 758         i2c_priv->speed = setup->speed_freq;
 759
 760         return 0;
 761 }
 762
 763 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 764 {
 765         struct stm32_i2c_regs *regs = i2c_priv->regs;
 766         struct stm32_i2c_timings t;
 767         int ret;
 768         u32 timing = 0;
 769
 770         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 771         if (ret)
 772                 return ret;
 773
 774         /* Disable I2C */
 775         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 776
 777         /* Timing settings */
 778         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 779         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 780         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 781         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 782         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 783         writel(timing, &regs->timingr);
 784
 785         /* Enable I2C */
 786         if (i2c_priv->setup->analog_filter)
 787                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 788         else
 789                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 790         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 791
 792         return 0;
 793 }
 794
 795 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 796 {
 797         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 798
 799         if (speed > I2C_SPEED_FAST_PLUS_RATE) {
 800                 debug("%s: Speed %d not supported\n", __func__, speed);
 801                 return -EINVAL;
 802         }
 803
 804         i2c_priv->speed = speed;
 805
 806         return stm32_i2c_hw_config(i2c_priv);
 807 }
 808
 809 static int stm32_i2c_probe(struct udevice *dev)
 810 {
 811         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 812         struct reset_ctl reset_ctl;
 813         fdt_addr_t addr;
 814         int ret;
 815
 816         addr = dev_read_addr(dev);
 817         if (addr == FDT_ADDR_T_NONE)
 818                 return -EINVAL;
 819
 820         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 821
 822         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 823         if (ret)
 824                 return ret;
 825
 826         ret = clk_enable(&i2c_priv->clk);
 827         if (ret)
 828                 goto clk_free;
 829
 830         ret = reset_get_by_index(dev, 0, &reset_ctl);
 831         if (ret)
 832                 goto clk_disable;
 833
 834         reset_assert(&reset_ctl);
 835         udelay(2);
 836         reset_deassert(&reset_ctl);
 837
 838         return 0;
 839
 840 clk_disable:
 841         clk_disable(&i2c_priv->clk);
 842 clk_free:
 843         clk_free(&i2c_priv->clk);
 844
 845         return ret;
 846 }
 847
 848 static int stm32_ofdata_to_platdata(struct udevice *dev)
 849 {
 850         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 851         u32 rise_time, fall_time;
 852
 853         i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
 854         if (!i2c_priv->setup)
 855                 return -EINVAL;
 856
 857         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
 858         if (rise_time)
 859                 i2c_priv->setup->rise_time = rise_time;
 860
 861         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
 862         if (fall_time)
 863                 i2c_priv->setup->fall_time = fall_time;
 864
 865         return 0;
 866 }
 867
 868 static const struct dm_i2c_ops stm32_i2c_ops = {
 869         .xfer = stm32_i2c_xfer,
 870         .set_bus_speed = stm32_i2c_set_bus_speed,
 871 };
 872
 873 static const struct udevice_id stm32_i2c_of_match[] = {
 874         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
 875         {}
 876 };
 877
 878 U_BOOT_DRIVER(stm32f7_i2c) = {
 879         .name = "stm32f7-i2c",
 880         .id = UCLASS_I2C,
 881         .of_match = stm32_i2c_of_match,
 882         .ofdata_to_platdata = stm32_ofdata_to_platdata,
 883         .probe = stm32_i2c_probe,
 884         .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
 885         .ops = &stm32_i2c_ops,
 886 };