drivers/i2c/sh_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011, 2013 Renesas Solutions Corp.
   4  * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   5  *
   6  * NOTE: This driver should be converted to driver model before June 2017.
   7  * Please see doc/driver-model/i2c-howto.rst for instructions.
   8  */
   9
  10 #include <common.h>
  11 #include <i2c.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 /* Every register is 32bit aligned, but only 8bits in size */
  18 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
  19 struct sh_i2c {
  20         ureg(icdr);
  21         ureg(iccr);
  22         ureg(icsr);
  23         ureg(icic);
  24         ureg(iccl);
  25         ureg(icch);
  26 };
  27 #undef ureg
  28
  29 /* ICCR */
  30 #define SH_I2C_ICCR_ICE         (1 << 7)
  31 #define SH_I2C_ICCR_RACK        (1 << 6)
  32 #define SH_I2C_ICCR_RTS         (1 << 4)
  33 #define SH_I2C_ICCR_BUSY        (1 << 2)
  34 #define SH_I2C_ICCR_SCP         (1 << 0)
  35
  36 /* ICSR / ICIC */
  37 #define SH_IC_BUSY      (1 << 4)
  38 #define SH_IC_TACK      (1 << 2)
  39 #define SH_IC_WAIT      (1 << 1)
  40 #define SH_IC_DTE       (1 << 0)
  41
  42 #ifdef CONFIG_SH_I2C_8BIT
  43 /* store 8th bit of iccl and icch in ICIC register */
  44 #define SH_I2C_ICIC_ICCLB8      (1 << 7)
  45 #define SH_I2C_ICIC_ICCHB8      (1 << 6)
  46 #endif
  47
  48 static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
  49         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
  50 #ifdef CONFIG_SYS_I2C_SH_BASE1
  51         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
  52 #endif
  53 #ifdef CONFIG_SYS_I2C_SH_BASE2
  54         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
  55 #endif
  56 #ifdef CONFIG_SYS_I2C_SH_BASE3
  57         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
  58 #endif
  59 #ifdef CONFIG_SYS_I2C_SH_BASE4
  60         (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
  61 #endif
  62 };
  63
  64 static u16 iccl, icch;
  65
  66 #define IRQ_WAIT 1000
  67
  68 static void sh_irq_dte(struct sh_i2c *dev)
  69 {
  70         int i;
  71
  72         for (i = 0; i < IRQ_WAIT; i++) {
  73                 if (SH_IC_DTE & readb(&dev->icsr))
  74                         break;
  75                 udelay(10);
  76         }
  77 }
  78
  79 static int sh_irq_dte_with_tack(struct sh_i2c *dev)
  80 {
  81         int i;
  82
  83         for (i = 0; i < IRQ_WAIT; i++) {
  84                 if (SH_IC_DTE & readb(&dev->icsr))
  85                         break;
  86                 if (SH_IC_TACK & readb(&dev->icsr))
  87                         return -1;
  88                 udelay(10);
  89         }
  90         return 0;
  91 }
  92
  93 static void sh_irq_busy(struct sh_i2c *dev)
  94 {
  95         int i;
  96
  97         for (i = 0; i < IRQ_WAIT; i++) {
  98                 if (!(SH_IC_BUSY & readb(&dev->icsr)))
  99                         break;
 100                 udelay(10);
 101         }
 102 }
 103
 104 static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
 105 {
 106         u8 icic = SH_IC_TACK;
 107
 108         debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
 109                                 __func__, chip, addr, iccl, icch);
 110         clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 111         setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 112
 113         writeb(iccl & 0xff, &dev->iccl);
 114         writeb(icch & 0xff, &dev->icch);
 115 #ifdef CONFIG_SH_I2C_8BIT
 116         if (iccl > 0xff)
 117                 icic |= SH_I2C_ICIC_ICCLB8;
 118         if (icch > 0xff)
 119                 icic |= SH_I2C_ICIC_ICCHB8;
 120 #endif
 121         writeb(icic, &dev->icic);
 122
 123         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
 124         sh_irq_dte(dev);
 125
 126         clrbits_8(&dev->icsr, SH_IC_TACK);
 127         writeb(chip << 1, &dev->icdr);
 128         if (sh_irq_dte_with_tack(dev) != 0)
 129                 return -1;
 130
 131         writeb(addr, &dev->icdr);
 132         if (stop)
 133                 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
 134
 135         if (sh_irq_dte_with_tack(dev) != 0)
 136                 return -1;
 137         return 0;
 138 }
 139
 140 static void sh_i2c_finish(struct sh_i2c *dev)
 141 {
 142         writeb(0, &dev->icsr);
 143         clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 144 }
 145
 146 static int
 147 sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
 148 {
 149         int ret = -1;
 150         if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
 151                 goto exit0;
 152         udelay(10);
 153
 154         writeb(val, &dev->icdr);
 155         if (sh_irq_dte_with_tack(dev) != 0)
 156                 goto exit0;
 157
 158         writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
 159         if (sh_irq_dte_with_tack(dev) != 0)
 160                 goto exit0;
 161         sh_irq_busy(dev);
 162         ret = 0;
 163
 164 exit0:
 165         sh_i2c_finish(dev);
 166         return ret;
 167 }
 168
 169 static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
 170 {
 171         int ret = -1;
 172
 173 #if defined(CONFIG_SH73A0)
 174         if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
 175                 goto exit0;
 176 #else
 177         if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
 178                 goto exit0;
 179         udelay(100);
 180 #endif
 181
 182         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
 183         sh_irq_dte(dev);
 184
 185         writeb(chip << 1 | 0x01, &dev->icdr);
 186         if (sh_irq_dte_with_tack(dev) != 0)
 187                 goto exit0;
 188
 189         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
 190         if (sh_irq_dte_with_tack(dev) != 0)
 191                 goto exit0;
 192
 193         ret = readb(&dev->icdr) & 0xff;
 194
 195         writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
 196         readb(&dev->icdr); /* Dummy read */
 197         sh_irq_busy(dev);
 198
 199 exit0:
 200         sh_i2c_finish(dev);
 201
 202         return ret;
 203 }
 204
 205 static void
 206 sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 207 {
 208         int num, denom, tmp;
 209
 210         /* No i2c support prior to relocation */
 211         if (!(gd->flags & GD_FLG_RELOC))
 212                 return;
 213
 214         /*
 215          * Calculate the value for iccl. From the data sheet:
 216          * iccl = (p-clock / transfer-rate) * (L / (L + H))
 217          * where L and H are the SCL low and high ratio.
 218          */
 219         num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
 220         denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
 221         tmp = num * 10 / denom;
 222         if (tmp % 10 >= 5)
 223                 iccl = (u16)((num/denom) + 1);
 224         else
 225                 iccl = (u16)(num/denom);
 226
 227         /* Calculate the value for icch. From the data sheet:
 228            icch = (p clock / transfer rate) * (H / (L + H)) */
 229         num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
 230         tmp = num * 10 / denom;
 231         if (tmp % 10 >= 5)
 232                 icch = (u16)((num/denom) + 1);
 233         else
 234                 icch = (u16)(num/denom);
 235
 236         debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
 237                         CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
 238 }
 239
 240 static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 241                                 uint addr, int alen, u8 *data, int len)
 242 {
 243         int ret, i;
 244         struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 245
 246         for (i = 0; i < len; i++) {
 247                 ret = sh_i2c_raw_read(dev, chip, addr + i);
 248                 if (ret < 0)
 249                         return -1;
 250
 251                 data[i] = ret & 0xff;
 252                 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
 259                                 int alen, u8 *data, int len)
 260 {
 261         struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 262         int i;
 263
 264         for (i = 0; i < len; i++) {
 265                 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
 266                 if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
 267                         return -1;
 268         }
 269         return 0;
 270 }
 271
 272 static int
 273 sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
 274 {
 275         u8 dummy[1];
 276
 277         return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
 278 }
 279
 280 static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
 281                         unsigned int speed)
 282 {
 283         struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 284
 285         sh_i2c_finish(dev);
 286         sh_i2c_init(adap, speed, 0);
 287
 288         return 0;
 289 }
 290
 291 /*
 292  * Register RCAR i2c adapters
 293  */
 294 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 295         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
 296 #ifdef CONFIG_SYS_I2C_SH_BASE1
 297 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 298         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
 299 #endif
 300 #ifdef CONFIG_SYS_I2C_SH_BASE2
 301 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 302         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
 303 #endif
 304 #ifdef CONFIG_SYS_I2C_SH_BASE3
 305 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 306         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
 307 #endif
 308 #ifdef CONFIG_SYS_I2C_SH_BASE4
 309 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 310         sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
 311 #endif