drivers/i2c/rcar_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/i2c/rcar_i2c.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Clock configuration based on Linux i2c-rcar.c:
   8  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
   9  * Copyright (C) 2011-2015 Renesas Electronics Corporation
  10  * Copyright (C) 2012-14 Renesas Solutions Corp.
  11  *   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  12  */
  13
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <dm.h>
  17 #include <i2c.h>
  18 #include <asm/io.h>
  19 #include <wait_bit.h>
  20 #include <dm/device_compat.h>
  21
  22 #define RCAR_I2C_ICSCR                  0x00 /* slave ctrl */
  23 #define RCAR_I2C_ICMCR                  0x04 /* master ctrl */
  24 #define RCAR_I2C_ICMCR_MDBS             BIT(7) /* non-fifo mode switch */
  25 #define RCAR_I2C_ICMCR_FSCL             BIT(6) /* override SCL pin */
  26 #define RCAR_I2C_ICMCR_FSDA             BIT(5) /* override SDA pin */
  27 #define RCAR_I2C_ICMCR_OBPC             BIT(4) /* override pins */
  28 #define RCAR_I2C_ICMCR_MIE              BIT(3) /* master if enable */
  29 #define RCAR_I2C_ICMCR_TSBE             BIT(2)
  30 #define RCAR_I2C_ICMCR_FSB              BIT(1) /* force stop bit */
  31 #define RCAR_I2C_ICMCR_ESG              BIT(0) /* enable start bit gen */
  32 #define RCAR_I2C_ICSSR                  0x08 /* slave status */
  33 #define RCAR_I2C_ICMSR                  0x0c /* master status */
  34 #define RCAR_I2C_ICMSR_MASK             0x7f
  35 #define RCAR_I2C_ICMSR_MNR              BIT(6) /* Nack */
  36 #define RCAR_I2C_ICMSR_MAL              BIT(5) /* Arbitration lost */
  37 #define RCAR_I2C_ICMSR_MST              BIT(4) /* Stop */
  38 #define RCAR_I2C_ICMSR_MDE              BIT(3)
  39 #define RCAR_I2C_ICMSR_MDT              BIT(2)
  40 #define RCAR_I2C_ICMSR_MDR              BIT(1)
  41 #define RCAR_I2C_ICMSR_MAT              BIT(0)
  42 #define RCAR_I2C_ICSIER                 0x10 /* slave irq enable */
  43 #define RCAR_I2C_ICMIER                 0x14 /* master irq enable */
  44 #define RCAR_I2C_ICCCR                  0x18 /* clock dividers */
  45 #define RCAR_I2C_ICCCR_SCGD_OFF         3
  46 #define RCAR_I2C_ICSAR                  0x1c /* slave address */
  47 #define RCAR_I2C_ICMAR                  0x20 /* master address */
  48 #define RCAR_I2C_ICRXD_ICTXD            0x24 /* data port */
  49 /*
  50  * First Bit Setup Cycle (Gen3).
  51  * Defines 1st bit delay between SDA and SCL.
  52  */
  53 #define RCAR_I2C_ICFBSCR                0x38
  54 #define RCAR_I2C_ICFBSCR_TCYC17         0x0f /* 17*Tcyc */
  55
  56
  57 enum rcar_i2c_type {
  58         RCAR_I2C_TYPE_GEN2,
  59         RCAR_I2C_TYPE_GEN3,
  60 };
  61
  62 struct rcar_i2c_priv {
  63         void __iomem            *base;
  64         struct clk              clk;
  65         u32                     intdelay;
  66         u32                     icccr;
  67         enum rcar_i2c_type      type;
  68 };
  69
  70 static int rcar_i2c_finish(struct udevice *dev)
  71 {
  72         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  73         int ret;
  74
  75         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
  76                                 true, 10, true);
  77
  78         writel(0, priv->base + RCAR_I2C_ICSSR);
  79         writel(0, priv->base + RCAR_I2C_ICMSR);
  80         writel(0, priv->base + RCAR_I2C_ICMCR);
  81
  82         return ret;
  83 }
  84
  85 static int rcar_i2c_recover(struct udevice *dev)
  86 {
  87         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  88         u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
  89         u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
  90         int i;
  91         u32 mstat;
  92
  93         /* Send 9 SCL pulses */
  94         for (i = 0; i < 9; i++) {
  95                 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  96                 udelay(5);
  97                 writel(mcra, priv->base + RCAR_I2C_ICMCR);
  98                 udelay(5);
  99         }
 100
 101         /* Send stop condition */
 102         udelay(5);
 103         writel(mcra, priv->base + RCAR_I2C_ICMCR);
 104         udelay(5);
 105         writel(mcr, priv->base + RCAR_I2C_ICMCR);
 106         udelay(5);
 107         writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 108         udelay(5);
 109         writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 110         udelay(5);
 111
 112         mstat = readl(priv->base + RCAR_I2C_ICMSR);
 113         return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
 114 }
 115
 116 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
 117 {
 118         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 119         u32 mask = RCAR_I2C_ICMSR_MAT |
 120                    (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
 121         int ret;
 122
 123         writel(0, priv->base + RCAR_I2C_ICMIER);
 124         writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
 125         writel(0, priv->base + RCAR_I2C_ICMSR);
 126         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 127
 128         /* Wait for the bus */
 129         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
 130                                 RCAR_I2C_ICMCR_FSDA, false, 2, true);
 131         if (ret) {
 132                 if (rcar_i2c_recover(dev)) {
 133                         dev_err(dev, "Bus busy, aborting\n");
 134                         return ret;
 135                 }
 136         }
 137
 138         writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
 139         /* Reset */
 140         writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
 141                priv->base + RCAR_I2C_ICMCR);
 142         /* Clear Status */
 143         writel(0, priv->base + RCAR_I2C_ICMSR);
 144
 145         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
 146                                 true, 100, true);
 147         if (ret)
 148                 return ret;
 149
 150         /* Check NAK */
 151         if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
 152                 return -EREMOTEIO;
 153
 154         return 0;
 155 }
 156
 157 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
 158 {
 159         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 160         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 161         int i, ret = -EREMOTEIO;
 162
 163         for (i = 0; i < msg->len; i++) {
 164                 if (msg->len - 1 == i)
 165                         icmcr |= RCAR_I2C_ICMCR_FSB;
 166
 167                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 168                 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 169
 170                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 171                                         RCAR_I2C_ICMSR_MDR, true, 100, true);
 172                 if (ret)
 173                         return ret;
 174
 175                 msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
 176         }
 177
 178         writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 179
 180         return rcar_i2c_finish(dev);
 181 }
 182
 183 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
 184 {
 185         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 186         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 187         int i, ret = -EREMOTEIO;
 188
 189         for (i = 0; i < msg->len; i++) {
 190                 writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
 191                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 192                 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 193
 194                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 195                                         RCAR_I2C_ICMSR_MDE, true, 100, true);
 196                 if (ret)
 197                         return ret;
 198         }
 199
 200         writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 201         icmcr |= RCAR_I2C_ICMCR_FSB;
 202         writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 203
 204         return rcar_i2c_finish(dev);
 205 }
 206
 207 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 208 {
 209         int ret;
 210
 211         for (; nmsgs > 0; nmsgs--, msg++) {
 212                 ret = rcar_i2c_set_addr(dev, msg->addr, 1);
 213                 if (ret)
 214                         return ret;
 215
 216                 if (msg->flags & I2C_M_RD)
 217                         ret = rcar_i2c_read_common(dev, msg);
 218                 else
 219                         ret = rcar_i2c_write_common(dev, msg);
 220
 221                 if (ret)
 222                         return ret;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
 229 {
 230         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 231         int ret;
 232
 233         /* Ignore address 0, slave address */
 234         if (addr == 0)
 235                 return -EINVAL;
 236
 237         ret = rcar_i2c_set_addr(dev, addr, 1);
 238         writel(0, priv->base + RCAR_I2C_ICMSR);
 239         return ret;
 240 }
 241
 242 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
 243 {
 244         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 245         u32 scgd, cdf, round, ick, sum, scl;
 246         unsigned long rate;
 247
 248         /*
 249          * calculate SCL clock
 250          * see
 251          *      ICCCR
 252          *
 253          * ick  = clkp / (1 + CDF)
 254          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 255          *
 256          * ick  : I2C internal clock < 20 MHz
 257          * ticf : I2C SCL falling time
 258          * tr   : I2C SCL rising  time
 259          * intd : LSI internal delay
 260          * clkp : peripheral_clk
 261          * F[]  : integer up-valuation
 262          */
 263         rate = clk_get_rate(&priv->clk);
 264         cdf = rate / 20000000;
 265         if (cdf >= 8) {
 266                 dev_err(dev, "Input clock %lu too high\n", rate);
 267                 return -EIO;
 268         }
 269         ick = rate / (cdf + 1);
 270
 271         /*
 272          * it is impossible to calculate large scale
 273          * number on u32. separate it
 274          *
 275          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
 276          *  = F[sum * ick / 1000000000]
 277          *  = F[(ick / 1000000) * sum / 1000]
 278          */
 279         sum = 35 + 200 + priv->intdelay;
 280         round = (ick + 500000) / 1000000 * sum;
 281         round = (round + 500) / 1000;
 282
 283         /*
 284          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 285          *
 286          * Calculation result (= SCL) should be less than
 287          * bus_speed for hardware safety
 288          *
 289          * We could use something along the lines of
 290          *      div = ick / (bus_speed + 1) + 1;
 291          *      scgd = (div - 20 - round + 7) / 8;
 292          *      scl = ick / (20 + (scgd * 8) + round);
 293          * (not fully verified) but that would get pretty involved
 294          */
 295         for (scgd = 0; scgd < 0x40; scgd++) {
 296                 scl = ick / (20 + (scgd * 8) + round);
 297                 if (scl <= bus_freq_hz)
 298                         goto scgd_find;
 299         }
 300         dev_err(dev, "it is impossible to calculate best SCL\n");
 301         return -EIO;
 302
 303 scgd_find:
 304         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 305                 scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
 306
 307         priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
 308         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 309
 310         if (priv->type == RCAR_I2C_TYPE_GEN3) {
 311                 /* Set SCL/SDA delay */
 312                 writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int rcar_i2c_probe(struct udevice *dev)
 319 {
 320         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 321         int ret;
 322
 323         priv->base = dev_read_addr_ptr(dev);
 324         priv->intdelay = dev_read_u32_default(dev,
 325                                               "i2c-scl-internal-delay-ns", 5);
 326         priv->type = dev_get_driver_data(dev);
 327
 328         ret = clk_get_by_index(dev, 0, &priv->clk);
 329         if (ret)
 330                 return ret;
 331
 332         ret = clk_enable(&priv->clk);
 333         if (ret)
 334                 return ret;
 335
 336         /* reset slave mode */
 337         writel(0, priv->base + RCAR_I2C_ICSIER);
 338         writel(0, priv->base + RCAR_I2C_ICSAR);
 339         writel(0, priv->base + RCAR_I2C_ICSCR);
 340         writel(0, priv->base + RCAR_I2C_ICSSR);
 341
 342         /* reset master mode */
 343         writel(0, priv->base + RCAR_I2C_ICMIER);
 344         writel(0, priv->base + RCAR_I2C_ICMCR);
 345         writel(0, priv->base + RCAR_I2C_ICMSR);
 346         writel(0, priv->base + RCAR_I2C_ICMAR);
 347
 348         ret = rcar_i2c_set_speed(dev, I2C_SPEED_STANDARD_RATE);
 349         if (ret)
 350                 clk_disable(&priv->clk);
 351
 352         return ret;
 353 }
 354
 355 static const struct dm_i2c_ops rcar_i2c_ops = {
 356         .xfer           = rcar_i2c_xfer,
 357         .probe_chip     = rcar_i2c_probe_chip,
 358         .set_bus_speed  = rcar_i2c_set_speed,
 359 };
 360
 361 static const struct udevice_id rcar_i2c_ids[] = {
 362         { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
 363         { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
 364         { }
 365 };
 366
 367 U_BOOT_DRIVER(i2c_rcar) = {
 368         .name           = "i2c_rcar",
 369         .id             = UCLASS_I2C,
 370         .of_match       = rcar_i2c_ids,
 371         .probe          = rcar_i2c_probe,
 372         .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
 373         .ops            = &rcar_i2c_ops,
 374 };