drivers/i2c/rcar_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/i2c/rcar_i2c.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Clock configuration based on Linux i2c-rcar.c:
   8  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
   9  * Copyright (C) 2011-2015 Renesas Electronics Corporation
  10  * Copyright (C) 2012-14 Renesas Solutions Corp.
  11  *   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  12  */
  13
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <dm.h>
  17 #include <i2c.h>
  18 #include <asm/io.h>
  19 #include <wait_bit.h>
  20 #include <dm/device_compat.h>
  21 #include <linux/delay.h>
  22
  23 #define RCAR_I2C_ICSCR                  0x00 /* slave ctrl */
  24 #define RCAR_I2C_ICMCR                  0x04 /* master ctrl */
  25 #define RCAR_I2C_ICMCR_MDBS             BIT(7) /* non-fifo mode switch */
  26 #define RCAR_I2C_ICMCR_FSCL             BIT(6) /* override SCL pin */
  27 #define RCAR_I2C_ICMCR_FSDA             BIT(5) /* override SDA pin */
  28 #define RCAR_I2C_ICMCR_OBPC             BIT(4) /* override pins */
  29 #define RCAR_I2C_ICMCR_MIE              BIT(3) /* master if enable */
  30 #define RCAR_I2C_ICMCR_TSBE             BIT(2)
  31 #define RCAR_I2C_ICMCR_FSB              BIT(1) /* force stop bit */
  32 #define RCAR_I2C_ICMCR_ESG              BIT(0) /* enable start bit gen */
  33 #define RCAR_I2C_ICSSR                  0x08 /* slave status */
  34 #define RCAR_I2C_ICMSR                  0x0c /* master status */
  35 #define RCAR_I2C_ICMSR_MASK             0x7f
  36 #define RCAR_I2C_ICMSR_MNR              BIT(6) /* Nack */
  37 #define RCAR_I2C_ICMSR_MAL              BIT(5) /* Arbitration lost */
  38 #define RCAR_I2C_ICMSR_MST              BIT(4) /* Stop */
  39 #define RCAR_I2C_ICMSR_MDE              BIT(3)
  40 #define RCAR_I2C_ICMSR_MDT              BIT(2)
  41 #define RCAR_I2C_ICMSR_MDR              BIT(1)
  42 #define RCAR_I2C_ICMSR_MAT              BIT(0)
  43 #define RCAR_I2C_ICSIER                 0x10 /* slave irq enable */
  44 #define RCAR_I2C_ICMIER                 0x14 /* master irq enable */
  45 #define RCAR_I2C_ICCCR                  0x18 /* clock dividers */
  46 #define RCAR_I2C_ICCCR_SCGD_OFF         3
  47 #define RCAR_I2C_ICSAR                  0x1c /* slave address */
  48 #define RCAR_I2C_ICMAR                  0x20 /* master address */
  49 #define RCAR_I2C_ICRXD_ICTXD            0x24 /* data port */
  50 /*
  51  * First Bit Setup Cycle (Gen3).
  52  * Defines 1st bit delay between SDA and SCL.
  53  */
  54 #define RCAR_I2C_ICFBSCR                0x38
  55 #define RCAR_I2C_ICFBSCR_TCYC17         0x0f /* 17*Tcyc */
  56
  57
  58 enum rcar_i2c_type {
  59         RCAR_I2C_TYPE_GEN2,
  60         RCAR_I2C_TYPE_GEN3,
  61 };
  62
  63 struct rcar_i2c_priv {
  64         void __iomem            *base;
  65         struct clk              clk;
  66         u32                     intdelay;
  67         u32                     icccr;
  68         enum rcar_i2c_type      type;
  69 };
  70
  71 static int rcar_i2c_finish(struct udevice *dev)
  72 {
  73         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  74         int ret;
  75
  76         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
  77                                 true, 10, true);
  78
  79         writel(0, priv->base + RCAR_I2C_ICSSR);
  80         writel(0, priv->base + RCAR_I2C_ICMSR);
  81         writel(0, priv->base + RCAR_I2C_ICMCR);
  82
  83         return ret;
  84 }
  85
  86 static int rcar_i2c_recover(struct udevice *dev)
  87 {
  88         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  89         u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
  90         u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
  91         int i;
  92         u32 mstat;
  93
  94         /* Send 9 SCL pulses */
  95         for (i = 0; i < 9; i++) {
  96                 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  97                 udelay(5);
  98                 writel(mcra, priv->base + RCAR_I2C_ICMCR);
  99                 udelay(5);
 100         }
 101
 102         /* Send stop condition */
 103         udelay(5);
 104         writel(mcra, priv->base + RCAR_I2C_ICMCR);
 105         udelay(5);
 106         writel(mcr, priv->base + RCAR_I2C_ICMCR);
 107         udelay(5);
 108         writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 109         udelay(5);
 110         writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 111         udelay(5);
 112
 113         mstat = readl(priv->base + RCAR_I2C_ICMSR);
 114         return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
 115 }
 116
 117 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
 118 {
 119         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 120         u32 mask = RCAR_I2C_ICMSR_MAT |
 121                    (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
 122         int ret;
 123
 124         writel(0, priv->base + RCAR_I2C_ICMIER);
 125         writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
 126         writel(0, priv->base + RCAR_I2C_ICMSR);
 127         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 128
 129         /* Wait for the bus */
 130         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
 131                                 RCAR_I2C_ICMCR_FSDA, false, 2, true);
 132         if (ret) {
 133                 if (rcar_i2c_recover(dev)) {
 134                         dev_err(dev, "Bus busy, aborting\n");
 135                         return ret;
 136                 }
 137         }
 138
 139         writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
 140         /* Reset */
 141         writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
 142                priv->base + RCAR_I2C_ICMCR);
 143         /* Clear Status */
 144         writel(0, priv->base + RCAR_I2C_ICMSR);
 145
 146         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
 147                                 true, 100, true);
 148         if (ret)
 149                 return ret;
 150
 151         /* Check NAK */
 152         if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
 153                 return -EREMOTEIO;
 154
 155         return 0;
 156 }
 157
 158 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
 159 {
 160         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 161         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 162         int i, ret = -EREMOTEIO;
 163
 164         for (i = 0; i < msg->len; i++) {
 165                 if (msg->len - 1 == i)
 166                         icmcr |= RCAR_I2C_ICMCR_FSB;
 167
 168                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 169                 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 170
 171                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 172                                         RCAR_I2C_ICMSR_MDR, true, 100, true);
 173                 if (ret)
 174                         return ret;
 175
 176                 msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
 177         }
 178
 179         writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 180
 181         return rcar_i2c_finish(dev);
 182 }
 183
 184 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
 185 {
 186         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 187         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 188         int i, ret = -EREMOTEIO;
 189
 190         for (i = 0; i < msg->len; i++) {
 191                 writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
 192                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 193                 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 194
 195                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 196                                         RCAR_I2C_ICMSR_MDE, true, 100, true);
 197                 if (ret)
 198                         return ret;
 199         }
 200
 201         writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 202         icmcr |= RCAR_I2C_ICMCR_FSB;
 203         writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 204
 205         return rcar_i2c_finish(dev);
 206 }
 207
 208 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 209 {
 210         int ret;
 211
 212         for (; nmsgs > 0; nmsgs--, msg++) {
 213                 ret = rcar_i2c_set_addr(dev, msg->addr, 1);
 214                 if (ret)
 215                         return ret;
 216
 217                 if (msg->flags & I2C_M_RD)
 218                         ret = rcar_i2c_read_common(dev, msg);
 219                 else
 220                         ret = rcar_i2c_write_common(dev, msg);
 221
 222                 if (ret)
 223                         return ret;
 224         }
 225
 226         return 0;
 227 }
 228
 229 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
 230 {
 231         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 232         int ret;
 233
 234         /* Ignore address 0, slave address */
 235         if (addr == 0)
 236                 return -EINVAL;
 237
 238         ret = rcar_i2c_set_addr(dev, addr, 1);
 239         writel(0, priv->base + RCAR_I2C_ICMSR);
 240         return ret;
 241 }
 242
 243 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
 244 {
 245         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 246         u32 scgd, cdf, round, ick, sum, scl;
 247         unsigned long rate;
 248
 249         /*
 250          * calculate SCL clock
 251          * see
 252          *      ICCCR
 253          *
 254          * ick  = clkp / (1 + CDF)
 255          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 256          *
 257          * ick  : I2C internal clock < 20 MHz
 258          * ticf : I2C SCL falling time
 259          * tr   : I2C SCL rising  time
 260          * intd : LSI internal delay
 261          * clkp : peripheral_clk
 262          * F[]  : integer up-valuation
 263          */
 264         rate = clk_get_rate(&priv->clk);
 265         cdf = rate / 20000000;
 266         if (cdf >= 8) {
 267                 dev_err(dev, "Input clock %lu too high\n", rate);
 268                 return -EIO;
 269         }
 270         ick = rate / (cdf + 1);
 271
 272         /*
 273          * it is impossible to calculate large scale
 274          * number on u32. separate it
 275          *
 276          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
 277          *  = F[sum * ick / 1000000000]
 278          *  = F[(ick / 1000000) * sum / 1000]
 279          */
 280         sum = 35 + 200 + priv->intdelay;
 281         round = (ick + 500000) / 1000000 * sum;
 282         round = (round + 500) / 1000;
 283
 284         /*
 285          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 286          *
 287          * Calculation result (= SCL) should be less than
 288          * bus_speed for hardware safety
 289          *
 290          * We could use something along the lines of
 291          *      div = ick / (bus_speed + 1) + 1;
 292          *      scgd = (div - 20 - round + 7) / 8;
 293          *      scl = ick / (20 + (scgd * 8) + round);
 294          * (not fully verified) but that would get pretty involved
 295          */
 296         for (scgd = 0; scgd < 0x40; scgd++) {
 297                 scl = ick / (20 + (scgd * 8) + round);
 298                 if (scl <= bus_freq_hz)
 299                         goto scgd_find;
 300         }
 301         dev_err(dev, "it is impossible to calculate best SCL\n");
 302         return -EIO;
 303
 304 scgd_find:
 305         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 306                 scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
 307
 308         priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
 309         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 310
 311         if (priv->type == RCAR_I2C_TYPE_GEN3) {
 312                 /* Set SCL/SDA delay */
 313                 writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int rcar_i2c_probe(struct udevice *dev)
 320 {
 321         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 322         int ret;
 323
 324         priv->base = dev_read_addr_ptr(dev);
 325         priv->intdelay = dev_read_u32_default(dev,
 326                                               "i2c-scl-internal-delay-ns", 5);
 327         priv->type = dev_get_driver_data(dev);
 328
 329         ret = clk_get_by_index(dev, 0, &priv->clk);
 330         if (ret)
 331                 return ret;
 332
 333         ret = clk_enable(&priv->clk);
 334         if (ret)
 335                 return ret;
 336
 337         /* reset slave mode */
 338         writel(0, priv->base + RCAR_I2C_ICSIER);
 339         writel(0, priv->base + RCAR_I2C_ICSAR);
 340         writel(0, priv->base + RCAR_I2C_ICSCR);
 341         writel(0, priv->base + RCAR_I2C_ICSSR);
 342
 343         /* reset master mode */
 344         writel(0, priv->base + RCAR_I2C_ICMIER);
 345         writel(0, priv->base + RCAR_I2C_ICMCR);
 346         writel(0, priv->base + RCAR_I2C_ICMSR);
 347         writel(0, priv->base + RCAR_I2C_ICMAR);
 348
 349         ret = rcar_i2c_set_speed(dev, I2C_SPEED_STANDARD_RATE);
 350         if (ret)
 351                 clk_disable(&priv->clk);
 352
 353         return ret;
 354 }
 355
 356 static const struct dm_i2c_ops rcar_i2c_ops = {
 357         .xfer           = rcar_i2c_xfer,
 358         .probe_chip     = rcar_i2c_probe_chip,
 359         .set_bus_speed  = rcar_i2c_set_speed,
 360 };
 361
 362 static const struct udevice_id rcar_i2c_ids[] = {
 363         { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
 364         { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
 365         { }
 366 };
 367
 368 U_BOOT_DRIVER(i2c_rcar) = {
 369         .name           = "i2c_rcar",
 370         .id             = UCLASS_I2C,
 371         .of_match       = rcar_i2c_ids,
 372         .probe          = rcar_i2c_probe,
 373         .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
 374         .ops            = &rcar_i2c_ops,
 375 };