drivers/i2c/rcar_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/i2c/rcar_i2c.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Clock configuration based on Linux i2c-rcar.c:
   8  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
   9  * Copyright (C) 2011-2015 Renesas Electronics Corporation
  10  * Copyright (C) 2012-14 Renesas Solutions Corp.
  11  *   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  12  */
  13
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <dm.h>
  17 #include <i2c.h>
  18 #include <asm/io.h>
  19 #include <wait_bit.h>
  20 #include <dm/device_compat.h>
  21 #include <linux/bitops.h>
  22 #include <linux/delay.h>
  23
  24 #define RCAR_I2C_ICSCR                  0x00 /* slave ctrl */
  25 #define RCAR_I2C_ICMCR                  0x04 /* master ctrl */
  26 #define RCAR_I2C_ICMCR_MDBS             BIT(7) /* non-fifo mode switch */
  27 #define RCAR_I2C_ICMCR_FSCL             BIT(6) /* override SCL pin */
  28 #define RCAR_I2C_ICMCR_FSDA             BIT(5) /* override SDA pin */
  29 #define RCAR_I2C_ICMCR_OBPC             BIT(4) /* override pins */
  30 #define RCAR_I2C_ICMCR_MIE              BIT(3) /* master if enable */
  31 #define RCAR_I2C_ICMCR_TSBE             BIT(2)
  32 #define RCAR_I2C_ICMCR_FSB              BIT(1) /* force stop bit */
  33 #define RCAR_I2C_ICMCR_ESG              BIT(0) /* enable start bit gen */
  34 #define RCAR_I2C_ICSSR                  0x08 /* slave status */
  35 #define RCAR_I2C_ICMSR                  0x0c /* master status */
  36 #define RCAR_I2C_ICMSR_MASK             0x7f
  37 #define RCAR_I2C_ICMSR_MNR              BIT(6) /* Nack */
  38 #define RCAR_I2C_ICMSR_MAL              BIT(5) /* Arbitration lost */
  39 #define RCAR_I2C_ICMSR_MST              BIT(4) /* Stop */
  40 #define RCAR_I2C_ICMSR_MDE              BIT(3)
  41 #define RCAR_I2C_ICMSR_MDT              BIT(2)
  42 #define RCAR_I2C_ICMSR_MDR              BIT(1)
  43 #define RCAR_I2C_ICMSR_MAT              BIT(0)
  44 #define RCAR_I2C_ICSIER                 0x10 /* slave irq enable */
  45 #define RCAR_I2C_ICMIER                 0x14 /* master irq enable */
  46 #define RCAR_I2C_ICCCR                  0x18 /* clock dividers */
  47 #define RCAR_I2C_ICCCR_SCGD_OFF         3
  48 #define RCAR_I2C_ICSAR                  0x1c /* slave address */
  49 #define RCAR_I2C_ICMAR                  0x20 /* master address */
  50 #define RCAR_I2C_ICRXD_ICTXD            0x24 /* data port */
  51 /*
  52  * First Bit Setup Cycle (Gen3).
  53  * Defines 1st bit delay between SDA and SCL.
  54  */
  55 #define RCAR_I2C_ICFBSCR                0x38
  56 #define RCAR_I2C_ICFBSCR_TCYC17         0x0f /* 17*Tcyc */
  57
  58
  59 enum rcar_i2c_type {
  60         RCAR_I2C_TYPE_GEN2,
  61         RCAR_I2C_TYPE_GEN3,
  62 };
  63
  64 struct rcar_i2c_priv {
  65         void __iomem            *base;
  66         struct clk              clk;
  67         u32                     intdelay;
  68         u32                     icccr;
  69         enum rcar_i2c_type      type;
  70 };
  71
  72 static int rcar_i2c_finish(struct udevice *dev)
  73 {
  74         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  75         int ret;
  76
  77         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
  78                                 true, 10, true);
  79
  80         writel(0, priv->base + RCAR_I2C_ICSSR);
  81         writel(0, priv->base + RCAR_I2C_ICMSR);
  82         writel(0, priv->base + RCAR_I2C_ICMCR);
  83
  84         return ret;
  85 }
  86
  87 static int rcar_i2c_recover(struct udevice *dev)
  88 {
  89         struct rcar_i2c_priv *priv = dev_get_priv(dev);
  90         u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
  91         u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
  92         int i;
  93         u32 mstat;
  94
  95         /* Send 9 SCL pulses */
  96         for (i = 0; i < 9; i++) {
  97                 writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  98                 udelay(5);
  99                 writel(mcra, priv->base + RCAR_I2C_ICMCR);
 100                 udelay(5);
 101         }
 102
 103         /* Send stop condition */
 104         udelay(5);
 105         writel(mcra, priv->base + RCAR_I2C_ICMCR);
 106         udelay(5);
 107         writel(mcr, priv->base + RCAR_I2C_ICMCR);
 108         udelay(5);
 109         writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 110         udelay(5);
 111         writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
 112         udelay(5);
 113
 114         mstat = readl(priv->base + RCAR_I2C_ICMSR);
 115         return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
 116 }
 117
 118 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
 119 {
 120         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 121         u32 mask = RCAR_I2C_ICMSR_MAT |
 122                    (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
 123         int ret;
 124
 125         writel(0, priv->base + RCAR_I2C_ICMIER);
 126         writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
 127         writel(0, priv->base + RCAR_I2C_ICMSR);
 128         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 129
 130         /* Wait for the bus */
 131         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
 132                                 RCAR_I2C_ICMCR_FSDA, false, 2, true);
 133         if (ret) {
 134                 if (rcar_i2c_recover(dev)) {
 135                         dev_err(dev, "Bus busy, aborting\n");
 136                         return ret;
 137                 }
 138         }
 139
 140         writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
 141         /* Reset */
 142         writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
 143                priv->base + RCAR_I2C_ICMCR);
 144         /* Clear Status */
 145         writel(0, priv->base + RCAR_I2C_ICMSR);
 146
 147         ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
 148                                 true, 100, true);
 149         if (ret)
 150                 return ret;
 151
 152         /* Check NAK */
 153         if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
 154                 return -EREMOTEIO;
 155
 156         return 0;
 157 }
 158
 159 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
 160 {
 161         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 162         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 163         int i, ret = -EREMOTEIO;
 164
 165         for (i = 0; i < msg->len; i++) {
 166                 if (msg->len - 1 == i)
 167                         icmcr |= RCAR_I2C_ICMCR_FSB;
 168
 169                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 170                 writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 171
 172                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 173                                         RCAR_I2C_ICMSR_MDR, true, 100, true);
 174                 if (ret)
 175                         return ret;
 176
 177                 msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
 178         }
 179
 180         writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
 181
 182         return rcar_i2c_finish(dev);
 183 }
 184
 185 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
 186 {
 187         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 188         u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
 189         int i, ret = -EREMOTEIO;
 190
 191         for (i = 0; i < msg->len; i++) {
 192                 writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
 193                 writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 194                 writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 195
 196                 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
 197                                         RCAR_I2C_ICMSR_MDE, true, 100, true);
 198                 if (ret)
 199                         return ret;
 200         }
 201
 202         writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
 203         icmcr |= RCAR_I2C_ICMCR_FSB;
 204         writel(icmcr, priv->base + RCAR_I2C_ICMCR);
 205
 206         return rcar_i2c_finish(dev);
 207 }
 208
 209 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
 210 {
 211         int ret;
 212
 213         for (; nmsgs > 0; nmsgs--, msg++) {
 214                 ret = rcar_i2c_set_addr(dev, msg->addr, 1);
 215                 if (ret)
 216                         return ret;
 217
 218                 if (msg->flags & I2C_M_RD)
 219                         ret = rcar_i2c_read_common(dev, msg);
 220                 else
 221                         ret = rcar_i2c_write_common(dev, msg);
 222
 223                 if (ret)
 224                         return ret;
 225         }
 226
 227         return 0;
 228 }
 229
 230 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
 231 {
 232         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 233         int ret;
 234
 235         /* Ignore address 0, slave address */
 236         if (addr == 0)
 237                 return -EINVAL;
 238
 239         ret = rcar_i2c_set_addr(dev, addr, 1);
 240         writel(0, priv->base + RCAR_I2C_ICMSR);
 241         return ret;
 242 }
 243
 244 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
 245 {
 246         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 247         u32 scgd, cdf, round, ick, sum, scl;
 248         unsigned long rate;
 249
 250         /*
 251          * calculate SCL clock
 252          * see
 253          *      ICCCR
 254          *
 255          * ick  = clkp / (1 + CDF)
 256          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 257          *
 258          * ick  : I2C internal clock < 20 MHz
 259          * ticf : I2C SCL falling time
 260          * tr   : I2C SCL rising  time
 261          * intd : LSI internal delay
 262          * clkp : peripheral_clk
 263          * F[]  : integer up-valuation
 264          */
 265         rate = clk_get_rate(&priv->clk);
 266         cdf = rate / 20000000;
 267         if (cdf >= 8) {
 268                 dev_err(dev, "Input clock %lu too high\n", rate);
 269                 return -EIO;
 270         }
 271         ick = rate / (cdf + 1);
 272
 273         /*
 274          * it is impossible to calculate large scale
 275          * number on u32. separate it
 276          *
 277          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
 278          *  = F[sum * ick / 1000000000]
 279          *  = F[(ick / 1000000) * sum / 1000]
 280          */
 281         sum = 35 + 200 + priv->intdelay;
 282         round = (ick + 500000) / 1000000 * sum;
 283         round = (round + 500) / 1000;
 284
 285         /*
 286          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 287          *
 288          * Calculation result (= SCL) should be less than
 289          * bus_speed for hardware safety
 290          *
 291          * We could use something along the lines of
 292          *      div = ick / (bus_speed + 1) + 1;
 293          *      scgd = (div - 20 - round + 7) / 8;
 294          *      scl = ick / (20 + (scgd * 8) + round);
 295          * (not fully verified) but that would get pretty involved
 296          */
 297         for (scgd = 0; scgd < 0x40; scgd++) {
 298                 scl = ick / (20 + (scgd * 8) + round);
 299                 if (scl <= bus_freq_hz)
 300                         goto scgd_find;
 301         }
 302         dev_err(dev, "it is impossible to calculate best SCL\n");
 303         return -EIO;
 304
 305 scgd_find:
 306         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 307                 scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
 308
 309         priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
 310         writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
 311
 312         if (priv->type == RCAR_I2C_TYPE_GEN3) {
 313                 /* Set SCL/SDA delay */
 314                 writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int rcar_i2c_probe(struct udevice *dev)
 321 {
 322         struct rcar_i2c_priv *priv = dev_get_priv(dev);
 323         int ret;
 324
 325         priv->base = dev_read_addr_ptr(dev);
 326         priv->intdelay = dev_read_u32_default(dev,
 327                                               "i2c-scl-internal-delay-ns", 5);
 328         priv->type = dev_get_driver_data(dev);
 329
 330         ret = clk_get_by_index(dev, 0, &priv->clk);
 331         if (ret)
 332                 return ret;
 333
 334         ret = clk_enable(&priv->clk);
 335         if (ret)
 336                 return ret;
 337
 338         /* reset slave mode */
 339         writel(0, priv->base + RCAR_I2C_ICSIER);
 340         writel(0, priv->base + RCAR_I2C_ICSAR);
 341         writel(0, priv->base + RCAR_I2C_ICSCR);
 342         writel(0, priv->base + RCAR_I2C_ICSSR);
 343
 344         /* reset master mode */
 345         writel(0, priv->base + RCAR_I2C_ICMIER);
 346         writel(0, priv->base + RCAR_I2C_ICMCR);
 347         writel(0, priv->base + RCAR_I2C_ICMSR);
 348         writel(0, priv->base + RCAR_I2C_ICMAR);
 349
 350         ret = rcar_i2c_set_speed(dev, I2C_SPEED_STANDARD_RATE);
 351         if (ret)
 352                 clk_disable(&priv->clk);
 353
 354         return ret;
 355 }
 356
 357 static const struct dm_i2c_ops rcar_i2c_ops = {
 358         .xfer           = rcar_i2c_xfer,
 359         .probe_chip     = rcar_i2c_probe_chip,
 360         .set_bus_speed  = rcar_i2c_set_speed,
 361 };
 362
 363 static const struct udevice_id rcar_i2c_ids[] = {
 364         { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
 365         { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
 366         { }
 367 };
 368
 369 U_BOOT_DRIVER(i2c_rcar) = {
 370         .name           = "i2c_rcar",
 371         .id             = UCLASS_I2C,
 372         .of_match       = rcar_i2c_ids,
 373         .probe          = rcar_i2c_probe,
 374         .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
 375         .ops            = &rcar_i2c_ops,
 376 };