1 // SPDX-License-Identifier: GPL-2.0+
3 * i2c driver for Freescale i.MX series
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
8 * Based on i2c-imx.c from linux kernel:
9 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
10 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
11 * Copyright (C) 2007 RightHand Technologies, Inc.
12 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <dm/device_compat.h>
21 #include <linux/errno.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/mach-imx/sys_proto.h>
28 #include <dm/pinctrl.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define I2C_QUIRK_FLAG (1 << 0)
35 #define IMX_I2C_REGSHIFT 2
36 #define VF610_I2C_REGSHIFT 0
38 #define I2C_EARLY_INIT_INDEX 0
39 #ifdef CONFIG_SYS_I2C_IFDR_DIV
40 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
42 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
52 #define I2CR_IIEN (1 << 6)
53 #define I2CR_MSTA (1 << 5)
54 #define I2CR_MTX (1 << 4)
55 #define I2CR_TX_NO_AK (1 << 3)
56 #define I2CR_RSTA (1 << 2)
58 #define I2SR_ICF (1 << 7)
59 #define I2SR_IBB (1 << 5)
60 #define I2SR_IAL (1 << 4)
61 #define I2SR_IIF (1 << 1)
62 #define I2SR_RX_NO_AK (1 << 0)
65 #define I2CR_IEN (0 << 7)
66 #define I2CR_IDIS (1 << 7)
67 #define I2SR_IIF_CLEAR (1 << 1)
69 #define I2CR_IEN (1 << 7)
70 #define I2CR_IDIS (0 << 7)
71 #define I2SR_IIF_CLEAR (0 << 1)
75 static u16 i2c_clk_div[60][2] = {
76 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
77 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
78 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
79 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
80 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
81 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
82 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
83 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
84 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
85 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
86 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
87 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
88 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
89 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
90 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
93 static u16 i2c_clk_div[50][2] = {
94 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
95 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
96 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
97 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
98 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
99 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
100 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
101 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
102 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
103 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
104 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
105 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
106 { 3072, 0x1E }, { 3840, 0x1F }
110 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
111 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
113 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
114 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
116 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
117 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
119 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
120 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
123 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
124 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
126 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
127 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
129 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
130 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
132 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
133 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
137 * Calculate and set proper clock divider
139 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
141 unsigned int i2c_clk_rate;
145 #if defined(CONFIG_MX31)
146 struct clock_control_regs *sc_regs =
147 (struct clock_control_regs *)CCM_BASE;
149 /* start the required I2C clock */
150 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
154 /* Divider value calculation */
155 #if CONFIG_IS_ENABLED(CLK)
156 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
158 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
161 div = (i2c_clk_rate + rate - 1) / rate;
162 if (div < i2c_clk_div[0][0])
164 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
165 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
167 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
170 /* Store divider value */
177 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
179 ulong base = i2c_bus->base;
180 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
181 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
182 u8 idx = i2c_clk_div[clk_idx][1];
183 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
188 /* Store divider value */
189 writeb(idx, base + (IFDR << reg_shift));
192 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
193 writeb(0, base + (I2SR << reg_shift));
197 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
198 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
199 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
201 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
205 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
206 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
207 ulong base = i2c_bus->base;
208 ulong start_time = get_timer(0);
210 sr = readb(base + (I2SR << reg_shift));
213 writeb(sr | I2SR_IAL, base +
214 (I2SR << reg_shift));
216 writeb(sr & ~I2SR_IAL, base +
217 (I2SR << reg_shift));
218 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
219 __func__, sr, readb(base + (I2CR << reg_shift)),
223 if ((sr & (state >> 8)) == (unsigned char)state)
226 elapsed = get_timer(start_time);
227 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
230 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
231 sr, readb(base + (I2CR << reg_shift)), state);
235 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
238 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
239 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
240 ulong base = i2c_bus->base;
242 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
243 writeb(byte, base + (I2DR << reg_shift));
245 ret = wait_for_sr_state(i2c_bus, ST_IIF);
248 if (ret & I2SR_RX_NO_AK)
254 * Stub implementations for outer i2c slave operations.
256 void __i2c_force_reset_slave(void)
259 void i2c_force_reset_slave(void)
260 __attribute__((weak, alias("__i2c_force_reset_slave")));
263 * Stop I2C transaction
265 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
268 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
269 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
270 ulong base = i2c_bus->base;
271 unsigned int temp = readb(base + (I2CR << reg_shift));
273 temp &= ~(I2CR_MSTA | I2CR_MTX);
274 writeb(temp, base + (I2CR << reg_shift));
275 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
277 printf("%s:trigger stop failed\n", __func__);
281 * Send start signal, chip address and
282 * write register address
284 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
289 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
290 ulong base = i2c_bus->base;
291 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
293 /* Reset i2c slave */
294 i2c_force_reset_slave();
296 /* Enable I2C controller */
298 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
300 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
303 writeb(I2CR_IEN, base + (I2CR << reg_shift));
304 /* Wait for controller to be stable */
308 if (readb(base + (IADR << reg_shift)) == (chip << 1))
309 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
310 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
311 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
315 /* Start I2C transaction */
316 temp = readb(base + (I2CR << reg_shift));
318 writeb(temp, base + (I2CR << reg_shift));
320 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
324 temp |= I2CR_MTX | I2CR_TX_NO_AK;
325 writeb(temp, base + (I2CR << reg_shift));
328 /* write slave address */
329 ret = tx_byte(i2c_bus, chip << 1);
334 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
343 #ifndef CONFIG_DM_I2C
344 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
346 if (i2c_bus && i2c_bus->idle_bus_fn)
347 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
352 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
354 * scl-gpios: specify the gpio related to SCL pin
355 * sda-gpios: specify the gpio related to SDA pin
356 * add pinctrl to configure i2c pins to gpio function for i2c
357 * bus recovery, call it "gpio" state
360 * The i2c_idle_bus is an implementation following Linux Kernel.
362 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
364 struct udevice *bus = i2c_bus->bus;
365 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
366 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
367 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
368 int sda, scl, idle_sclks;
370 ulong elapsed, start_time;
372 if (pinctrl_select_state(bus, "gpio")) {
373 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
375 * GPIO pinctrl for i2c force idle is not a must,
376 * but it is strongly recommended to be used.
377 * Because it can help you to recover from bad
378 * i2c bus state. Do not return failure, because
384 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
385 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
386 scl = dm_gpio_get_value(scl_gpio);
387 sda = dm_gpio_get_value(sda_gpio);
389 if ((sda & scl) == 1)
390 goto exit; /* Bus is idle already */
393 * In most cases it is just enough to generate 8 + 1 SCLK
394 * clocks to recover I2C slave device from 'stuck' state
395 * (when for example SW reset was performed, in the middle of
398 * However, there are devices which send data in packets of
399 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
404 if (i2c->max_transaction_bytes > 0)
405 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
406 /* Send high and low on the SCL line */
407 for (i = 0; i < idle_sclks; i++) {
408 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
409 dm_gpio_set_value(scl_gpio, 0);
411 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
414 start_time = get_timer(0);
416 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
417 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
418 scl = dm_gpio_get_value(scl_gpio);
419 sda = dm_gpio_get_value(sda_gpio);
420 if ((sda & scl) == 1)
423 elapsed = get_timer(start_time);
424 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
426 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
432 pinctrl_select_state(bus, "default");
437 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
442 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
443 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
448 for (retry = 0; retry < 3; retry++) {
449 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
452 i2c_imx_stop(i2c_bus);
453 if (ret == -EREMOTEIO)
456 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
458 if (ret != -ERESTART)
459 /* Disable controller */
460 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
462 if (i2c_idle_bus(i2c_bus) < 0)
465 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
470 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
475 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
476 debug("write_data: ");
477 /* use rc for counter */
478 for (i = 0; i < len; ++i)
479 debug(" 0x%02x", buf[i]);
482 for (i = 0; i < len; i++) {
483 ret = tx_byte(i2c_bus, buf[i]);
485 debug("i2c_write_data(): rc=%d\n", ret);
493 /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
494 * final message of a transaction. If not, it switches the bus back to TX mode
495 * and does not send a STOP, leaving the bus in a state where a repeated start
496 * and address can be sent for another message.
498 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
504 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
505 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
506 ulong base = i2c_bus->base;
508 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
510 /* setup bus to read data */
511 temp = readb(base + (I2CR << reg_shift));
512 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
514 temp |= I2CR_TX_NO_AK;
515 writeb(temp, base + (I2CR << reg_shift));
516 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
517 /* dummy read to clear ICF */
518 readb(base + (I2DR << reg_shift));
521 for (i = 0; i < len; i++) {
522 ret = wait_for_sr_state(i2c_bus, ST_IIF);
524 debug("i2c_read_data(): ret=%d\n", ret);
525 i2c_imx_stop(i2c_bus);
529 if (i == (len - 1)) {
530 /* Final byte has already been received by master! When
531 * we read it from I2DR, the master will start another
532 * cycle. We must program it first to send a STOP or
533 * switch to TX to avoid this.
536 i2c_imx_stop(i2c_bus);
538 /* Final read, no stop, switch back to tx */
539 temp = readb(base + (I2CR << reg_shift));
540 temp |= I2CR_MTX | I2CR_TX_NO_AK;
541 writeb(temp, base + (I2CR << reg_shift));
543 } else if (i == (len - 2)) {
544 /* Master has already recevied penultimate byte. When
545 * we read it from I2DR, master will start RX of final
546 * byte. We must set TX_NO_AK now so it does not ACK
549 temp = readb(base + (I2CR << reg_shift));
550 temp |= I2CR_TX_NO_AK;
551 writeb(temp, base + (I2CR << reg_shift));
554 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
555 buf[i] = readb(base + (I2DR << reg_shift));
558 /* reuse ret for counter*/
559 for (ret = 0; ret < len; ++ret)
560 debug(" 0x%02x", buf[ret]);
563 /* It is not clear to me that this is necessary */
565 i2c_imx_stop(i2c_bus);
569 int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
574 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
575 __attribute__((weak, alias("__enable_i2c_clk")));
577 #ifndef CONFIG_DM_I2C
579 * Read data from I2C device
581 * The transactions use the syntax defined in the Linux kernel I2C docs.
583 * If alen is > 0, then this function will send a transaction of the form:
584 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
585 * This is a normal I2C register read: writing the register address, then doing
586 * a repeated start and reading the data.
588 * If alen == 0, then we get this transaction:
589 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
590 * This is somewhat unusual, though valid, transaction. It addresses the chip
591 * in write mode, but doesn't actually write any register address or data, then
592 * does a repeated start and reads data.
594 * If alen < 0, then we get this transaction:
595 * S Chip Rd [A] [data] A ... NA P
596 * The chip is addressed in read mode and then data is read. No register
597 * address is written first. This is perfectly valid on most devices and
598 * required on some (usually those that don't act like an array of registers).
600 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
601 int alen, u8 *buf, int len)
605 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
606 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
607 ulong base = i2c_bus->base;
609 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
614 temp = readb(base + (I2CR << reg_shift));
616 writeb(temp, base + (I2CR << reg_shift));
619 ret = tx_byte(i2c_bus, (chip << 1) | 1);
621 i2c_imx_stop(i2c_bus);
625 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
627 i2c_imx_stop(i2c_bus);
632 * Write data to I2C device
634 * If alen > 0, we get this transaction:
635 * S Chip Wr [A] addr [A] data [A] ... [A] P
636 * An ordinary write register command.
638 * If alen == 0, then we get this:
639 * S Chip Wr [A] data [A] ... [A] P
640 * This is a simple I2C write.
642 * If alen < 0, then we get this:
643 * S data [A] ... [A] P
644 * This is most likely NOT something that should be used. It doesn't send the
645 * chip address first, so in effect, the first byte of data will be used as the
648 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
649 int alen, const u8 *buf, int len)
653 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
657 ret = i2c_write_data(i2c_bus, chip, buf, len);
659 i2c_imx_stop(i2c_bus);
664 #if !defined(I2C2_BASE_ADDR)
665 #define I2C2_BASE_ADDR 0
668 #if !defined(I2C3_BASE_ADDR)
669 #define I2C3_BASE_ADDR 0
672 #if !defined(I2C4_BASE_ADDR)
673 #define I2C4_BASE_ADDR 0
676 #if !defined(I2C5_BASE_ADDR)
677 #define I2C5_BASE_ADDR 0
680 #if !defined(I2C6_BASE_ADDR)
681 #define I2C6_BASE_ADDR 0
684 #if !defined(I2C7_BASE_ADDR)
685 #define I2C7_BASE_ADDR 0
688 #if !defined(I2C8_BASE_ADDR)
689 #define I2C8_BASE_ADDR 0
692 static struct mxc_i2c_bus mxc_i2c_buses[] = {
693 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
694 defined(CONFIG_FSL_LAYERSCAPE)
695 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
696 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
697 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
698 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
699 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
700 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
701 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
702 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
704 { 0, I2C1_BASE_ADDR, 0 },
705 { 1, I2C2_BASE_ADDR, 0 },
706 { 2, I2C3_BASE_ADDR, 0 },
707 { 3, I2C4_BASE_ADDR, 0 },
708 { 4, I2C5_BASE_ADDR, 0 },
709 { 5, I2C6_BASE_ADDR, 0 },
710 { 6, I2C7_BASE_ADDR, 0 },
711 { 7, I2C8_BASE_ADDR, 0 },
715 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
717 return &mxc_i2c_buses[adap->hwadapnr];
720 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
721 uint addr, int alen, uint8_t *buffer,
724 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
727 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
728 uint addr, int alen, uint8_t *buffer,
731 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
735 * Test if a chip at a given address responds (probe the chip)
737 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
739 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
742 void bus_i2c_init(int index, int speed, int unused,
743 int (*idle_bus_fn)(void *p), void *idle_bus_data)
747 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
748 debug("Error i2c index\n");
752 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
753 if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
754 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
755 (ulong)mxc_i2c_buses[index].base);
761 * Warning: Be careful to allow the assignment to a static
762 * variable here. This function could be called while U-Boot is
763 * still running in flash memory. So such assignment is equal
764 * to write data to flash without erasing.
767 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
769 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
771 ret = enable_i2c_clk(1, index);
773 debug("I2C-%d clk fail to enable.\n", index);
777 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
781 * Early init I2C for prepare read the clk through I2C.
783 void i2c_early_init_f(void)
785 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
786 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
787 & I2C_QUIRK_FLAG ? true : false;
788 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
790 /* Set I2C divider value */
791 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
793 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
794 writeb(0, base + (I2SR << reg_shift));
796 writeb(I2CR_IEN, base + (I2CR << reg_shift));
802 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
804 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
810 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
812 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
816 * Register mxc i2c adapters
818 #ifdef CONFIG_SYS_I2C_MXC_I2C1
819 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
820 mxc_i2c_read, mxc_i2c_write,
821 mxc_i2c_set_bus_speed,
822 CONFIG_SYS_MXC_I2C1_SPEED,
823 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
826 #ifdef CONFIG_SYS_I2C_MXC_I2C2
827 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
828 mxc_i2c_read, mxc_i2c_write,
829 mxc_i2c_set_bus_speed,
830 CONFIG_SYS_MXC_I2C2_SPEED,
831 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
834 #ifdef CONFIG_SYS_I2C_MXC_I2C3
835 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
836 mxc_i2c_read, mxc_i2c_write,
837 mxc_i2c_set_bus_speed,
838 CONFIG_SYS_MXC_I2C3_SPEED,
839 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
842 #ifdef CONFIG_SYS_I2C_MXC_I2C4
843 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
844 mxc_i2c_read, mxc_i2c_write,
845 mxc_i2c_set_bus_speed,
846 CONFIG_SYS_MXC_I2C4_SPEED,
847 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
850 #ifdef CONFIG_SYS_I2C_MXC_I2C5
851 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
852 mxc_i2c_read, mxc_i2c_write,
853 mxc_i2c_set_bus_speed,
854 CONFIG_SYS_MXC_I2C5_SPEED,
855 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
858 #ifdef CONFIG_SYS_I2C_MXC_I2C6
859 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
860 mxc_i2c_read, mxc_i2c_write,
861 mxc_i2c_set_bus_speed,
862 CONFIG_SYS_MXC_I2C6_SPEED,
863 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
866 #ifdef CONFIG_SYS_I2C_MXC_I2C7
867 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
868 mxc_i2c_read, mxc_i2c_write,
869 mxc_i2c_set_bus_speed,
870 CONFIG_SYS_MXC_I2C7_SPEED,
871 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
874 #ifdef CONFIG_SYS_I2C_MXC_I2C8
875 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
876 mxc_i2c_read, mxc_i2c_write,
877 mxc_i2c_set_bus_speed,
878 CONFIG_SYS_MXC_I2C8_SPEED,
879 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
884 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
886 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
888 return bus_i2c_set_bus_speed(i2c_bus, speed);
891 static int mxc_i2c_probe(struct udevice *bus)
893 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
894 const void *fdt = gd->fdt_blob;
895 int node = dev_of_offset(bus);
899 i2c_bus->driver_data = dev_get_driver_data(bus);
901 addr = devfdt_get_addr(bus);
902 if (addr == FDT_ADDR_T_NONE)
905 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
906 if (i2c_fused((ulong)addr)) {
907 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
913 i2c_bus->base = addr;
914 i2c_bus->index = bus->seq;
918 #if CONFIG_IS_ENABLED(CLK)
919 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
921 printf("Failed to get i2c clk\n");
924 ret = clk_enable(&i2c_bus->per_clk);
926 printf("Failed to enable i2c clk\n");
930 ret = enable_i2c_clk(1, bus->seq);
936 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
937 * Use gpio to force bus idle when necessary.
939 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
941 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
943 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
944 "scl-gpios", 0, &i2c_bus->scl_gpio,
946 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
947 "sda-gpios", 0, &i2c_bus->sda_gpio,
949 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
950 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
952 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
958 * Pinmux settings are in board file now, until pinmux is supported,
959 * we can set pinmux here in probe function.
962 debug("i2c : controller bus %d at %lu , speed %d: ",
963 bus->seq, i2c_bus->base,
969 /* Sends: S Addr Wr [A|NA] P */
970 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
974 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
976 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
978 debug("%s failed, ret = %d\n", __func__, ret);
982 i2c_imx_stop(i2c_bus);
987 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
989 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
991 ulong base = i2c_bus->base;
992 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
993 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
996 /* Here address len is set to -1 to not send any address at first.
997 * Otherwise i2c_init_transfer will send the chip address with write
998 * mode set. This is wrong if the 1st message is read.
1000 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
1002 debug("i2c_init_transfer error: %d\n", ret);
1006 read_mode = -1; /* So it's always different on the first message */
1007 for (; nmsgs > 0; nmsgs--, msg++) {
1008 const int msg_is_read = !!(msg->flags & I2C_M_RD);
1010 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
1011 msg->len, msg_is_read ? 'R' : 'W');
1013 if (msg_is_read != read_mode) {
1014 /* Send repeated start if not 1st message */
1015 if (read_mode != -1) {
1016 debug("i2c_xfer: [RSTART]\n");
1017 ret = readb(base + (I2CR << reg_shift));
1019 writeb(ret, base + (I2CR << reg_shift));
1021 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1022 msg_is_read ? 'R' : 'W');
1023 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1025 debug("i2c_xfer: [STOP]\n");
1026 i2c_imx_stop(i2c_bus);
1029 read_mode = msg_is_read;
1032 if (msg->flags & I2C_M_RD)
1033 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1034 msg->len, nmsgs == 1 ||
1035 (msg->flags & I2C_M_STOP));
1037 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1045 debug("i2c_write: error sending\n");
1047 i2c_imx_stop(i2c_bus);
1052 static const struct dm_i2c_ops mxc_i2c_ops = {
1053 .xfer = mxc_i2c_xfer,
1054 .probe_chip = mxc_i2c_probe_chip,
1055 .set_bus_speed = mxc_i2c_set_bus_speed,
1058 static const struct udevice_id mxc_i2c_ids[] = {
1059 { .compatible = "fsl,imx21-i2c", },
1060 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1064 U_BOOT_DRIVER(i2c_mxc) = {
1067 .of_match = mxc_i2c_ids,
1068 .probe = mxc_i2c_probe,
1069 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
1070 .ops = &mxc_i2c_ops,
1071 .flags = DM_FLAG_PRE_RELOC,