drivers/i2c/kona_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Broadcom Corporation.
   4  *
   5  * NOTE: This driver should be converted to driver model before June 2017.
   6  * Please see doc/driver-model/i2c-howto.rst for instructions.
   7  */
   8
   9 #include <common.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <linux/errno.h>
  13 #include <asm/arch/sysmap.h>
  14 #include <asm/kona-common/clk.h>
  15 #include <i2c.h>
  16
  17 /* Hardware register offsets and field defintions */
  18 #define CS_OFFSET                               0x00000020
  19 #define CS_ACK_SHIFT                            3
  20 #define CS_ACK_MASK                             0x00000008
  21 #define CS_ACK_CMD_GEN_START                    0x00000000
  22 #define CS_ACK_CMD_GEN_RESTART                  0x00000001
  23 #define CS_CMD_SHIFT                            1
  24 #define CS_CMD_CMD_NO_ACTION                    0x00000000
  25 #define CS_CMD_CMD_START_RESTART                0x00000001
  26 #define CS_CMD_CMD_STOP                         0x00000002
  27 #define CS_EN_SHIFT                             0
  28 #define CS_EN_CMD_ENABLE_BSC                    0x00000001
  29
  30 #define TIM_OFFSET                              0x00000024
  31 #define TIM_PRESCALE_SHIFT                      6
  32 #define TIM_P_SHIFT                             3
  33 #define TIM_NO_DIV_SHIFT                        2
  34 #define TIM_DIV_SHIFT                           0
  35
  36 #define DAT_OFFSET                              0x00000028
  37
  38 #define TOUT_OFFSET                             0x0000002c
  39
  40 #define TXFCR_OFFSET                            0x0000003c
  41 #define TXFCR_FIFO_FLUSH_MASK                   0x00000080
  42 #define TXFCR_FIFO_EN_MASK                      0x00000040
  43
  44 #define IER_OFFSET                              0x00000044
  45 #define IER_READ_COMPLETE_INT_MASK              0x00000010
  46 #define IER_I2C_INT_EN_MASK                     0x00000008
  47 #define IER_FIFO_INT_EN_MASK                    0x00000002
  48 #define IER_NOACK_EN_MASK                       0x00000001
  49
  50 #define ISR_OFFSET                              0x00000048
  51 #define ISR_RESERVED_MASK                       0xffffff60
  52 #define ISR_CMDBUSY_MASK                        0x00000080
  53 #define ISR_READ_COMPLETE_MASK                  0x00000010
  54 #define ISR_SES_DONE_MASK                       0x00000008
  55 #define ISR_ERR_MASK                            0x00000004
  56 #define ISR_TXFIFOEMPTY_MASK                    0x00000002
  57 #define ISR_NOACK_MASK                          0x00000001
  58
  59 #define CLKEN_OFFSET                            0x0000004c
  60 #define CLKEN_AUTOSENSE_OFF_MASK                0x00000080
  61 #define CLKEN_M_SHIFT                           4
  62 #define CLKEN_N_SHIFT                           1
  63 #define CLKEN_CLKEN_MASK                        0x00000001
  64
  65 #define FIFO_STATUS_OFFSET                      0x00000054
  66 #define FIFO_STATUS_RXFIFO_EMPTY_MASK           0x00000004
  67 #define FIFO_STATUS_TXFIFO_EMPTY_MASK           0x00000010
  68
  69 #define HSTIM_OFFSET                            0x00000058
  70 #define HSTIM_HS_MODE_MASK                      0x00008000
  71 #define HSTIM_HS_HOLD_SHIFT                     10
  72 #define HSTIM_HS_HIGH_PHASE_SHIFT               5
  73 #define HSTIM_HS_SETUP_SHIFT                    0
  74
  75 #define PADCTL_OFFSET                           0x0000005c
  76 #define PADCTL_PAD_OUT_EN_MASK                  0x00000004
  77
  78 #define RXFCR_OFFSET                            0x00000068
  79 #define RXFCR_NACK_EN_SHIFT                     7
  80 #define RXFCR_READ_COUNT_SHIFT                  0
  81 #define RXFIFORDOUT_OFFSET                      0x0000006c
  82
  83 /* Locally used constants */
  84 #define MAX_RX_FIFO_SIZE                64U     /* bytes */
  85 #define MAX_TX_FIFO_SIZE                64U     /* bytes */
  86
  87 #define I2C_TIMEOUT                     100000  /* usecs */
  88
  89 #define WAIT_INT_CHK                    100     /* usecs */
  90 #if I2C_TIMEOUT % WAIT_INT_CHK
  91 #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
  92 #endif
  93
  94 /* Operations that can be commanded to the controller */
  95 enum bcm_kona_cmd_t {
  96         BCM_CMD_NOACTION = 0,
  97         BCM_CMD_START,
  98         BCM_CMD_RESTART,
  99         BCM_CMD_STOP,
 100 };
 101
 102 /* Internal divider settings for standard mode, fast mode and fast mode plus */
 103 struct bus_speed_cfg {
 104         uint8_t time_m;         /* Number of cycles for setup time */
 105         uint8_t time_n;         /* Number of cycles for hold time */
 106         uint8_t prescale;       /* Prescale divider */
 107         uint8_t time_p;         /* Timing coefficient */
 108         uint8_t no_div;         /* Disable clock divider */
 109         uint8_t time_div;       /* Post-prescale divider */
 110 };
 111
 112 static const struct bus_speed_cfg std_cfg_table[] = {
 113         [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
 114         [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
 115         [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
 116 };
 117
 118 struct bcm_kona_i2c_dev {
 119         void *base;
 120         uint speed;
 121         const struct bus_speed_cfg *std_cfg;
 122 };
 123
 124 /* Keep these two defines in sync */
 125 #define DEF_SPD I2C_SPEED_STANDARD_RATE
 126 #define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD
 127
 128 #define DEF_DEVICE(num) \
 129 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
 130
 131 static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
 132 #ifdef CONFIG_SYS_I2C_BASE0
 133         DEF_DEVICE(0),
 134 #endif
 135 #ifdef CONFIG_SYS_I2C_BASE1
 136         DEF_DEVICE(1),
 137 #endif
 138 #ifdef CONFIG_SYS_I2C_BASE2
 139         DEF_DEVICE(2),
 140 #endif
 141 #ifdef CONFIG_SYS_I2C_BASE3
 142         DEF_DEVICE(3),
 143 #endif
 144 #ifdef CONFIG_SYS_I2C_BASE4
 145         DEF_DEVICE(4),
 146 #endif
 147 #ifdef CONFIG_SYS_I2C_BASE5
 148         DEF_DEVICE(5),
 149 #endif
 150 };
 151
 152 #define I2C_M_TEN       0x0010  /* ten bit address */
 153 #define I2C_M_RD        0x0001  /* read data */
 154 #define I2C_M_NOSTART   0x4000  /* no restart between msgs */
 155
 156 struct kona_i2c_msg {
 157         uint16_t addr;
 158         uint16_t flags;
 159         uint16_t len;
 160         uint8_t *buf;
 161 };
 162
 163 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
 164                                           enum bcm_kona_cmd_t cmd)
 165 {
 166         debug("%s, %d\n", __func__, cmd);
 167
 168         switch (cmd) {
 169         case BCM_CMD_NOACTION:
 170                 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
 171                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 172                        dev->base + CS_OFFSET);
 173                 break;
 174
 175         case BCM_CMD_START:
 176                 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
 177                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 178                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 179                        dev->base + CS_OFFSET);
 180                 break;
 181
 182         case BCM_CMD_RESTART:
 183                 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
 184                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 185                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 186                        dev->base + CS_OFFSET);
 187                 break;
 188
 189         case BCM_CMD_STOP:
 190                 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
 191                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 192                        dev->base + CS_OFFSET);
 193                 break;
 194
 195         default:
 196                 printf("Unknown command %d\n", cmd);
 197         }
 198 }
 199
 200 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
 201 {
 202         writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
 203                dev->base + CLKEN_OFFSET);
 204 }
 205
 206 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
 207 {
 208         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
 209                dev->base + CLKEN_OFFSET);
 210 }
 211
 212 /* Wait until at least one of the mask bit(s) are set */
 213 static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
 214                                           unsigned long time_left,
 215                                           uint32_t mask)
 216 {
 217         uint32_t status;
 218
 219         while (time_left) {
 220                 status = readl(dev->base + ISR_OFFSET);
 221
 222                 if ((status & ~ISR_RESERVED_MASK) == 0) {
 223                         debug("Bogus I2C interrupt 0x%x\n", status);
 224                         continue;
 225                 }
 226
 227                 /* Must flush the TX FIFO when NAK detected */
 228                 if (status & ISR_NOACK_MASK)
 229                         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 230                                dev->base + TXFCR_OFFSET);
 231
 232                 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
 233
 234                 if (status & mask) {
 235                         /* We are done since one of the mask bits are set */
 236                         return time_left;
 237                 }
 238                 udelay(WAIT_INT_CHK);
 239                 time_left -= WAIT_INT_CHK;
 240         }
 241         return 0;
 242 }
 243
 244 /* Send command to I2C bus */
 245 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
 246                                  enum bcm_kona_cmd_t cmd)
 247 {
 248         int rc = 0;
 249         unsigned long time_left = I2C_TIMEOUT;
 250
 251         /* Send the command */
 252         bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
 253
 254         /* Wait for transaction to finish or timeout */
 255         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 256
 257         if (!time_left) {
 258                 printf("controller timed out\n");
 259                 rc = -ETIMEDOUT;
 260         }
 261
 262         /* Clear command */
 263         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 264
 265         return rc;
 266 }
 267
 268 /* Read a single RX FIFO worth of data from the i2c bus */
 269 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
 270                                          uint8_t *buf, unsigned int len,
 271                                          unsigned int last_byte_nak)
 272 {
 273         unsigned long time_left = I2C_TIMEOUT;
 274
 275         /* Start the RX FIFO */
 276         writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
 277                (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
 278
 279         /* Wait for FIFO read to complete */
 280         time_left =
 281             wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
 282
 283         if (!time_left) {
 284                 printf("RX FIFO time out\n");
 285                 return -EREMOTEIO;
 286         }
 287
 288         /* Read data from FIFO */
 289         for (; len > 0; len--, buf++)
 290                 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
 291
 292         return 0;
 293 }
 294
 295 /* Read any amount of data using the RX FIFO from the i2c bus */
 296 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
 297                                   struct kona_i2c_msg *msg)
 298 {
 299         unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
 300         unsigned int last_byte_nak = 0;
 301         unsigned int bytes_read = 0;
 302         int rc;
 303
 304         uint8_t *tmp_buf = msg->buf;
 305
 306         while (bytes_read < msg->len) {
 307                 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
 308                         last_byte_nak = 1;      /* NAK last byte of transfer */
 309                         bytes_to_read = msg->len - bytes_read;
 310                 }
 311
 312                 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
 313                                                    last_byte_nak);
 314                 if (rc < 0)
 315                         return -EREMOTEIO;
 316
 317                 bytes_read += bytes_to_read;
 318                 tmp_buf += bytes_to_read;
 319         }
 320
 321         return 0;
 322 }
 323
 324 /* Write a single byte of data to the i2c bus */
 325 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
 326                                    unsigned int nak_expected)
 327 {
 328         unsigned long time_left = I2C_TIMEOUT;
 329         unsigned int nak_received;
 330
 331         /* Clear pending session done interrupt */
 332         writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
 333
 334         /* Send one byte of data */
 335         writel(data, dev->base + DAT_OFFSET);
 336
 337         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 338
 339         if (!time_left) {
 340                 debug("controller timed out\n");
 341                 return -ETIMEDOUT;
 342         }
 343
 344         nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
 345
 346         if (nak_received ^ nak_expected) {
 347                 debug("unexpected NAK/ACK\n");
 348                 return -EREMOTEIO;
 349         }
 350
 351         return 0;
 352 }
 353
 354 /* Write a single TX FIFO worth of data to the i2c bus */
 355 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
 356                                           uint8_t *buf, unsigned int len)
 357 {
 358         int k;
 359         unsigned long time_left = I2C_TIMEOUT;
 360         unsigned int fifo_status;
 361
 362         /* Write data into FIFO */
 363         for (k = 0; k < len; k++)
 364                 writel(buf[k], (dev->base + DAT_OFFSET));
 365
 366         /* Wait for FIFO to empty */
 367         do {
 368                 time_left =
 369                     wait_for_int_timeout(dev, time_left,
 370                                          (IER_FIFO_INT_EN_MASK |
 371                                           IER_NOACK_EN_MASK));
 372                 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
 373         } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
 374
 375         /* Check if there was a NAK */
 376         if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
 377                 printf("unexpected NAK\n");
 378                 return -EREMOTEIO;
 379         }
 380
 381         /* Check if a timeout occurred */
 382         if (!time_left) {
 383                 printf("completion timed out\n");
 384                 return -EREMOTEIO;
 385         }
 386
 387         return 0;
 388 }
 389
 390 /* Write any amount of data using TX FIFO to the i2c bus */
 391 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
 392                                    struct kona_i2c_msg *msg)
 393 {
 394         unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
 395         unsigned int bytes_written = 0;
 396         int rc;
 397
 398         uint8_t *tmp_buf = msg->buf;
 399
 400         while (bytes_written < msg->len) {
 401                 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
 402                         bytes_to_write = msg->len - bytes_written;
 403
 404                 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
 405                                                     bytes_to_write);
 406                 if (rc < 0)
 407                         return -EREMOTEIO;
 408
 409                 bytes_written += bytes_to_write;
 410                 tmp_buf += bytes_to_write;
 411         }
 412
 413         return 0;
 414 }
 415
 416 /* Send i2c address */
 417 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
 418                                 struct kona_i2c_msg *msg)
 419 {
 420         unsigned char addr;
 421
 422         if (msg->flags & I2C_M_TEN) {
 423                 /* First byte is 11110XX0 where XX is upper 2 bits */
 424                 addr = 0xf0 | ((msg->addr & 0x300) >> 7);
 425                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 426                         return -EREMOTEIO;
 427
 428                 /* Second byte is the remaining 8 bits */
 429                 addr = msg->addr & 0xff;
 430                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 431                         return -EREMOTEIO;
 432
 433                 if (msg->flags & I2C_M_RD) {
 434                         /* For read, send restart command */
 435                         if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
 436                                 return -EREMOTEIO;
 437
 438                         /* Then re-send the first byte with the read bit set */
 439                         addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
 440                         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 441                                 return -EREMOTEIO;
 442                 }
 443         } else {
 444                 addr = msg->addr << 1;
 445
 446                 if (msg->flags & I2C_M_RD)
 447                         addr |= 1;
 448
 449                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 450                         return -EREMOTEIO;
 451         }
 452
 453         return 0;
 454 }
 455
 456 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
 457 {
 458         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
 459                dev->base + CLKEN_OFFSET);
 460 }
 461
 462 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
 463 {
 464         writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
 465                dev->base + HSTIM_OFFSET);
 466
 467         writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
 468                (dev->std_cfg->time_p << TIM_P_SHIFT) |
 469                (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
 470                (dev->std_cfg->time_div << TIM_DIV_SHIFT),
 471                dev->base + TIM_OFFSET);
 472
 473         writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
 474                (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
 475                CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
 476 }
 477
 478 /* Master transfer function */
 479 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
 480                              struct kona_i2c_msg msgs[], int num)
 481 {
 482         struct kona_i2c_msg *pmsg;
 483         int rc = 0;
 484         int i;
 485
 486         /* Enable pad output */
 487         writel(0, dev->base + PADCTL_OFFSET);
 488
 489         /* Enable internal clocks */
 490         bcm_kona_i2c_enable_clock(dev);
 491
 492         /* Send start command */
 493         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
 494         if (rc < 0) {
 495                 printf("Start command failed rc = %d\n", rc);
 496                 goto xfer_disable_pad;
 497         }
 498
 499         /* Loop through all messages */
 500         for (i = 0; i < num; i++) {
 501                 pmsg = &msgs[i];
 502
 503                 /* Send restart for subsequent messages */
 504                 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
 505                         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
 506                         if (rc < 0) {
 507                                 printf("restart cmd failed rc = %d\n", rc);
 508                                 goto xfer_send_stop;
 509                         }
 510                 }
 511
 512                 /* Send slave address */
 513                 if (!(pmsg->flags & I2C_M_NOSTART)) {
 514                         rc = bcm_kona_i2c_do_addr(dev, pmsg);
 515                         if (rc < 0) {
 516                                 debug("NAK from addr %2.2x msg#%d rc = %d\n",
 517                                       pmsg->addr, i, rc);
 518                                 goto xfer_send_stop;
 519                         }
 520                 }
 521
 522                 /* Perform data transfer */
 523                 if (pmsg->flags & I2C_M_RD) {
 524                         rc = bcm_kona_i2c_read_fifo(dev, pmsg);
 525                         if (rc < 0) {
 526                                 printf("read failure\n");
 527                                 goto xfer_send_stop;
 528                         }
 529                 } else {
 530                         rc = bcm_kona_i2c_write_fifo(dev, pmsg);
 531                         if (rc < 0) {
 532                                 printf("write failure");
 533                                 goto xfer_send_stop;
 534                         }
 535                 }
 536         }
 537
 538         rc = num;
 539
 540 xfer_send_stop:
 541         /* Send a STOP command */
 542         bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
 543
 544 xfer_disable_pad:
 545         /* Disable pad output */
 546         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 547
 548         /* Stop internal clock */
 549         bcm_kona_i2c_disable_clock(dev);
 550
 551         return rc;
 552 }
 553
 554 static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
 555                                           uint speed)
 556 {
 557         switch (speed) {
 558         case I2C_SPEED_STANDARD_RATE:
 559                 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD];
 560                 break;
 561         case I2C_SPEED_FAST_RATE:
 562                 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST];
 563                 break;
 564         case I2C_SPEED_FAST_PLUS_RATE:
 565                 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS];
 566                 break;
 567         default:
 568                 printf("%d hz bus speed not supported\n", speed);
 569                 return -EINVAL;
 570         }
 571         dev->speed = speed;
 572         return 0;
 573 }
 574
 575 static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
 576 {
 577         /* Parse bus speed */
 578         bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
 579
 580         /* Enable internal clocks */
 581         bcm_kona_i2c_enable_clock(dev);
 582
 583         /* Configure internal dividers */
 584         bcm_kona_i2c_config_timing(dev);
 585
 586         /* Disable timeout */
 587         writel(0, dev->base + TOUT_OFFSET);
 588
 589         /* Enable autosense */
 590         bcm_kona_i2c_enable_autosense(dev);
 591
 592         /* Enable TX FIFO */
 593         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 594                dev->base + TXFCR_OFFSET);
 595
 596         /* Mask all interrupts */
 597         writel(0, dev->base + IER_OFFSET);
 598
 599         /* Clear all pending interrupts */
 600         writel(ISR_CMDBUSY_MASK |
 601                ISR_READ_COMPLETE_MASK |
 602                ISR_SES_DONE_MASK |
 603                ISR_ERR_MASK |
 604                ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
 605
 606         /* Enable the controller but leave it idle */
 607         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 608
 609         /* Disable pad output */
 610         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 611 }
 612
 613 /*
 614  * uboot layer
 615  */
 616 struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
 617 {
 618         return &g_i2c_devs[adap->hwadapnr];
 619 }
 620
 621 static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 622 {
 623         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 624
 625         if (clk_bsc_enable(dev->base))
 626                 return;
 627
 628         bcm_kona_i2c_init(dev);
 629 }
 630
 631 static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 632                          int alen, uchar *buffer, int len)
 633 {
 634         /* msg[0] writes the addr, msg[1] reads the data */
 635         struct kona_i2c_msg msg[2];
 636         unsigned char msgbuf0[64];
 637         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 638
 639         msg[0].addr = chip;
 640         msg[0].flags = 0;
 641         msg[0].len = 1;
 642         msg[0].buf = msgbuf0;   /* msgbuf0 contains incrementing reg addr */
 643
 644         msg[1].addr = chip;
 645         msg[1].flags = I2C_M_RD;
 646         /* msg[1].buf dest ptr increments each read */
 647
 648         msgbuf0[0] = (unsigned char)addr;
 649         msg[1].buf = buffer;
 650         msg[1].len = len;
 651         if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
 652                 /* Sending 2 i2c messages */
 653                 kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 654                 debug("I2C read: I/O error\n");
 655                 return -EIO;
 656         }
 657         return 0;
 658 }
 659
 660 static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 661                           int alen, uchar *buffer, int len)
 662 {
 663         struct kona_i2c_msg msg[1];
 664         unsigned char msgbuf0[64];
 665         unsigned int i;
 666         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 667
 668         msg[0].addr = chip;
 669         msg[0].flags = 0;
 670         msg[0].len = 2;         /* addr byte plus data */
 671         msg[0].buf = msgbuf0;
 672
 673         for (i = 0; i < len; i++) {
 674                 msgbuf0[0] = addr++;
 675                 msgbuf0[1] = buffer[i];
 676                 if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
 677                         kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 678                         debug("I2C write: I/O error\n");
 679                         return -EIO;
 680                 }
 681         }
 682         return 0;
 683 }
 684
 685 static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
 686 {
 687         uchar tmp;
 688
 689         /*
 690          * read addr 0x0 of the given chip.
 691          */
 692         return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
 693 }
 694
 695 static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 696 {
 697         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 698         return bcm_kona_i2c_assign_bus_speed(dev, speed);
 699 }
 700
 701 /*
 702  * Register kona i2c adapters. Keep the order below so
 703  * that the bus number matches the adapter number.
 704  */
 705 #define DEF_ADAPTER(num) \
 706 U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
 707                          kona_i2c_read, kona_i2c_write, \
 708                          kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
 709
 710 #ifdef CONFIG_SYS_I2C_BASE0
 711         DEF_ADAPTER(0)
 712 #endif
 713 #ifdef CONFIG_SYS_I2C_BASE1
 714         DEF_ADAPTER(1)
 715 #endif
 716 #ifdef CONFIG_SYS_I2C_BASE2
 717         DEF_ADAPTER(2)
 718 #endif
 719 #ifdef CONFIG_SYS_I2C_BASE3
 720         DEF_ADAPTER(3)
 721 #endif
 722 #ifdef CONFIG_SYS_I2C_BASE4
 723         DEF_ADAPTER(4)
 724 #endif
 725 #ifdef CONFIG_SYS_I2C_BASE5
 726         DEF_ADAPTER(5)
 727 #endif