drivers/i2c/ihs_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #ifdef CONFIG_DM_I2C
  10 #include <dm.h>
  11 #include <regmap.h>
  12 #else
  13 #include <gdsys_fpga.h>
  14 #endif
  15 #include <log.h>
  16 #include <asm/unaligned.h>
  17 #include <linux/delay.h>
  18
  19 #ifdef CONFIG_DM_I2C
  20 struct ihs_i2c_priv {
  21         uint speed;
  22         struct regmap *map;
  23 };
  24
  25 struct ihs_i2c_regs {
  26         u16 interrupt_status;
  27         u16 interrupt_enable_control;
  28         u16 write_mailbox_ext;
  29         u16 write_mailbox;
  30         u16 read_mailbox_ext;
  31         u16 read_mailbox;
  32 };
  33
  34 #define ihs_i2c_set(map, member, val) \
  35         regmap_set(map, struct ihs_i2c_regs, member, val)
  36
  37 #define ihs_i2c_get(map, member, valp) \
  38         regmap_get(map, struct ihs_i2c_regs, member, valp)
  39
  40 #else /* !CONFIG_DM_I2C */
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  44
  45 #define I2C_SET_REG(fld, val) \
  46         do { \
  47                 if (I2C_ADAP_HWNR & 0x10) \
  48                         FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  49                 else \
  50                         FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  51         } while (0)
  52 #else
  53 #define I2C_SET_REG(fld, val) \
  54                 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  55 #endif
  56
  57 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  58 #define I2C_GET_REG(fld, val) \
  59         do {                                    \
  60                 if (I2C_ADAP_HWNR & 0x10) \
  61                         FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  62                 else \
  63                         FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  64         } while (0)
  65 #else
  66 #define I2C_GET_REG(fld, val) \
  67                 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  68 #endif
  69 #endif /* CONFIG_DM_I2C */
  70
  71 enum {
  72         I2CINT_ERROR_EV = BIT(13),
  73         I2CINT_TRANSMIT_EV = BIT(14),
  74         I2CINT_RECEIVE_EV = BIT(15),
  75 };
  76
  77 enum {
  78         I2CMB_READ = 0 << 10,
  79         I2CMB_WRITE = 1 << 10,
  80         I2CMB_1BYTE = 0 << 11,
  81         I2CMB_2BYTE = 1 << 11,
  82         I2CMB_DONT_HOLD_BUS = 0 << 13,
  83         I2CMB_HOLD_BUS = 1 << 13,
  84         I2CMB_NATIVE = 2 << 14,
  85 };
  86
  87 enum {
  88         I2COP_WRITE = 0,
  89         I2COP_READ = 1,
  90 };
  91
  92 #ifdef CONFIG_DM_I2C
  93 static int wait_for_int(struct udevice *dev, int read)
  94 #else
  95 static int wait_for_int(bool read)
  96 #endif
  97 {
  98         u16 val;
  99         uint ctr = 0;
 100 #ifdef CONFIG_DM_I2C
 101         struct ihs_i2c_priv *priv = dev_get_priv(dev);
 102 #endif
 103
 104 #ifdef CONFIG_DM_I2C
 105         ihs_i2c_get(priv->map, interrupt_status, &val);
 106 #else
 107         I2C_GET_REG(interrupt_status, &val);
 108 #endif
 109         /* Wait until error or receive/transmit interrupt was raised */
 110         while (!(val & (I2CINT_ERROR_EV
 111                | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
 112                 udelay(10);
 113                 if (ctr++ > 5000) {
 114                         debug("%s: timed out\n", __func__);
 115                         return -ETIMEDOUT;
 116                 }
 117 #ifdef CONFIG_DM_I2C
 118                 ihs_i2c_get(priv->map, interrupt_status, &val);
 119 #else
 120                 I2C_GET_REG(interrupt_status, &val);
 121 #endif
 122         }
 123
 124         return (val & I2CINT_ERROR_EV) ? -EIO : 0;
 125 }
 126
 127 #ifdef CONFIG_DM_I2C
 128 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
 129                             uchar *buffer, int len, int read, bool is_last)
 130 #else
 131 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 132                             bool is_last)
 133 #endif
 134 {
 135         u16 val;
 136         u16 data;
 137         int res;
 138 #ifdef CONFIG_DM_I2C
 139         struct ihs_i2c_priv *priv = dev_get_priv(dev);
 140 #endif
 141
 142         /* Clear interrupt status */
 143         data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
 144 #ifdef CONFIG_DM_I2C
 145         ihs_i2c_set(priv->map, interrupt_status, data);
 146         ihs_i2c_get(priv->map, interrupt_status, &val);
 147 #else
 148         I2C_SET_REG(interrupt_status, data);
 149         I2C_GET_REG(interrupt_status, &val);
 150 #endif
 151
 152         /* If we want to write and have data, write the bytes to the mailbox */
 153         if (!read && len) {
 154                 val = buffer[0];
 155
 156                 if (len > 1)
 157                         val |= buffer[1] << 8;
 158 #ifdef CONFIG_DM_I2C
 159                 ihs_i2c_set(priv->map, write_mailbox_ext, val);
 160 #else
 161                 I2C_SET_REG(write_mailbox_ext, val);
 162 #endif
 163         }
 164
 165         data = I2CMB_NATIVE
 166                | (read ? 0 : I2CMB_WRITE)
 167                | (chip << 1)
 168                | ((len > 1) ? I2CMB_2BYTE : 0)
 169                | (is_last ? 0 : I2CMB_HOLD_BUS);
 170
 171 #ifdef CONFIG_DM_I2C
 172         ihs_i2c_set(priv->map, write_mailbox, data);
 173 #else
 174         I2C_SET_REG(write_mailbox, data);
 175 #endif
 176
 177 #ifdef CONFIG_DM_I2C
 178         res = wait_for_int(dev, read);
 179 #else
 180         res = wait_for_int(read);
 181 #endif
 182         if (res) {
 183                 if (res == -ETIMEDOUT)
 184                         debug("%s: time out while waiting for event\n", __func__);
 185
 186                 return res;
 187         }
 188
 189         /* If we want to read, get the bytes from the mailbox */
 190         if (read) {
 191 #ifdef CONFIG_DM_I2C
 192                 ihs_i2c_get(priv->map, read_mailbox_ext, &val);
 193 #else
 194                 I2C_GET_REG(read_mailbox_ext, &val);
 195 #endif
 196                 buffer[0] = val & 0xff;
 197                 if (len > 1)
 198                         buffer[1] = val >> 8;
 199         }
 200
 201         return 0;
 202 }
 203
 204 #ifdef CONFIG_DM_I2C
 205 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
 206 #else
 207 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
 208                                int read)
 209 #endif
 210 {
 211         int res;
 212
 213         while (len) {
 214                 int transfer = min(len, 2);
 215                 bool is_last = len <= transfer;
 216
 217 #ifdef CONFIG_DM_I2C
 218                 res = ihs_i2c_transfer(dev, chip, data, transfer, read,
 219                                        hold_bus ? false : is_last);
 220 #else
 221                 res = ihs_i2c_transfer(chip, data, transfer, read,
 222                                        hold_bus ? false : is_last);
 223 #endif
 224                 if (res)
 225                         return res;
 226
 227                 data += transfer;
 228                 len -= transfer;
 229         }
 230
 231         return 0;
 232 }
 233
 234 #ifdef CONFIG_DM_I2C
 235 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
 236                            bool hold_bus)
 237 #else
 238 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
 239 #endif
 240 {
 241 #ifdef CONFIG_DM_I2C
 242         return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
 243 #else
 244         return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
 245 #endif
 246 }
 247
 248 #ifdef CONFIG_DM_I2C
 249 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
 250                           int alen, uchar *buffer, int len, int read)
 251 #else
 252 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
 253                           int alen, uchar *buffer, int len, int read)
 254 #endif
 255 {
 256         int res;
 257
 258         /* Don't hold the bus if length of data to send/receive is zero */
 259         if (len <= 0)
 260                 return -EINVAL;
 261
 262 #ifdef CONFIG_DM_I2C
 263         res = ihs_i2c_address(dev, chip, addr, alen, len);
 264 #else
 265         res = ihs_i2c_address(chip, addr, alen, len);
 266 #endif
 267         if (res)
 268                 return res;
 269
 270 #ifdef CONFIG_DM_I2C
 271         return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
 272 #else
 273         return ihs_i2c_send_buffer(chip, buffer, len, false, read);
 274 #endif
 275 }
 276
 277 #ifdef CONFIG_DM_I2C
 278
 279 int ihs_i2c_probe(struct udevice *bus)
 280 {
 281         struct ihs_i2c_priv *priv = dev_get_priv(bus);
 282
 283         regmap_init_mem(dev_ofnode(bus), &priv->map);
 284
 285         return 0;
 286 }
 287
 288 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
 289 {
 290         struct ihs_i2c_priv *priv = dev_get_priv(bus);
 291
 292         if (speed != priv->speed && priv->speed != 0)
 293                 return -EINVAL;
 294
 295         priv->speed = speed;
 296
 297         return 0;
 298 }
 299
 300 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 301 {
 302         struct i2c_msg *dmsg, *omsg, dummy;
 303
 304         memset(&dummy, 0, sizeof(struct i2c_msg));
 305
 306         /* We expect either two messages (one with an offset and one with the
 307          * actucal data) or one message (just data)
 308          */
 309         if (nmsgs > 2 || nmsgs == 0) {
 310                 debug("%s: Only one or two messages are supported\n", __func__);
 311                 return -ENOTSUPP;
 312         }
 313
 314         omsg = nmsgs == 1 ? &dummy : msg;
 315         dmsg = nmsgs == 1 ? msg : msg + 1;
 316
 317         if (dmsg->flags & I2C_M_RD)
 318                 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
 319                                       omsg->len, dmsg->buf, dmsg->len,
 320                                       I2COP_READ);
 321         else
 322                 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
 323                                       omsg->len, dmsg->buf, dmsg->len,
 324                                       I2COP_WRITE);
 325 }
 326
 327 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 328                               u32 chip_flags)
 329 {
 330         uchar buffer[2];
 331         int res;
 332
 333         res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
 334         if (res)
 335                 return res;
 336
 337         return 0;
 338 }
 339
 340 static const struct dm_i2c_ops ihs_i2c_ops = {
 341         .xfer           = ihs_i2c_xfer,
 342         .probe_chip     = ihs_i2c_probe_chip,
 343         .set_bus_speed  = ihs_i2c_set_bus_speed,
 344 };
 345
 346 static const struct udevice_id ihs_i2c_ids[] = {
 347         { .compatible = "gdsys,ihs_i2cmaster", },
 348         { /* sentinel */ }
 349 };
 350
 351 U_BOOT_DRIVER(i2c_ihs) = {
 352         .name = "i2c_ihs",
 353         .id = UCLASS_I2C,
 354         .of_match = ihs_i2c_ids,
 355         .probe = ihs_i2c_probe,
 356         .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
 357         .ops = &ihs_i2c_ops,
 358 };
 359
 360 #else /* CONFIG_DM_I2C */
 361
 362 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 363 {
 364 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 365         /*
 366          * Call board specific i2c bus reset routine before accessing the
 367          * environment, which might be in a chip on that bus. For details
 368          * about this problem see doc/I2C_Edge_Conditions.
 369          */
 370         i2c_init_board();
 371 #endif
 372 }
 373
 374 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
 375 {
 376         uchar buffer[2];
 377         int res;
 378
 379         res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
 380         if (res)
 381                 return res;
 382
 383         return 0;
 384 }
 385
 386 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 387                         int alen, uchar *buffer, int len)
 388 {
 389         u8 addr_bytes[4];
 390
 391         put_unaligned_le32(addr, addr_bytes);
 392
 393         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 394                               I2COP_READ);
 395 }
 396
 397 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 398                          int alen, uchar *buffer, int len)
 399 {
 400         u8 addr_bytes[4];
 401
 402         put_unaligned_le32(addr, addr_bytes);
 403
 404         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 405                               I2COP_WRITE);
 406 }
 407
 408 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
 409                                           unsigned int speed)
 410 {
 411         if (speed != adap->speed)
 412                 return -EINVAL;
 413         return speed;
 414 }
 415
 416 /*
 417  * Register IHS i2c adapters
 418  */
 419 #ifdef CONFIG_SYS_I2C_IHS_CH0
 420 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
 421                          ihs_i2c_read, ihs_i2c_write,
 422                          ihs_i2c_set_bus_speed,
 423                          CONFIG_SYS_I2C_IHS_SPEED_0,
 424                          CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
 425 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 426 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
 427                          ihs_i2c_read, ihs_i2c_write,
 428                          ihs_i2c_set_bus_speed,
 429                          CONFIG_SYS_I2C_IHS_SPEED_0_1,
 430                          CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
 431 #endif
 432 #endif
 433 #ifdef CONFIG_SYS_I2C_IHS_CH1
 434 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
 435                          ihs_i2c_read, ihs_i2c_write,
 436                          ihs_i2c_set_bus_speed,
 437                          CONFIG_SYS_I2C_IHS_SPEED_1,
 438                          CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
 439 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 440 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
 441                          ihs_i2c_read, ihs_i2c_write,
 442                          ihs_i2c_set_bus_speed,
 443                          CONFIG_SYS_I2C_IHS_SPEED_1_1,
 444                          CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
 445 #endif
 446 #endif
 447 #ifdef CONFIG_SYS_I2C_IHS_CH2
 448 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
 449                          ihs_i2c_read, ihs_i2c_write,
 450                          ihs_i2c_set_bus_speed,
 451                          CONFIG_SYS_I2C_IHS_SPEED_2,
 452                          CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
 453 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 454 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
 455                          ihs_i2c_read, ihs_i2c_write,
 456                          ihs_i2c_set_bus_speed,
 457                          CONFIG_SYS_I2C_IHS_SPEED_2_1,
 458                          CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
 459 #endif
 460 #endif
 461 #ifdef CONFIG_SYS_I2C_IHS_CH3
 462 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
 463                          ihs_i2c_read, ihs_i2c_write,
 464                          ihs_i2c_set_bus_speed,
 465                          CONFIG_SYS_I2C_IHS_SPEED_3,
 466                          CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
 467 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 468 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
 469                          ihs_i2c_read, ihs_i2c_write,
 470                          ihs_i2c_set_bus_speed,
 471                          CONFIG_SYS_I2C_IHS_SPEED_3_1,
 472                          CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
 473 #endif
 474 #endif
 475 #endif /* CONFIG_DM_I2C */