drivers/i2c/i2c-cdns.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
   4  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   5  *
   6  * This file is based on: drivers/i2c/zynq_i2c.c,
   7  * with added driver-model support and code cleanup.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <log.h>
  13 #include <linux/types.h>
  14 #include <linux/io.h>
  15 #include <linux/errno.h>
  16 #include <dm/root.h>
  17 #include <i2c.h>
  18 #include <fdtdec.h>
  19 #include <mapmem.h>
  20 #include <wait_bit.h>
  21 #include <clk.h>
  22
  23 /* i2c register set */
  24 struct cdns_i2c_regs {
  25         u32 control;
  26         u32 status;
  27         u32 address;
  28         u32 data;
  29         u32 interrupt_status;
  30         u32 transfer_size;
  31         u32 slave_mon_pause;
  32         u32 time_out;
  33         u32 interrupt_mask;
  34         u32 interrupt_enable;
  35         u32 interrupt_disable;
  36 };
  37
  38 /* Control register fields */
  39 #define CDNS_I2C_CONTROL_RW             0x00000001
  40 #define CDNS_I2C_CONTROL_MS             0x00000002
  41 #define CDNS_I2C_CONTROL_NEA            0x00000004
  42 #define CDNS_I2C_CONTROL_ACKEN          0x00000008
  43 #define CDNS_I2C_CONTROL_HOLD           0x00000010
  44 #define CDNS_I2C_CONTROL_SLVMON         0x00000020
  45 #define CDNS_I2C_CONTROL_CLR_FIFO       0x00000040
  46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT    8
  47 #define CDNS_I2C_CONTROL_DIV_B_MASK     0x00003F00
  48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT    14
  49 #define CDNS_I2C_CONTROL_DIV_A_MASK     0x0000C000
  50
  51 /* Status register values */
  52 #define CDNS_I2C_STATUS_RXDV    0x00000020
  53 #define CDNS_I2C_STATUS_TXDV    0x00000040
  54 #define CDNS_I2C_STATUS_RXOVF   0x00000080
  55 #define CDNS_I2C_STATUS_BA      0x00000100
  56
  57 /* Interrupt register fields */
  58 #define CDNS_I2C_INTERRUPT_COMP         0x00000001
  59 #define CDNS_I2C_INTERRUPT_DATA         0x00000002
  60 #define CDNS_I2C_INTERRUPT_NACK         0x00000004
  61 #define CDNS_I2C_INTERRUPT_TO           0x00000008
  62 #define CDNS_I2C_INTERRUPT_SLVRDY       0x00000010
  63 #define CDNS_I2C_INTERRUPT_RXOVF        0x00000020
  64 #define CDNS_I2C_INTERRUPT_TXOVF        0x00000040
  65 #define CDNS_I2C_INTERRUPT_RXUNF        0x00000080
  66 #define CDNS_I2C_INTERRUPT_ARBLOST      0x00000200
  67
  68 #define CDNS_I2C_INTERRUPTS_MASK        (CDNS_I2C_INTERRUPT_COMP | \
  69                                         CDNS_I2C_INTERRUPT_DATA | \
  70                                         CDNS_I2C_INTERRUPT_NACK | \
  71                                         CDNS_I2C_INTERRUPT_TO | \
  72                                         CDNS_I2C_INTERRUPT_SLVRDY | \
  73                                         CDNS_I2C_INTERRUPT_RXOVF | \
  74                                         CDNS_I2C_INTERRUPT_TXOVF | \
  75                                         CDNS_I2C_INTERRUPT_RXUNF | \
  76                                         CDNS_I2C_INTERRUPT_ARBLOST)
  77
  78 #define CDNS_I2C_FIFO_DEPTH             16
  79 #define CDNS_I2C_TRANSFER_SIZE_MAX      255 /* Controller transfer limit */
  80 #define CDNS_I2C_TRANSFER_SIZE          (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  81
  82 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
  83
  84 #define CDNS_I2C_ARB_LOST_MAX_RETRIES   10
  85
  86 #ifdef DEBUG
  87 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  88 {
  89         int int_status;
  90         int status;
  91         int_status = readl(&cdns_i2c->interrupt_status);
  92
  93         status = readl(&cdns_i2c->status);
  94         if (int_status || status) {
  95                 debug("Status: ");
  96                 if (int_status & CDNS_I2C_INTERRUPT_COMP)
  97                         debug("COMP ");
  98                 if (int_status & CDNS_I2C_INTERRUPT_DATA)
  99                         debug("DATA ");
 100                 if (int_status & CDNS_I2C_INTERRUPT_NACK)
 101                         debug("NACK ");
 102                 if (int_status & CDNS_I2C_INTERRUPT_TO)
 103                         debug("TO ");
 104                 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
 105                         debug("SLVRDY ");
 106                 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
 107                         debug("RXOVF ");
 108                 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
 109                         debug("TXOVF ");
 110                 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
 111                         debug("RXUNF ");
 112                 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
 113                         debug("ARBLOST ");
 114                 if (status & CDNS_I2C_STATUS_RXDV)
 115                         debug("RXDV ");
 116                 if (status & CDNS_I2C_STATUS_TXDV)
 117                         debug("TXDV ");
 118                 if (status & CDNS_I2C_STATUS_RXOVF)
 119                         debug("RXOVF ");
 120                 if (status & CDNS_I2C_STATUS_BA)
 121                         debug("BA ");
 122                 debug("TS%d ", readl(&cdns_i2c->transfer_size));
 123                 debug("\n");
 124         }
 125 }
 126 #endif
 127
 128 struct i2c_cdns_bus {
 129         int id;
 130         unsigned int input_freq;
 131         struct cdns_i2c_regs __iomem *regs;     /* register base */
 132
 133         int hold_flag;
 134         u32 quirks;
 135 };
 136
 137 struct cdns_i2c_platform_data {
 138         u32 quirks;
 139 };
 140
 141 /* Wait for an interrupt */
 142 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 143 {
 144         int timeout, int_status;
 145
 146         for (timeout = 0; timeout < 100; timeout++) {
 147                 int_status = readl(&cdns_i2c->interrupt_status);
 148                 if (int_status & mask)
 149                         break;
 150                 udelay(100);
 151         }
 152
 153         /* Clear interrupt status flags */
 154         writel(int_status & mask, &cdns_i2c->interrupt_status);
 155
 156         return int_status & mask;
 157 }
 158
 159 #define CDNS_I2C_DIVA_MAX       4
 160 #define CDNS_I2C_DIVB_MAX       64
 161
 162 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 163                 unsigned int *a, unsigned int *b)
 164 {
 165         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 166         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 167         unsigned int last_error, current_error;
 168
 169         /* calculate (divisor_a+1) x (divisor_b+1) */
 170         temp = input_clk / (22 * fscl);
 171
 172         /*
 173          * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
 174          * the fscl input is out of range. Return error.
 175          */
 176         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 177                 return -EINVAL;
 178
 179         last_error = -1;
 180         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 181                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 182
 183                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 184                         continue;
 185                 div_b--;
 186
 187                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 188
 189                 if (actual_fscl > fscl)
 190                         continue;
 191
 192                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 193                                                         (fscl - actual_fscl));
 194
 195                 if (last_error > current_error) {
 196                         calc_div_a = div_a;
 197                         calc_div_b = div_b;
 198                         best_fscl = actual_fscl;
 199                         last_error = current_error;
 200                 }
 201         }
 202
 203         *a = calc_div_a;
 204         *b = calc_div_b;
 205         *f = best_fscl;
 206
 207         return 0;
 208 }
 209
 210 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 211 {
 212         struct i2c_cdns_bus *bus = dev_get_priv(dev);
 213         u32 div_a = 0, div_b = 0;
 214         unsigned long speed_p = speed;
 215         int ret = 0;
 216
 217         if (speed > I2C_SPEED_FAST_RATE) {
 218                 debug("%s, failed to set clock speed to %u\n", __func__,
 219                       speed);
 220                 return -EINVAL;
 221         }
 222
 223         ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
 224         if (ret)
 225                 return ret;
 226
 227         debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
 228               __func__, div_a, div_b, bus->input_freq, speed, speed_p);
 229
 230         writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
 231                (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 232
 233         /* Enable master mode, ack, and 7-bit addressing */
 234         setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
 235                 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
 236
 237         return 0;
 238 }
 239
 240 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
 241 {
 242         return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
 243 }
 244
 245 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 246                                u32 len)
 247 {
 248         u8 *cur_data = data;
 249         struct cdns_i2c_regs *regs = i2c_bus->regs;
 250         u32 ret;
 251
 252         /* Set the controller in Master transmit mode and clear FIFO */
 253         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
 254         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
 255
 256         /* Check message size against FIFO depth, and set hold bus bit
 257          * if it is greater than FIFO depth
 258          */
 259         if (len > CDNS_I2C_FIFO_DEPTH)
 260                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 261
 262         /* Clear the interrupts in status register */
 263         writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
 264
 265         writel(addr, &regs->address);
 266
 267         while (len-- && !is_arbitration_lost(regs)) {
 268                 writel(*(cur_data++), &regs->data);
 269                 if (len && readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
 270                         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 271                                             CDNS_I2C_INTERRUPT_ARBLOST);
 272                         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 273                                 return -EAGAIN;
 274                         if (ret & CDNS_I2C_INTERRUPT_COMP)
 275                                 continue;
 276                         /* Release the bus */
 277                         clrbits_le32(&regs->control,
 278                                      CDNS_I2C_CONTROL_HOLD);
 279                         return -ETIMEDOUT;
 280                 }
 281         }
 282
 283         if (len && is_arbitration_lost(regs))
 284                 return -EAGAIN;
 285
 286         /* All done... release the bus */
 287         if (!i2c_bus->hold_flag)
 288                 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 289
 290         /* Wait for the address and data to be sent */
 291         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 292                             CDNS_I2C_INTERRUPT_ARBLOST);
 293         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 294                      CDNS_I2C_INTERRUPT_COMP)))
 295                 return -ETIMEDOUT;
 296         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 297                 return -EAGAIN;
 298
 299         return 0;
 300 }
 301
 302 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
 303 {
 304         return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
 305 }
 306
 307 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 308                               u32 recv_count)
 309 {
 310         u8 *cur_data = data;
 311         struct cdns_i2c_regs *regs = i2c_bus->regs;
 312         u32 curr_recv_count;
 313         int updatetx, hold_quirk;
 314         u32 ret;
 315
 316         curr_recv_count = recv_count;
 317
 318         /* Check for the message size against the FIFO depth */
 319         if (recv_count > CDNS_I2C_FIFO_DEPTH)
 320                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 321
 322         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 323                 CDNS_I2C_CONTROL_RW);
 324
 325         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 326                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 327                 writel(curr_recv_count, &regs->transfer_size);
 328         } else {
 329                 writel(recv_count, &regs->transfer_size);
 330         }
 331
 332         /* Start reading data */
 333         writel(addr, &regs->address);
 334
 335         updatetx = recv_count > curr_recv_count;
 336
 337         hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 338
 339         while (recv_count && !is_arbitration_lost(regs)) {
 340                 while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
 341                         if (recv_count < CDNS_I2C_FIFO_DEPTH &&
 342                             !i2c_bus->hold_flag) {
 343                                 clrbits_le32(&regs->control,
 344                                              CDNS_I2C_CONTROL_HOLD);
 345                         }
 346                         *(cur_data)++ = readl(&regs->data);
 347                         recv_count--;
 348                         curr_recv_count--;
 349
 350                         if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
 351                                 break;
 352                 }
 353
 354                 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
 355                         /* wait while fifo is full */
 356                         while (readl(&regs->transfer_size) !=
 357                                      (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 358                                 ;
 359                         /*
 360                          * Check number of bytes to be received against maximum
 361                          * transfer size and update register accordingly.
 362                          */
 363                         if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
 364                             CDNS_I2C_TRANSFER_SIZE) {
 365                                 writel(CDNS_I2C_TRANSFER_SIZE,
 366                                        &regs->transfer_size);
 367                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 368                                         CDNS_I2C_FIFO_DEPTH;
 369                         } else {
 370                                 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
 371                                        &regs->transfer_size);
 372                                 curr_recv_count = recv_count;
 373                         }
 374                 } else if (recv_count && !hold_quirk && !curr_recv_count) {
 375                         writel(addr, &regs->address);
 376                         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 377                                 writel(CDNS_I2C_TRANSFER_SIZE,
 378                                        &regs->transfer_size);
 379                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 380                         } else {
 381                                 writel(recv_count, &regs->transfer_size);
 382                                 curr_recv_count = recv_count;
 383                         }
 384                 }
 385         }
 386
 387         /* Wait for the address and data to be sent */
 388         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 389                             CDNS_I2C_INTERRUPT_ARBLOST);
 390         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 391                      CDNS_I2C_INTERRUPT_COMP)))
 392                 return -ETIMEDOUT;
 393         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 394                 return -EAGAIN;
 395
 396         return 0;
 397 }
 398
 399 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 400                          int nmsgs)
 401 {
 402         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 403         int ret = 0;
 404         int count;
 405         bool hold_quirk;
 406         struct i2c_msg *message = msg;
 407         int num_msgs = nmsgs;
 408
 409         hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 410
 411         if (nmsgs > 1) {
 412                 /*
 413                  * This controller does not give completion interrupt after a
 414                  * master receive message if HOLD bit is set (repeated start),
 415                  * resulting in SW timeout. Hence, if a receive message is
 416                  * followed by any other message, an error is returned
 417                  * indicating that this sequence is not supported.
 418                  */
 419                 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
 420                         if (msg[count].flags & I2C_M_RD) {
 421                                 printf("Can't do repeated start after a receive message\n");
 422                                 return -EOPNOTSUPP;
 423                         }
 424                 }
 425
 426                 i2c_bus->hold_flag = 1;
 427                 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
 428         } else {
 429                 i2c_bus->hold_flag = 0;
 430         }
 431
 432         debug("i2c_xfer: %d messages\n", nmsgs);
 433         for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
 434              nmsgs > 0; nmsgs--, msg++) {
 435                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 436                 if (msg->flags & I2C_M_RD) {
 437                         ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
 438                                                  msg->len);
 439                 } else {
 440                         ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
 441                                                   msg->len);
 442                 }
 443                 if (ret == -EAGAIN) {
 444                         msg = message;
 445                         nmsgs = num_msgs;
 446                         retry++;
 447                         printf("%s,arbitration lost, retrying:%d\n", __func__,
 448                                retry);
 449                         continue;
 450                 }
 451
 452                 if (ret) {
 453                         debug("i2c_write: error sending\n");
 454                         return -EREMOTEIO;
 455                 }
 456         }
 457
 458         return ret;
 459 }
 460
 461 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 462 {
 463         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 464         struct cdns_i2c_platform_data *pdata =
 465                 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
 466         struct clk clk;
 467         int ret;
 468
 469         i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
 470         if (!i2c_bus->regs)
 471                 return -ENOMEM;
 472
 473         if (pdata)
 474                 i2c_bus->quirks = pdata->quirks;
 475
 476         ret = clk_get_by_index(dev, 0, &clk);
 477         if (ret)
 478                 return ret;
 479
 480         i2c_bus->input_freq = clk_get_rate(&clk);
 481
 482         return 0;
 483 }
 484
 485 static const struct dm_i2c_ops cdns_i2c_ops = {
 486         .xfer = cdns_i2c_xfer,
 487         .set_bus_speed = cdns_i2c_set_bus_speed,
 488 };
 489
 490 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
 491         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
 492 };
 493
 494 static const struct udevice_id cdns_i2c_of_match[] = {
 495         { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
 496         { .compatible = "cdns,i2c-r1p14" },
 497         { /* end of table */ }
 498 };
 499
 500 U_BOOT_DRIVER(cdns_i2c) = {
 501         .name = "i2c-cdns",
 502         .id = UCLASS_I2C,
 503         .of_match = cdns_i2c_of_match,
 504         .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 505         .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 506         .ops = &cdns_i2c_ops,
 507 };