drivers/i2c/i2c-cdns.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
   4  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   5  *
   6  * This file is based on: drivers/i2c/zynq_i2c.c,
   7  * with added driver-model support and code cleanup.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <log.h>
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/types.h>
  16 #include <linux/io.h>
  17 #include <linux/errno.h>
  18 #include <dm/root.h>
  19 #include <i2c.h>
  20 #include <fdtdec.h>
  21 #include <mapmem.h>
  22 #include <wait_bit.h>
  23 #include <clk.h>
  24
  25 /* i2c register set */
  26 struct cdns_i2c_regs {
  27         u32 control;
  28         u32 status;
  29         u32 address;
  30         u32 data;
  31         u32 interrupt_status;
  32         u32 transfer_size;
  33         u32 slave_mon_pause;
  34         u32 time_out;
  35         u32 interrupt_mask;
  36         u32 interrupt_enable;
  37         u32 interrupt_disable;
  38 };
  39
  40 /* Control register fields */
  41 #define CDNS_I2C_CONTROL_RW             0x00000001
  42 #define CDNS_I2C_CONTROL_MS             0x00000002
  43 #define CDNS_I2C_CONTROL_NEA            0x00000004
  44 #define CDNS_I2C_CONTROL_ACKEN          0x00000008
  45 #define CDNS_I2C_CONTROL_HOLD           0x00000010
  46 #define CDNS_I2C_CONTROL_SLVMON         0x00000020
  47 #define CDNS_I2C_CONTROL_CLR_FIFO       0x00000040
  48 #define CDNS_I2C_CONTROL_DIV_B_SHIFT    8
  49 #define CDNS_I2C_CONTROL_DIV_B_MASK     0x00003F00
  50 #define CDNS_I2C_CONTROL_DIV_A_SHIFT    14
  51 #define CDNS_I2C_CONTROL_DIV_A_MASK     0x0000C000
  52
  53 /* Status register values */
  54 #define CDNS_I2C_STATUS_RXDV    0x00000020
  55 #define CDNS_I2C_STATUS_TXDV    0x00000040
  56 #define CDNS_I2C_STATUS_RXOVF   0x00000080
  57 #define CDNS_I2C_STATUS_BA      0x00000100
  58
  59 /* Interrupt register fields */
  60 #define CDNS_I2C_INTERRUPT_COMP         0x00000001
  61 #define CDNS_I2C_INTERRUPT_DATA         0x00000002
  62 #define CDNS_I2C_INTERRUPT_NACK         0x00000004
  63 #define CDNS_I2C_INTERRUPT_TO           0x00000008
  64 #define CDNS_I2C_INTERRUPT_SLVRDY       0x00000010
  65 #define CDNS_I2C_INTERRUPT_RXOVF        0x00000020
  66 #define CDNS_I2C_INTERRUPT_TXOVF        0x00000040
  67 #define CDNS_I2C_INTERRUPT_RXUNF        0x00000080
  68 #define CDNS_I2C_INTERRUPT_ARBLOST      0x00000200
  69
  70 #define CDNS_I2C_INTERRUPTS_MASK        (CDNS_I2C_INTERRUPT_COMP | \
  71                                         CDNS_I2C_INTERRUPT_DATA | \
  72                                         CDNS_I2C_INTERRUPT_NACK | \
  73                                         CDNS_I2C_INTERRUPT_TO | \
  74                                         CDNS_I2C_INTERRUPT_SLVRDY | \
  75                                         CDNS_I2C_INTERRUPT_RXOVF | \
  76                                         CDNS_I2C_INTERRUPT_TXOVF | \
  77                                         CDNS_I2C_INTERRUPT_RXUNF | \
  78                                         CDNS_I2C_INTERRUPT_ARBLOST)
  79
  80 #define CDNS_I2C_FIFO_DEPTH             16
  81 #define CDNS_I2C_TRANSFER_SIZE_MAX      255 /* Controller transfer limit */
  82 #define CDNS_I2C_TRANSFER_SIZE          (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  83
  84 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
  85
  86 #define CDNS_I2C_ARB_LOST_MAX_RETRIES   10
  87
  88 #ifdef DEBUG
  89 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  90 {
  91         int int_status;
  92         int status;
  93         int_status = readl(&cdns_i2c->interrupt_status);
  94
  95         status = readl(&cdns_i2c->status);
  96         if (int_status || status) {
  97                 debug("Status: ");
  98                 if (int_status & CDNS_I2C_INTERRUPT_COMP)
  99                         debug("COMP ");
 100                 if (int_status & CDNS_I2C_INTERRUPT_DATA)
 101                         debug("DATA ");
 102                 if (int_status & CDNS_I2C_INTERRUPT_NACK)
 103                         debug("NACK ");
 104                 if (int_status & CDNS_I2C_INTERRUPT_TO)
 105                         debug("TO ");
 106                 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
 107                         debug("SLVRDY ");
 108                 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
 109                         debug("RXOVF ");
 110                 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
 111                         debug("TXOVF ");
 112                 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
 113                         debug("RXUNF ");
 114                 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
 115                         debug("ARBLOST ");
 116                 if (status & CDNS_I2C_STATUS_RXDV)
 117                         debug("RXDV ");
 118                 if (status & CDNS_I2C_STATUS_TXDV)
 119                         debug("TXDV ");
 120                 if (status & CDNS_I2C_STATUS_RXOVF)
 121                         debug("RXOVF ");
 122                 if (status & CDNS_I2C_STATUS_BA)
 123                         debug("BA ");
 124                 debug("TS%d ", readl(&cdns_i2c->transfer_size));
 125                 debug("\n");
 126         }
 127 }
 128 #endif
 129
 130 struct i2c_cdns_bus {
 131         int id;
 132         unsigned int input_freq;
 133         struct cdns_i2c_regs __iomem *regs;     /* register base */
 134
 135         int hold_flag;
 136         u32 quirks;
 137 };
 138
 139 struct cdns_i2c_platform_data {
 140         u32 quirks;
 141 };
 142
 143 /* Wait for an interrupt */
 144 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 145 {
 146         int timeout, int_status;
 147
 148         for (timeout = 0; timeout < 100; timeout++) {
 149                 int_status = readl(&cdns_i2c->interrupt_status);
 150                 if (int_status & mask)
 151                         break;
 152                 udelay(100);
 153         }
 154
 155         /* Clear interrupt status flags */
 156         writel(int_status & mask, &cdns_i2c->interrupt_status);
 157
 158         return int_status & mask;
 159 }
 160
 161 #define CDNS_I2C_DIVA_MAX       4
 162 #define CDNS_I2C_DIVB_MAX       64
 163
 164 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 165                 unsigned int *a, unsigned int *b)
 166 {
 167         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 168         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 169         unsigned int last_error, current_error;
 170
 171         /* calculate (divisor_a+1) x (divisor_b+1) */
 172         temp = input_clk / (22 * fscl);
 173
 174         /*
 175          * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
 176          * the fscl input is out of range. Return error.
 177          */
 178         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 179                 return -EINVAL;
 180
 181         last_error = -1;
 182         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 183                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 184
 185                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 186                         continue;
 187                 div_b--;
 188
 189                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 190
 191                 if (actual_fscl > fscl)
 192                         continue;
 193
 194                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 195                                                         (fscl - actual_fscl));
 196
 197                 if (last_error > current_error) {
 198                         calc_div_a = div_a;
 199                         calc_div_b = div_b;
 200                         best_fscl = actual_fscl;
 201                         last_error = current_error;
 202                 }
 203         }
 204
 205         *a = calc_div_a;
 206         *b = calc_div_b;
 207         *f = best_fscl;
 208
 209         return 0;
 210 }
 211
 212 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 213 {
 214         struct i2c_cdns_bus *bus = dev_get_priv(dev);
 215         u32 div_a = 0, div_b = 0;
 216         unsigned long speed_p = speed;
 217         int ret = 0;
 218
 219         if (speed > I2C_SPEED_FAST_RATE) {
 220                 debug("%s, failed to set clock speed to %u\n", __func__,
 221                       speed);
 222                 return -EINVAL;
 223         }
 224
 225         ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
 226         if (ret)
 227                 return ret;
 228
 229         debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
 230               __func__, div_a, div_b, bus->input_freq, speed, speed_p);
 231
 232         writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
 233                (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 234
 235         /* Enable master mode, ack, and 7-bit addressing */
 236         setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
 237                 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
 238
 239         return 0;
 240 }
 241
 242 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
 243 {
 244         return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
 245 }
 246
 247 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 248                                u32 len)
 249 {
 250         u8 *cur_data = data;
 251         struct cdns_i2c_regs *regs = i2c_bus->regs;
 252         u32 ret;
 253
 254         /* Set the controller in Master transmit mode and clear FIFO */
 255         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
 256         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
 257
 258         /* Check message size against FIFO depth, and set hold bus bit
 259          * if it is greater than FIFO depth
 260          */
 261         if (len > CDNS_I2C_FIFO_DEPTH)
 262                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 263
 264         /* Clear the interrupts in status register */
 265         writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
 266
 267         writel(addr, &regs->address);
 268
 269         while (len-- && !is_arbitration_lost(regs)) {
 270                 writel(*(cur_data++), &regs->data);
 271                 if (len && readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
 272                         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 273                                             CDNS_I2C_INTERRUPT_ARBLOST);
 274                         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 275                                 return -EAGAIN;
 276                         if (ret & CDNS_I2C_INTERRUPT_COMP)
 277                                 continue;
 278                         /* Release the bus */
 279                         clrbits_le32(&regs->control,
 280                                      CDNS_I2C_CONTROL_HOLD);
 281                         return -ETIMEDOUT;
 282                 }
 283         }
 284
 285         if (len && is_arbitration_lost(regs))
 286                 return -EAGAIN;
 287
 288         /* All done... release the bus */
 289         if (!i2c_bus->hold_flag)
 290                 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 291
 292         /* Wait for the address and data to be sent */
 293         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 294                             CDNS_I2C_INTERRUPT_ARBLOST);
 295         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 296                      CDNS_I2C_INTERRUPT_COMP)))
 297                 return -ETIMEDOUT;
 298         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 299                 return -EAGAIN;
 300
 301         return 0;
 302 }
 303
 304 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
 305 {
 306         return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
 307 }
 308
 309 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 310                               u32 recv_count)
 311 {
 312         u8 *cur_data = data;
 313         struct cdns_i2c_regs *regs = i2c_bus->regs;
 314         u32 curr_recv_count;
 315         int updatetx, hold_quirk;
 316         u32 ret;
 317
 318         curr_recv_count = recv_count;
 319
 320         /* Check for the message size against the FIFO depth */
 321         if (recv_count > CDNS_I2C_FIFO_DEPTH)
 322                 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 323
 324         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 325                 CDNS_I2C_CONTROL_RW);
 326
 327         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 328                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 329                 writel(curr_recv_count, &regs->transfer_size);
 330         } else {
 331                 writel(recv_count, &regs->transfer_size);
 332         }
 333
 334         /* Start reading data */
 335         writel(addr, &regs->address);
 336
 337         updatetx = recv_count > curr_recv_count;
 338
 339         hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 340
 341         while (recv_count && !is_arbitration_lost(regs)) {
 342                 while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
 343                         if (recv_count < CDNS_I2C_FIFO_DEPTH &&
 344                             !i2c_bus->hold_flag) {
 345                                 clrbits_le32(&regs->control,
 346                                              CDNS_I2C_CONTROL_HOLD);
 347                         }
 348                         *(cur_data)++ = readl(&regs->data);
 349                         recv_count--;
 350                         curr_recv_count--;
 351
 352                         if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
 353                                 break;
 354                 }
 355
 356                 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
 357                         /* wait while fifo is full */
 358                         while (readl(&regs->transfer_size) !=
 359                                      (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 360                                 ;
 361                         /*
 362                          * Check number of bytes to be received against maximum
 363                          * transfer size and update register accordingly.
 364                          */
 365                         if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
 366                             CDNS_I2C_TRANSFER_SIZE) {
 367                                 writel(CDNS_I2C_TRANSFER_SIZE,
 368                                        &regs->transfer_size);
 369                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 370                                         CDNS_I2C_FIFO_DEPTH;
 371                         } else {
 372                                 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
 373                                        &regs->transfer_size);
 374                                 curr_recv_count = recv_count;
 375                         }
 376                 } else if (recv_count && !hold_quirk && !curr_recv_count) {
 377                         writel(addr, &regs->address);
 378                         if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
 379                                 writel(CDNS_I2C_TRANSFER_SIZE,
 380                                        &regs->transfer_size);
 381                                 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 382                         } else {
 383                                 writel(recv_count, &regs->transfer_size);
 384                                 curr_recv_count = recv_count;
 385                         }
 386                 }
 387         }
 388
 389         /* Wait for the address and data to be sent */
 390         ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 391                             CDNS_I2C_INTERRUPT_ARBLOST);
 392         if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
 393                      CDNS_I2C_INTERRUPT_COMP)))
 394                 return -ETIMEDOUT;
 395         if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
 396                 return -EAGAIN;
 397
 398         return 0;
 399 }
 400
 401 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 402                          int nmsgs)
 403 {
 404         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 405         int ret = 0;
 406         int count;
 407         bool hold_quirk;
 408         struct i2c_msg *message = msg;
 409         int num_msgs = nmsgs;
 410
 411         hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 412
 413         if (nmsgs > 1) {
 414                 /*
 415                  * This controller does not give completion interrupt after a
 416                  * master receive message if HOLD bit is set (repeated start),
 417                  * resulting in SW timeout. Hence, if a receive message is
 418                  * followed by any other message, an error is returned
 419                  * indicating that this sequence is not supported.
 420                  */
 421                 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
 422                         if (msg[count].flags & I2C_M_RD) {
 423                                 printf("Can't do repeated start after a receive message\n");
 424                                 return -EOPNOTSUPP;
 425                         }
 426                 }
 427
 428                 i2c_bus->hold_flag = 1;
 429                 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
 430         } else {
 431                 i2c_bus->hold_flag = 0;
 432         }
 433
 434         debug("i2c_xfer: %d messages\n", nmsgs);
 435         for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
 436              nmsgs > 0; nmsgs--, msg++) {
 437                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 438                 if (msg->flags & I2C_M_RD) {
 439                         ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
 440                                                  msg->len);
 441                 } else {
 442                         ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
 443                                                   msg->len);
 444                 }
 445                 if (ret == -EAGAIN) {
 446                         msg = message;
 447                         nmsgs = num_msgs;
 448                         retry++;
 449                         printf("%s,arbitration lost, retrying:%d\n", __func__,
 450                                retry);
 451                         continue;
 452                 }
 453
 454                 if (ret) {
 455                         debug("i2c_write: error sending\n");
 456                         return -EREMOTEIO;
 457                 }
 458         }
 459
 460         return ret;
 461 }
 462
 463 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 464 {
 465         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 466         struct cdns_i2c_platform_data *pdata =
 467                 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
 468         struct clk clk;
 469         int ret;
 470
 471         i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
 472         if (!i2c_bus->regs)
 473                 return -ENOMEM;
 474
 475         if (pdata)
 476                 i2c_bus->quirks = pdata->quirks;
 477
 478         ret = clk_get_by_index(dev, 0, &clk);
 479         if (ret)
 480                 return ret;
 481
 482         i2c_bus->input_freq = clk_get_rate(&clk);
 483
 484         return 0;
 485 }
 486
 487 static const struct dm_i2c_ops cdns_i2c_ops = {
 488         .xfer = cdns_i2c_xfer,
 489         .set_bus_speed = cdns_i2c_set_bus_speed,
 490 };
 491
 492 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
 493         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
 494 };
 495
 496 static const struct udevice_id cdns_i2c_of_match[] = {
 497         { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
 498         { .compatible = "cdns,i2c-r1p14" },
 499         { /* end of table */ }
 500 };
 501
 502 U_BOOT_DRIVER(cdns_i2c) = {
 503         .name = "i2c-cdns",
 504         .id = UCLASS_I2C,
 505         .of_match = cdns_i2c_of_match,
 506         .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 507         .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 508         .ops = &cdns_i2c_ops,
 509 };