drivers/i2c/exynos_hs_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016, Google Inc
   4  *
   5  * (C) Copyright 2002
   6  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <i2c.h>
  12 #include <log.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <linux/delay.h>
  17 #include "s3c24x0_i2c.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /* HSI2C-specific register description */
  22
  23 /* I2C_CTL Register bits */
  24 #define HSI2C_FUNC_MODE_I2C             (1u << 0)
  25 #define HSI2C_MASTER                    (1u << 3)
  26 #define HSI2C_RXCHON                    (1u << 6)       /* Write/Send */
  27 #define HSI2C_TXCHON                    (1u << 7)       /* Read/Receive */
  28 #define HSI2C_SW_RST                    (1u << 31)
  29
  30 /* I2C_FIFO_CTL Register bits */
  31 #define HSI2C_RXFIFO_EN                 (1u << 0)
  32 #define HSI2C_TXFIFO_EN                 (1u << 1)
  33 #define HSI2C_TXFIFO_TRIGGER_LEVEL      (0x20 << 16)
  34 #define HSI2C_RXFIFO_TRIGGER_LEVEL      (0x20 << 4)
  35
  36 /* I2C_TRAILING_CTL Register bits */
  37 #define HSI2C_TRAILING_COUNT            (0xff)
  38
  39 /* I2C_INT_EN Register bits */
  40 #define HSI2C_TX_UNDERRUN_EN            (1u << 2)
  41 #define HSI2C_TX_OVERRUN_EN             (1u << 3)
  42 #define HSI2C_RX_UNDERRUN_EN            (1u << 4)
  43 #define HSI2C_RX_OVERRUN_EN             (1u << 5)
  44 #define HSI2C_INT_TRAILING_EN           (1u << 6)
  45 #define HSI2C_INT_I2C_EN                (1u << 9)
  46
  47 #define HSI2C_INT_ERROR_MASK    (HSI2C_TX_UNDERRUN_EN |\
  48                                  HSI2C_TX_OVERRUN_EN  |\
  49                                  HSI2C_RX_UNDERRUN_EN |\
  50                                  HSI2C_RX_OVERRUN_EN  |\
  51                                  HSI2C_INT_TRAILING_EN)
  52
  53 /* I2C_CONF Register bits */
  54 #define HSI2C_AUTO_MODE                 (1u << 31)
  55 #define HSI2C_10BIT_ADDR_MODE           (1u << 30)
  56 #define HSI2C_HS_MODE                   (1u << 29)
  57
  58 /* I2C_AUTO_CONF Register bits */
  59 #define HSI2C_READ_WRITE                (1u << 16)
  60 #define HSI2C_STOP_AFTER_TRANS          (1u << 17)
  61 #define HSI2C_MASTER_RUN                (1u << 31)
  62
  63 /* I2C_TIMEOUT Register bits */
  64 #define HSI2C_TIMEOUT_EN                (1u << 31)
  65
  66 /* I2C_TRANS_STATUS register bits */
  67 #define HSI2C_MASTER_BUSY               (1u << 17)
  68 #define HSI2C_SLAVE_BUSY                (1u << 16)
  69 #define HSI2C_TIMEOUT_AUTO              (1u << 4)
  70 #define HSI2C_NO_DEV                    (1u << 3)
  71 #define HSI2C_NO_DEV_ACK                (1u << 2)
  72 #define HSI2C_TRANS_ABORT               (1u << 1)
  73 #define HSI2C_TRANS_SUCCESS             (1u << 0)
  74 #define HSI2C_TRANS_ERROR_MASK  (HSI2C_TIMEOUT_AUTO |\
  75                                  HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
  76                                  HSI2C_TRANS_ABORT)
  77 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
  78
  79
  80 /* I2C_FIFO_STAT Register bits */
  81 #define HSI2C_RX_FIFO_EMPTY             (1u << 24)
  82 #define HSI2C_RX_FIFO_FULL              (1u << 23)
  83 #define HSI2C_TX_FIFO_EMPTY             (1u << 8)
  84 #define HSI2C_TX_FIFO_FULL              (1u << 7)
  85 #define HSI2C_RX_FIFO_LEVEL(x)          (((x) >> 16) & 0x7f)
  86 #define HSI2C_TX_FIFO_LEVEL(x)          ((x) & 0x7f)
  87
  88 #define HSI2C_SLV_ADDR_MAS(x)           ((x & 0x3ff) << 10)
  89
  90 #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
  91
  92 /*
  93  * Wait for transfer completion.
  94  *
  95  * This function reads the interrupt status register waiting for the INT_I2C
  96  * bit to be set, which indicates copletion of a transaction.
  97  *
  98  * @param i2c: pointer to the appropriate register bank
  99  *
 100  * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
 101  *          the status bits do not get set in time, or an approrpiate error
 102  *          value in case of transfer errors.
 103  */
 104 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
 105 {
 106         int i = HSI2C_TIMEOUT_US;
 107
 108         while (i-- > 0) {
 109                 u32 int_status = readl(&i2c->usi_int_stat);
 110
 111                 if (int_status & HSI2C_INT_I2C_EN) {
 112                         u32 trans_status = readl(&i2c->usi_trans_status);
 113
 114                         /* Deassert pending interrupt. */
 115                         writel(int_status, &i2c->usi_int_stat);
 116
 117                         if (trans_status & HSI2C_NO_DEV_ACK) {
 118                                 debug("%s: no ACK from device\n", __func__);
 119                                 return I2C_NACK;
 120                         }
 121                         if (trans_status & HSI2C_NO_DEV) {
 122                                 debug("%s: no device\n", __func__);
 123                                 return I2C_NOK;
 124                         }
 125                         if (trans_status & HSI2C_TRANS_ABORT) {
 126                                 debug("%s: arbitration lost\n", __func__);
 127                                 return I2C_NOK_LA;
 128                         }
 129                         if (trans_status & HSI2C_TIMEOUT_AUTO) {
 130                                 debug("%s: device timed out\n", __func__);
 131                                 return I2C_NOK_TOUT;
 132                         }
 133                         return I2C_OK;
 134                 }
 135                 udelay(1);
 136         }
 137         debug("%s: transaction timeout!\n", __func__);
 138         return I2C_NOK_TOUT;
 139 }
 140
 141 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 142 {
 143         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 144         ulong clkin;
 145         unsigned int op_clk = i2c_bus->clock_frequency;
 146         unsigned int i = 0, utemp0 = 0, utemp1 = 0;
 147         unsigned int t_ftl_cycle;
 148
 149 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 150         clkin = get_i2c_clk();
 151 #else
 152         clkin = get_PCLK();
 153 #endif
 154         /* FPCLK / FI2C =
 155          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 156          * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
 157          * uTemp1 = (TSCLK_L + TSCLK_H + 2)
 158          * uTemp2 = TSCLK_L + TSCLK_H
 159          */
 160         t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
 161         utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
 162
 163         /* CLK_DIV max is 256 */
 164         for (i = 0; i < 256; i++) {
 165                 utemp1 = utemp0 / (i + 1);
 166                 if ((utemp1 < 512) && (utemp1 > 4)) {
 167                         i2c_bus->clk_cycle = utemp1 - 2;
 168                         i2c_bus->clk_div = i;
 169                         return 0;
 170                 }
 171         }
 172         return -EINVAL;
 173 }
 174
 175 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
 176 {
 177         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 178         unsigned int t_sr_release;
 179         unsigned int n_clkdiv;
 180         unsigned int t_start_su, t_start_hd;
 181         unsigned int t_stop_su;
 182         unsigned int t_data_su, t_data_hd;
 183         unsigned int t_scl_l, t_scl_h;
 184         u32 i2c_timing_s1;
 185         u32 i2c_timing_s2;
 186         u32 i2c_timing_s3;
 187         u32 i2c_timing_sla;
 188
 189         n_clkdiv = i2c_bus->clk_div;
 190         t_scl_l = i2c_bus->clk_cycle / 2;
 191         t_scl_h = i2c_bus->clk_cycle / 2;
 192         t_start_su = t_scl_l;
 193         t_start_hd = t_scl_l;
 194         t_stop_su = t_scl_l;
 195         t_data_su = t_scl_l / 2;
 196         t_data_hd = t_scl_l / 2;
 197         t_sr_release = i2c_bus->clk_cycle;
 198
 199         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 200         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 201         i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
 202         i2c_timing_sla = t_data_hd << 0;
 203
 204         writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
 205
 206         /* Clear to enable Timeout */
 207         clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
 208
 209         /* set AUTO mode */
 210         writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
 211
 212         /* Enable completion conditions' reporting. */
 213         writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
 214
 215         /* Enable FIFOs */
 216         writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
 217
 218         /* Currently operating in Fast speed mode. */
 219         writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
 220         writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
 221         writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
 222         writel(i2c_timing_sla, &hsregs->usi_timing_sla);
 223 }
 224
 225 /* SW reset for the high speed bus */
 226 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
 227 {
 228         struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
 229         u32 i2c_ctl;
 230
 231         /* Set and clear the bit for reset */
 232         i2c_ctl = readl(&i2c->usi_ctl);
 233         i2c_ctl |= HSI2C_SW_RST;
 234         writel(i2c_ctl, &i2c->usi_ctl);
 235
 236         i2c_ctl = readl(&i2c->usi_ctl);
 237         i2c_ctl &= ~HSI2C_SW_RST;
 238         writel(i2c_ctl, &i2c->usi_ctl);
 239
 240         /* Initialize the configure registers */
 241         hsi2c_ch_init(i2c_bus);
 242 }
 243
 244 /*
 245  * Poll the appropriate bit of the fifo status register until the interface is
 246  * ready to process the next byte or timeout expires.
 247  *
 248  * In addition to the FIFO status register this function also polls the
 249  * interrupt status register to be able to detect unexpected transaction
 250  * completion.
 251  *
 252  * When FIFO is ready to process the next byte, this function returns I2C_OK.
 253  * If in course of polling the INT_I2C assertion is detected, the function
 254  * returns I2C_NOK. If timeout happens before any of the above conditions is
 255  * met - the function returns I2C_NOK_TOUT;
 256
 257  * @param i2c: pointer to the appropriate i2c register bank.
 258  * @param rx_transfer: set to True if the receive transaction is in progress.
 259  * @return: as described above.
 260  */
 261 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
 262 {
 263         u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
 264         int i = HSI2C_TIMEOUT_US;
 265
 266         while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
 267                 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
 268                         /*
 269                          * There is a chance that assertion of
 270                          * HSI2C_INT_I2C_EN and deassertion of
 271                          * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
 272                          * give FIFO status priority and check it one more
 273                          * time before reporting interrupt. The interrupt will
 274                          * be reported next time this function is called.
 275                          */
 276                         if (rx_transfer &&
 277                             !(readl(&i2c->usi_fifo_stat) & fifo_bit))
 278                                 break;
 279                         return I2C_NOK;
 280                 }
 281                 if (!i--) {
 282                         debug("%s: FIFO polling timeout!\n", __func__);
 283                         return I2C_NOK_TOUT;
 284                 }
 285                 udelay(1);
 286         }
 287         return I2C_OK;
 288 }
 289
 290 /*
 291  * Preapre hsi2c transaction, either read or write.
 292  *
 293  * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
 294  * the 5420 UM.
 295  *
 296  * @param i2c: pointer to the appropriate i2c register bank.
 297  * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
 298  * @param len: number of bytes expected to be sent or received
 299  * @param rx_transfer: set to true for receive transactions
 300  * @param: issue_stop: set to true if i2c stop condition should be generated
 301  *         after this transaction.
 302  * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
 303  *          I2C_OK otherwise.
 304  */
 305 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
 306                                      u8 chip,
 307                                      u16 len,
 308                                      bool rx_transfer,
 309                                      bool issue_stop)
 310 {
 311         u32 conf;
 312
 313         conf = len | HSI2C_MASTER_RUN;
 314
 315         if (issue_stop)
 316                 conf |= HSI2C_STOP_AFTER_TRANS;
 317
 318         /* Clear to enable Timeout */
 319         writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
 320
 321         /* Set slave address */
 322         writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
 323
 324         if (rx_transfer) {
 325                 /* i2c master, read transaction */
 326                 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 327                        &i2c->usi_ctl);
 328
 329                 /* read up to len bytes, stop after transaction is finished */
 330                 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
 331         } else {
 332                 /* i2c master, write transaction */
 333                 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 334                        &i2c->usi_ctl);
 335
 336                 /* write up to len bytes, stop after transaction is finished */
 337                 writel(conf, &i2c->usi_auto_conf);
 338         }
 339
 340         /* Reset all pending interrupt status bits we care about, if any */
 341         writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
 342
 343         return I2C_OK;
 344 }
 345
 346 /*
 347  * Wait while i2c bus is settling down (mostly stop gets completed).
 348  */
 349 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
 350 {
 351         int i = HSI2C_TIMEOUT_US;
 352
 353         while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
 354                 if (!i--) {
 355                         debug("%s: bus busy\n", __func__);
 356                         return I2C_NOK_TOUT;
 357                 }
 358                 udelay(1);
 359         }
 360         return I2C_OK;
 361 }
 362
 363 static int hsi2c_write(struct exynos5_hsi2c *i2c,
 364                        unsigned char chip,
 365                        unsigned char addr[],
 366                        unsigned char alen,
 367                        unsigned char data[],
 368                        unsigned short len,
 369                        bool issue_stop)
 370 {
 371         int i, rv = 0;
 372
 373         if (!(len + alen)) {
 374                 /* Writes of zero length not supported in auto mode. */
 375                 debug("%s: zero length writes not supported\n", __func__);
 376                 return I2C_NOK;
 377         }
 378
 379         rv = hsi2c_prepare_transaction
 380                 (i2c, chip, len + alen, false, issue_stop);
 381         if (rv != I2C_OK)
 382                 return rv;
 383
 384         /* Move address, if any, and the data, if any, into the FIFO. */
 385         for (i = 0; i < alen; i++) {
 386                 rv = hsi2c_poll_fifo(i2c, false);
 387                 if (rv != I2C_OK) {
 388                         debug("%s: address write failed\n", __func__);
 389                         goto write_error;
 390                 }
 391                 writel(addr[i], &i2c->usi_txdata);
 392         }
 393
 394         for (i = 0; i < len; i++) {
 395                 rv = hsi2c_poll_fifo(i2c, false);
 396                 if (rv != I2C_OK) {
 397                         debug("%s: data write failed\n", __func__);
 398                         goto write_error;
 399                 }
 400                 writel(data[i], &i2c->usi_txdata);
 401         }
 402
 403         rv = hsi2c_wait_for_trx(i2c);
 404
 405  write_error:
 406         if (issue_stop) {
 407                 int tmp_ret = hsi2c_wait_while_busy(i2c);
 408                 if (rv == I2C_OK)
 409                         rv = tmp_ret;
 410         }
 411
 412         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 413         return rv;
 414 }
 415
 416 static int hsi2c_read(struct exynos5_hsi2c *i2c,
 417                       unsigned char chip,
 418                       unsigned char addr[],
 419                       unsigned char alen,
 420                       unsigned char data[],
 421                       unsigned short len)
 422 {
 423         int i, rv, tmp_ret;
 424         bool drop_data = false;
 425
 426         if (!len) {
 427                 /* Reads of zero length not supported in auto mode. */
 428                 debug("%s: zero length read adjusted\n", __func__);
 429                 drop_data = true;
 430                 len = 1;
 431         }
 432
 433         if (alen) {
 434                 /* Internal register adress needs to be written first. */
 435                 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
 436                 if (rv != I2C_OK)
 437                         return rv;
 438         }
 439
 440         rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
 441
 442         if (rv != I2C_OK)
 443                 return rv;
 444
 445         for (i = 0; i < len; i++) {
 446                 rv = hsi2c_poll_fifo(i2c, true);
 447                 if (rv != I2C_OK)
 448                         goto read_err;
 449                 if (drop_data)
 450                         continue;
 451                 data[i] = readl(&i2c->usi_rxdata);
 452         }
 453
 454         rv = hsi2c_wait_for_trx(i2c);
 455
 456  read_err:
 457         tmp_ret = hsi2c_wait_while_busy(i2c);
 458         if (rv == I2C_OK)
 459                 rv = tmp_ret;
 460
 461         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 462         return rv;
 463 }
 464
 465 static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 466                               int nmsgs)
 467 {
 468         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 469         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 470         int ret;
 471
 472         for (; nmsgs > 0; nmsgs--, msg++) {
 473                 if (msg->flags & I2C_M_RD) {
 474                         ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
 475                                          msg->len);
 476                 } else {
 477                         ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
 478                                           msg->len, true);
 479                 }
 480                 if (ret) {
 481                         exynos5_i2c_reset(i2c_bus);
 482                         return -EREMOTEIO;
 483                 }
 484         }
 485
 486         return 0;
 487 }
 488
 489 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 490 {
 491         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 492
 493         i2c_bus->clock_frequency = speed;
 494
 495         if (hsi2c_get_clk_details(i2c_bus))
 496                 return -EFAULT;
 497         hsi2c_ch_init(i2c_bus);
 498
 499         return 0;
 500 }
 501
 502 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
 503 {
 504         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 505         uchar buf[1];
 506         int ret;
 507
 508         buf[0] = 0;
 509
 510         /*
 511          * What is needed is to send the chip address and verify that the
 512          * address was <ACK>ed (i.e. there was a chip at that address which
 513          * drove the data line low).
 514          */
 515         ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1);
 516
 517         return ret != I2C_OK;
 518 }
 519
 520 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
 521 {
 522         const void *blob = gd->fdt_blob;
 523         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 524         int node;
 525
 526         node = dev_of_offset(dev);
 527
 528         i2c_bus->hsregs = (struct exynos5_hsi2c *)devfdt_get_addr(dev);
 529
 530         i2c_bus->id = pinmux_decode_periph_id(blob, node);
 531
 532         i2c_bus->clock_frequency =
 533                 dev_read_u32_default(dev, "clock-frequency",
 534                                      I2C_SPEED_STANDARD_RATE);
 535         i2c_bus->node = node;
 536         i2c_bus->bus_num = dev->seq;
 537
 538         exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE);
 539
 540         i2c_bus->active = true;
 541
 542         return 0;
 543 }
 544
 545 static const struct dm_i2c_ops exynos_hs_i2c_ops = {
 546         .xfer           = exynos_hs_i2c_xfer,
 547         .probe_chip     = s3c24x0_i2c_probe,
 548         .set_bus_speed  = s3c24x0_i2c_set_bus_speed,
 549 };
 550
 551 static const struct udevice_id exynos_hs_i2c_ids[] = {
 552         { .compatible = "samsung,exynos5-hsi2c" },
 553         { }
 554 };
 555
 556 U_BOOT_DRIVER(hs_i2c) = {
 557         .name   = "i2c_s3c_hs",
 558         .id     = UCLASS_I2C,
 559         .of_match = exynos_hs_i2c_ids,
 560         .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
 561         .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
 562         .ops    = &exynos_hs_i2c_ops,
 563 };