drivers/i2c/designware_i2c_pci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  * Copyright 2019 Google Inc
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <spl.h>
  12 #include <asm/lpss.h>
  13 #include "designware_i2c.h"
  14
  15 enum {
  16         VANILLA         = 0,    /* standard I2C with no tweaks */
  17         INTEL_APL,              /* Apollo Lake I2C */
  18 };
  19
  20 /* BayTrail HCNT/LCNT/SDA hold time */
  21 static struct dw_scl_sda_cfg byt_config = {
  22         .ss_hcnt = 0x200,
  23         .fs_hcnt = 0x55,
  24         .ss_lcnt = 0x200,
  25         .fs_lcnt = 0x99,
  26         .sda_hold = 0x6,
  27 };
  28
  29 /* Have a weak function for now - possibly should be a new uclass */
  30 __weak void lpss_reset_release(void *regs);
  31
  32 static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
  33 {
  34         struct dw_i2c *priv = dev_get_priv(dev);
  35
  36         if (spl_phase() < PHASE_SPL) {
  37                 u32 base;
  38                 int ret;
  39
  40                 ret = dev_read_u32(dev, "early-regs", &base);
  41                 if (ret)
  42                         return log_msg_ret("early-regs", ret);
  43
  44                 /* Set i2c base address */
  45                 dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
  46
  47                 /* Enable memory access and bus master */
  48                 dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
  49                                       PCI_COMMAND_MASTER);
  50         }
  51
  52         if (spl_phase() < PHASE_BOARD_F) {
  53                 /* Handle early, fixed mapping into a different address space */
  54                 priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
  55         } else {
  56                 priv->regs = (struct i2c_regs *)
  57                         dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  58         }
  59         if (!priv->regs)
  60                 return -EINVAL;
  61
  62         /* Save base address from PCI BAR */
  63         if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
  64                 /* Use BayTrail specific timing values */
  65                 priv->scl_sda_cfg = &byt_config;
  66         if (dev_get_driver_data(dev) == INTEL_APL)
  67                 priv->has_spk_cnt = true;
  68
  69         return designware_i2c_ofdata_to_platdata(dev);
  70 }
  71
  72 static int designware_i2c_pci_probe(struct udevice *dev)
  73 {
  74         struct dw_i2c *priv = dev_get_priv(dev);
  75
  76         if (dev_get_driver_data(dev) == INTEL_APL) {
  77                 /* Ensure controller is in D0 state */
  78                 lpss_set_power_state(dev, STATE_D0);
  79
  80                 lpss_reset_release(priv->regs);
  81         }
  82
  83         return designware_i2c_probe(dev);
  84 }
  85
  86 static int designware_i2c_pci_bind(struct udevice *dev)
  87 {
  88         char name[20];
  89
  90         /*
  91          * Create a unique device name for PCI type devices
  92          * ToDo:
  93          * Setting req_seq in the driver is probably not recommended.
  94          * But without a DT alias the number is not configured. And
  95          * using this driver is impossible for PCIe I2C devices.
  96          * This can be removed, once a better (correct) way for this
  97          * is found and implemented.
  98          *
  99          * TODO(sjg@chromium.org): Perhaps if uclasses had platdata this would
 100          * be possible. We cannot use static data in drivers since they may be
 101          * used in SPL or before relocation.
 102          */
 103         dev->req_seq = gd->arch.dw_i2c_num_cards++;
 104         sprintf(name, "i2c_designware#%u", dev->req_seq);
 105         device_set_name(dev, name);
 106
 107         return 0;
 108 }
 109
 110 static const struct udevice_id designware_i2c_pci_ids[] = {
 111         { .compatible = "snps,designware-i2c-pci" },
 112         { .compatible = "intel,apl-i2c", .data = INTEL_APL },
 113         { }
 114 };
 115
 116 U_BOOT_DRIVER(i2c_designware_pci) = {
 117         .name   = "i2c_designware_pci",
 118         .id     = UCLASS_I2C,
 119         .of_match = designware_i2c_pci_ids,
 120         .bind   = designware_i2c_pci_bind,
 121         .ofdata_to_platdata     = designware_i2c_pci_ofdata_to_platdata,
 122         .probe  = designware_i2c_pci_probe,
 123         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 124         .remove = designware_i2c_remove,
 125         .flags = DM_FLAG_OS_PREPARE,
 126         .ops    = &designware_i2c_ops,
 127 };
 128
 129 static struct pci_device_id designware_pci_supported[] = {
 130         /* Intel BayTrail has 7 I2C controller located on the PCI bus */
 131         { PCI_VDEVICE(INTEL, 0x0f41) },
 132         { PCI_VDEVICE(INTEL, 0x0f42) },
 133         { PCI_VDEVICE(INTEL, 0x0f43) },
 134         { PCI_VDEVICE(INTEL, 0x0f44) },
 135         { PCI_VDEVICE(INTEL, 0x0f45) },
 136         { PCI_VDEVICE(INTEL, 0x0f46) },
 137         { PCI_VDEVICE(INTEL, 0x0f47) },
 138         { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
 139         { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
 140         { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
 141         { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
 142         { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
 143         { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
 144         {},
 145 };
 146
 147 U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);