drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <pci.h>
  14 #include <reset.h>
  15 #include <asm/io.h>
  16 #include <linux/delay.h>
  17 #include "designware_i2c.h"
  18 #include <dm/device_compat.h>
  19 #include <linux/err.h>
  20
  21 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  22 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  23 {
  24         u32 ena = enable ? IC_ENABLE_0B : 0;
  25
  26         writel(ena, &i2c_base->ic_enable);
  27
  28         return 0;
  29 }
  30 #else
  31 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  32 {
  33         u32 ena = enable ? IC_ENABLE_0B : 0;
  34         int timeout = 100;
  35
  36         do {
  37                 writel(ena, &i2c_base->ic_enable);
  38                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  39                         return 0;
  40
  41                 /*
  42                  * Wait 10 times the signaling period of the highest I2C
  43                  * transfer supported by the driver (for 400KHz this is
  44                  * 25us) as described in the DesignWare I2C databook.
  45                  */
  46                 udelay(25);
  47         } while (timeout--);
  48         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  49
  50         return -ETIMEDOUT;
  51 }
  52 #endif
  53
  54 /* High and low times in different speed modes (in ns) */
  55 enum {
  56         /* SDA Hold Time */
  57         DEFAULT_SDA_HOLD_TIME           = 300,
  58 };
  59
  60 /**
  61  * calc_counts() - Convert a period to a number of IC clk cycles
  62  *
  63  * @ic_clk: Input clock in Hz
  64  * @period_ns: Period to represent, in ns
  65  * @return calculated count
  66  */
  67 static uint calc_counts(uint ic_clk, uint period_ns)
  68 {
  69         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  70 }
  71
  72 /**
  73  * struct i2c_mode_info - Information about an I2C speed mode
  74  *
  75  * Each speed mode has its own characteristics. This struct holds these to aid
  76  * calculations in dw_i2c_calc_timing().
  77  *
  78  * @speed: Speed in Hz
  79  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  80  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  81  * @def_rise_time_ns: Default rise time in ns
  82  * @def_fall_time_ns: Default fall time in ns
  83  */
  84 struct i2c_mode_info {
  85         int speed;
  86         int min_scl_hightime_ns;
  87         int min_scl_lowtime_ns;
  88         int def_rise_time_ns;
  89         int def_fall_time_ns;
  90 };
  91
  92 static const struct i2c_mode_info info_for_mode[] = {
  93         [IC_SPEED_MODE_STANDARD] = {
  94                 I2C_SPEED_STANDARD_RATE,
  95                 MIN_SS_SCL_HIGHTIME,
  96                 MIN_SS_SCL_LOWTIME,
  97                 1000,
  98                 300,
  99         },
 100         [IC_SPEED_MODE_FAST] = {
 101                 I2C_SPEED_FAST_RATE,
 102                 MIN_FS_SCL_HIGHTIME,
 103                 MIN_FS_SCL_LOWTIME,
 104                 300,
 105                 300,
 106         },
 107         [IC_SPEED_MODE_FAST_PLUS] = {
 108                 I2C_SPEED_FAST_PLUS_RATE,
 109                 MIN_FP_SCL_HIGHTIME,
 110                 MIN_FP_SCL_LOWTIME,
 111                 260,
 112                 500,
 113         },
 114         [IC_SPEED_MODE_HIGH] = {
 115                 I2C_SPEED_HIGH_RATE,
 116                 MIN_HS_SCL_HIGHTIME,
 117                 MIN_HS_SCL_LOWTIME,
 118                 120,
 119                 120,
 120         },
 121 };
 122
 123 /**
 124  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 125  *
 126  * @priv: Bus private information (NULL if not using driver model)
 127  * @mode: Speed mode to use
 128  * @ic_clk: IC clock speed in Hz
 129  * @spk_cnt: Spike-suppression count
 130  * @config: Returns value to use
 131  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 132  */
 133 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 134                               int ic_clk, int spk_cnt,
 135                               struct dw_i2c_speed_config *config)
 136 {
 137         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 138         int hcnt, lcnt, period_cnt, diff, tot;
 139         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 140         const struct i2c_mode_info *info;
 141
 142         /*
 143          * Find the period, rise, fall, min tlow, and min thigh in terms of
 144          * counts of the IC clock
 145          */
 146         info = &info_for_mode[mode];
 147         period_cnt = ic_clk / info->speed;
 148         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 149                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 150         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 151                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 152         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 153         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 154         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 155         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 156
 157         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 158               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 159               spk_cnt);
 160
 161         /*
 162          * Back-solve for hcnt and lcnt according to the following equations:
 163          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 164          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 165          */
 166         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 167         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 168
 169         if (hcnt < 0 || lcnt < 0) {
 170                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 171                 return -EINVAL;
 172         }
 173
 174         /*
 175          * Now add things back up to ensure the period is hit. If it is off,
 176          * split the difference and bias to lcnt for remainder
 177          */
 178         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 179
 180         if (tot < period_cnt) {
 181                 diff = (period_cnt - tot) / 2;
 182                 hcnt += diff;
 183                 lcnt += diff;
 184                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 185                 lcnt += period_cnt - tot;
 186         }
 187
 188         config->scl_lcnt = lcnt;
 189         config->scl_hcnt = hcnt;
 190
 191         /* Use internal default unless other value is specified */
 192         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 193                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 194         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 195
 196         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 197               config->sda_hold);
 198
 199         return 0;
 200 }
 201
 202 /**
 203  * calc_bus_speed() - Calculate the config to use for a particular i2c speed
 204  *
 205  * @priv: Private information for the driver (NULL if not using driver model)
 206  * @i2c_base: Registers for the I2C controller
 207  * @speed: Required i2c speed in Hz
 208  * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
 209  * @config: Returns the config to use for this speed
 210  * @return 0 if OK, -ve on error
 211  */
 212 static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
 213                           ulong bus_clk, struct dw_i2c_speed_config *config)
 214 {
 215         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 216         enum i2c_speed_mode i2c_spd;
 217         int spk_cnt;
 218         int ret;
 219
 220         if (priv)
 221                 scl_sda_cfg = priv->scl_sda_cfg;
 222         /* Allow high speed if there is no config, or the config allows it */
 223         if (speed >= I2C_SPEED_HIGH_RATE)
 224                 i2c_spd = IC_SPEED_MODE_HIGH;
 225         else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
 226                 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
 227         else if (speed >= I2C_SPEED_FAST_RATE)
 228                 i2c_spd = IC_SPEED_MODE_FAST;
 229         else
 230                 i2c_spd = IC_SPEED_MODE_STANDARD;
 231
 232         /* Check is high speed possible and fall back to fast mode if not */
 233         if (i2c_spd == IC_SPEED_MODE_HIGH) {
 234                 u32 comp_param1;
 235
 236                 comp_param1 = readl(&regs->comp_param1);
 237                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 238                                 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
 239                         i2c_spd = IC_SPEED_MODE_FAST;
 240         }
 241
 242         /* Get the proper spike-suppression count based on target speed */
 243         if (!priv || !priv->has_spk_cnt)
 244                 spk_cnt = 0;
 245         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 246                 spk_cnt = readl(&regs->hs_spklen);
 247         else
 248                 spk_cnt = readl(&regs->fs_spklen);
 249         if (scl_sda_cfg) {
 250                 config->sda_hold = scl_sda_cfg->sda_hold;
 251                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 252                         config->scl_hcnt = scl_sda_cfg->ss_hcnt;
 253                         config->scl_lcnt = scl_sda_cfg->ss_lcnt;
 254                 } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
 255                         config->scl_hcnt = scl_sda_cfg->hs_hcnt;
 256                         config->scl_lcnt = scl_sda_cfg->hs_lcnt;
 257                 } else {
 258                         config->scl_hcnt = scl_sda_cfg->fs_hcnt;
 259                         config->scl_lcnt = scl_sda_cfg->fs_lcnt;
 260                 }
 261         } else {
 262                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 263                                          config);
 264                 if (ret)
 265                         return log_msg_ret("gen_confg", ret);
 266         }
 267         config->speed_mode = i2c_spd;
 268
 269         return 0;
 270 }
 271
 272 /**
 273  * _dw_i2c_set_bus_speed() - Set the i2c speed
 274  *
 275  * @priv: Private information for the driver (NULL if not using driver model)
 276  * @i2c_base: Registers for the I2C controller
 277  * @speed: Required i2c speed in Hz
 278  * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
 279  * @return 0 if OK, -ve on error
 280  */
 281 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 282                                  unsigned int speed, unsigned int bus_clk)
 283 {
 284         struct dw_i2c_speed_config config;
 285         unsigned int cntl;
 286         unsigned int ena;
 287         int ret;
 288
 289         ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config);
 290         if (ret)
 291                 return ret;
 292
 293         /* Get enable setting for restore later */
 294         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 295
 296         /* to set speed cltr must be disabled */
 297         dw_i2c_enable(i2c_base, false);
 298
 299         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 300
 301         switch (config.speed_mode) {
 302         case IC_SPEED_MODE_HIGH:
 303                 cntl |= IC_CON_SPD_HS;
 304                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 305                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 306                 break;
 307         case IC_SPEED_MODE_STANDARD:
 308                 cntl |= IC_CON_SPD_SS;
 309                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 310                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 311                 break;
 312         case IC_SPEED_MODE_FAST_PLUS:
 313         case IC_SPEED_MODE_FAST:
 314         default:
 315                 cntl |= IC_CON_SPD_FS;
 316                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 317                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 318                 break;
 319         }
 320
 321         writel(cntl, &i2c_base->ic_con);
 322
 323         /* Configure SDA Hold Time if required */
 324         if (config.sda_hold)
 325                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 326
 327         /* Restore back i2c now speed set */
 328         if (ena == IC_ENABLE_0B)
 329                 dw_i2c_enable(i2c_base, true);
 330
 331         return 0;
 332 }
 333
 334 /*
 335  * i2c_setaddress - Sets the target slave address
 336  * @i2c_addr:   target i2c address
 337  *
 338  * Sets the target slave address.
 339  */
 340 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 341 {
 342         /* Disable i2c */
 343         dw_i2c_enable(i2c_base, false);
 344
 345         writel(i2c_addr, &i2c_base->ic_tar);
 346
 347         /* Enable i2c */
 348         dw_i2c_enable(i2c_base, true);
 349 }
 350
 351 /*
 352  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 353  *
 354  * Flushes the i2c RX FIFO
 355  */
 356 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 357 {
 358         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 359                 readl(&i2c_base->ic_cmd_data);
 360 }
 361
 362 /*
 363  * i2c_wait_for_bb - Waits for bus busy
 364  *
 365  * Waits for bus busy
 366  */
 367 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 368 {
 369         unsigned long start_time_bb = get_timer(0);
 370
 371         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 372                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 373
 374                 /* Evaluate timeout */
 375                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 376                         return 1;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 383                          int alen)
 384 {
 385         if (i2c_wait_for_bb(i2c_base))
 386                 return 1;
 387
 388         i2c_setaddress(i2c_base, chip);
 389         while (alen) {
 390                 alen--;
 391                 /* high byte address going out first */
 392                 writel((addr >> (alen * 8)) & 0xff,
 393                        &i2c_base->ic_cmd_data);
 394         }
 395         return 0;
 396 }
 397
 398 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 399 {
 400         ulong start_stop_det = get_timer(0);
 401
 402         while (1) {
 403                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 404                         readl(&i2c_base->ic_clr_stop_det);
 405                         break;
 406                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 407                         break;
 408                 }
 409         }
 410
 411         if (i2c_wait_for_bb(i2c_base)) {
 412                 printf("Timed out waiting for bus\n");
 413                 return 1;
 414         }
 415
 416         i2c_flush_rxfifo(i2c_base);
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * i2c_read - Read from i2c memory
 423  * @chip:       target i2c address
 424  * @addr:       address to read from
 425  * @alen:
 426  * @buffer:     buffer for read data
 427  * @len:        no of bytes to be read
 428  *
 429  * Read from i2c memory.
 430  */
 431 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 432                          int alen, u8 *buffer, int len)
 433 {
 434         unsigned long start_time_rx;
 435         unsigned int active = 0;
 436
 437 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 438         /*
 439          * EEPROM chips that implement "address overflow" are ones
 440          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 441          * address and the extra bits end up in the "chip address"
 442          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 443          * four 256 byte chips.
 444          *
 445          * Note that we consider the length of the address field to
 446          * still be one byte because the extra address bits are
 447          * hidden in the chip address.
 448          */
 449         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 450         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 451
 452         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 453               addr);
 454 #endif
 455
 456         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 457                 return 1;
 458
 459         start_time_rx = get_timer(0);
 460         while (len) {
 461                 if (!active) {
 462                         /*
 463                          * Avoid writing to ic_cmd_data multiple times
 464                          * in case this loop spins too quickly and the
 465                          * ic_status RFNE bit isn't set after the first
 466                          * write. Subsequent writes to ic_cmd_data can
 467                          * trigger spurious i2c transfer.
 468                          */
 469                         if (len == 1)
 470                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 471                         else
 472                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 473                         active = 1;
 474                 }
 475
 476                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 477                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 478                         len--;
 479                         start_time_rx = get_timer(0);
 480                         active = 0;
 481                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 482                         return 1;
 483                 }
 484         }
 485
 486         return i2c_xfer_finish(i2c_base);
 487 }
 488
 489 /*
 490  * i2c_write - Write to i2c memory
 491  * @chip:       target i2c address
 492  * @addr:       address to read from
 493  * @alen:
 494  * @buffer:     buffer for read data
 495  * @len:        no of bytes to be read
 496  *
 497  * Write to i2c memory.
 498  */
 499 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 500                           int alen, u8 *buffer, int len)
 501 {
 502         int nb = len;
 503         unsigned long start_time_tx;
 504
 505 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 506         /*
 507          * EEPROM chips that implement "address overflow" are ones
 508          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 509          * address and the extra bits end up in the "chip address"
 510          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 511          * four 256 byte chips.
 512          *
 513          * Note that we consider the length of the address field to
 514          * still be one byte because the extra address bits are
 515          * hidden in the chip address.
 516          */
 517         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 518         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 519
 520         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 521               addr);
 522 #endif
 523
 524         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 525                 return 1;
 526
 527         start_time_tx = get_timer(0);
 528         while (len) {
 529                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 530                         if (--len == 0) {
 531                                 writel(*buffer | IC_STOP,
 532                                        &i2c_base->ic_cmd_data);
 533                         } else {
 534                                 writel(*buffer, &i2c_base->ic_cmd_data);
 535                         }
 536                         buffer++;
 537                         start_time_tx = get_timer(0);
 538
 539                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 540                                 printf("Timed out. i2c write Failed\n");
 541                                 return 1;
 542                 }
 543         }
 544
 545         return i2c_xfer_finish(i2c_base);
 546 }
 547
 548 /*
 549  * __dw_i2c_init - Init function
 550  * @speed:      required i2c speed
 551  * @slaveaddr:  slave address for the device
 552  *
 553  * Initialization function.
 554  */
 555 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 556 {
 557         int ret;
 558
 559         /* Disable i2c */
 560         ret = dw_i2c_enable(i2c_base, false);
 561         if (ret)
 562                 return ret;
 563
 564         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 565                &i2c_base->ic_con);
 566         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 567         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 568         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 569 #ifndef CONFIG_DM_I2C
 570         _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 571         writel(slaveaddr, &i2c_base->ic_sar);
 572 #endif
 573
 574         /* Enable i2c */
 575         ret = dw_i2c_enable(i2c_base, true);
 576         if (ret)
 577                 return ret;
 578
 579         return 0;
 580 }
 581
 582 #ifndef CONFIG_DM_I2C
 583 /*
 584  * The legacy I2C functions. These need to get removed once
 585  * all users of this driver are converted to DM.
 586  */
 587 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 588 {
 589         switch (adap->hwadapnr) {
 590 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 591         case 3:
 592                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 593 #endif
 594 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 595         case 2:
 596                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 597 #endif
 598 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 599         case 1:
 600                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 601 #endif
 602         case 0:
 603                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 604         default:
 605                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 606         }
 607
 608         return NULL;
 609 }
 610
 611 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 612                                          unsigned int speed)
 613 {
 614         adap->speed = speed;
 615         return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 616 }
 617
 618 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 619 {
 620         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 621 }
 622
 623 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 624                        int alen, u8 *buffer, int len)
 625 {
 626         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 627 }
 628
 629 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 630                         int alen, u8 *buffer, int len)
 631 {
 632         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 633 }
 634
 635 /* dw_i2c_probe - Probe the i2c chip */
 636 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 637 {
 638         struct i2c_regs *i2c_base = i2c_get_base(adap);
 639         u32 tmp;
 640         int ret;
 641
 642         /*
 643          * Try to read the first location of the chip.
 644          */
 645         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 646         if (ret)
 647                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 648
 649         return ret;
 650 }
 651
 652 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 653                          dw_i2c_write, dw_i2c_set_bus_speed,
 654                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 655
 656 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 657 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 658                          dw_i2c_write, dw_i2c_set_bus_speed,
 659                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 660 #endif
 661
 662 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 663 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 664                          dw_i2c_write, dw_i2c_set_bus_speed,
 665                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 666 #endif
 667
 668 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 669 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 670                          dw_i2c_write, dw_i2c_set_bus_speed,
 671                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 672 #endif
 673
 674 #else /* CONFIG_DM_I2C */
 675 /* The DM I2C functions */
 676
 677 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 678                                int nmsgs)
 679 {
 680         struct dw_i2c *i2c = dev_get_priv(bus);
 681         int ret;
 682
 683         debug("i2c_xfer: %d messages\n", nmsgs);
 684         for (; nmsgs > 0; nmsgs--, msg++) {
 685                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 686                 if (msg->flags & I2C_M_RD) {
 687                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 688                                             msg->buf, msg->len);
 689                 } else {
 690                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 691                                              msg->buf, msg->len);
 692                 }
 693                 if (ret) {
 694                         debug("i2c_write: error sending\n");
 695                         return -EREMOTEIO;
 696                 }
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 703 {
 704         struct dw_i2c *i2c = dev_get_priv(bus);
 705         ulong rate;
 706
 707 #if CONFIG_IS_ENABLED(CLK)
 708         rate = clk_get_rate(&i2c->clk);
 709         if (IS_ERR_VALUE(rate))
 710                 return -EINVAL;
 711 #else
 712         rate = IC_CLK;
 713 #endif
 714         return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 715 }
 716
 717 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 718                                      uint chip_flags)
 719 {
 720         struct dw_i2c *i2c = dev_get_priv(bus);
 721         struct i2c_regs *i2c_base = i2c->regs;
 722         u32 tmp;
 723         int ret;
 724
 725         /* Try to read the first location of the chip */
 726         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 727         if (ret)
 728                 __dw_i2c_init(i2c_base, 0, 0);
 729
 730         return ret;
 731 }
 732
 733 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 734 {
 735         struct dw_i2c *priv = dev_get_priv(bus);
 736         int ret;
 737
 738         if (!priv->regs)
 739                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 740         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 741         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 742         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 743
 744         ret = reset_get_bulk(bus, &priv->resets);
 745         if (ret)
 746                 dev_warn(bus, "Can't get reset: %d\n", ret);
 747         else
 748                 reset_deassert_bulk(&priv->resets);
 749
 750 #if CONFIG_IS_ENABLED(CLK)
 751         ret = clk_get_by_index(bus, 0, &priv->clk);
 752         if (ret)
 753                 return ret;
 754
 755         ret = clk_enable(&priv->clk);
 756         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 757                 clk_free(&priv->clk);
 758                 dev_err(bus, "failed to enable clock\n");
 759                 return ret;
 760         }
 761 #endif
 762
 763         return 0;
 764 }
 765
 766 int designware_i2c_probe(struct udevice *bus)
 767 {
 768         struct dw_i2c *priv = dev_get_priv(bus);
 769
 770         return __dw_i2c_init(priv->regs, 0, 0);
 771 }
 772
 773 int designware_i2c_remove(struct udevice *dev)
 774 {
 775         struct dw_i2c *priv = dev_get_priv(dev);
 776
 777 #if CONFIG_IS_ENABLED(CLK)
 778         clk_disable(&priv->clk);
 779         clk_free(&priv->clk);
 780 #endif
 781
 782         return reset_release_bulk(&priv->resets);
 783 }
 784
 785 const struct dm_i2c_ops designware_i2c_ops = {
 786         .xfer           = designware_i2c_xfer,
 787         .probe_chip     = designware_i2c_probe_chip,
 788         .set_bus_speed  = designware_i2c_set_bus_speed,
 789 };
 790
 791 static const struct udevice_id designware_i2c_ids[] = {
 792         { .compatible = "snps,designware-i2c" },
 793         { }
 794 };
 795
 796 U_BOOT_DRIVER(i2c_designware) = {
 797         .name   = "i2c_designware",
 798         .id     = UCLASS_I2C,
 799         .of_match = designware_i2c_ids,
 800         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 801         .probe  = designware_i2c_probe,
 802         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 803         .remove = designware_i2c_remove,
 804         .flags  = DM_FLAG_OS_PREPARE,
 805         .ops    = &designware_i2c_ops,
 806 };
 807
 808 #endif /* CONFIG_DM_I2C */