drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <reset.h>
  13 #include <asm/io.h>
  14 #include "designware_i2c.h"
  15 #include <linux/err.h>
  16
  17 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  18 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  19 {
  20         u32 ena = enable ? IC_ENABLE_0B : 0;
  21
  22         writel(ena, &i2c_base->ic_enable);
  23
  24         return 0;
  25 }
  26 #else
  27 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  28 {
  29         u32 ena = enable ? IC_ENABLE_0B : 0;
  30         int timeout = 100;
  31
  32         do {
  33                 writel(ena, &i2c_base->ic_enable);
  34                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  35                         return 0;
  36
  37                 /*
  38                  * Wait 10 times the signaling period of the highest I2C
  39                  * transfer supported by the driver (for 400KHz this is
  40                  * 25us) as described in the DesignWare I2C databook.
  41                  */
  42                 udelay(25);
  43         } while (timeout--);
  44         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  45
  46         return -ETIMEDOUT;
  47 }
  48 #endif
  49
  50 /* High and low times in different speed modes (in ns) */
  51 enum {
  52         /* SDA Hold Time */
  53         DEFAULT_SDA_HOLD_TIME           = 300,
  54 };
  55
  56 /**
  57  * calc_counts() - Convert a period to a number of IC clk cycles
  58  *
  59  * @ic_clk: Input clock in Hz
  60  * @period_ns: Period to represent, in ns
  61  * @return calculated count
  62  */
  63 static uint calc_counts(uint ic_clk, uint period_ns)
  64 {
  65         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  66 }
  67
  68 /**
  69  * struct i2c_mode_info - Information about an I2C speed mode
  70  *
  71  * Each speed mode has its own characteristics. This struct holds these to aid
  72  * calculations in dw_i2c_calc_timing().
  73  *
  74  * @speed: Speed in Hz
  75  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  76  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  77  * @def_rise_time_ns: Default rise time in ns
  78  * @def_fall_time_ns: Default fall time in ns
  79  */
  80 struct i2c_mode_info {
  81         int speed;
  82         int min_scl_hightime_ns;
  83         int min_scl_lowtime_ns;
  84         int def_rise_time_ns;
  85         int def_fall_time_ns;
  86 };
  87
  88 static const struct i2c_mode_info info_for_mode[] = {
  89         [IC_SPEED_MODE_STANDARD] = {
  90                 I2C_SPEED_STANDARD_RATE,
  91                 MIN_SS_SCL_HIGHTIME,
  92                 MIN_SS_SCL_LOWTIME,
  93                 1000,
  94                 300,
  95         },
  96         [IC_SPEED_MODE_FAST] = {
  97                 I2C_SPEED_FAST_RATE,
  98                 MIN_FS_SCL_HIGHTIME,
  99                 MIN_FS_SCL_LOWTIME,
 100                 300,
 101                 300,
 102         },
 103         [IC_SPEED_MODE_FAST_PLUS] = {
 104                 I2C_SPEED_FAST_PLUS_RATE,
 105                 MIN_FP_SCL_HIGHTIME,
 106                 MIN_FP_SCL_LOWTIME,
 107                 260,
 108                 500,
 109         },
 110         [IC_SPEED_MODE_HIGH] = {
 111                 I2C_SPEED_HIGH_RATE,
 112                 MIN_HS_SCL_HIGHTIME,
 113                 MIN_HS_SCL_LOWTIME,
 114                 120,
 115                 120,
 116         },
 117 };
 118
 119 /**
 120  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 121  *
 122  * @priv: Bus private information (NULL if not using driver model)
 123  * @mode: Speed mode to use
 124  * @ic_clk: IC clock speed in Hz
 125  * @spk_cnt: Spike-suppression count
 126  * @config: Returns value to use
 127  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 128  */
 129 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 130                               int ic_clk, int spk_cnt,
 131                               struct dw_i2c_speed_config *config)
 132 {
 133         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 134         int hcnt, lcnt, period_cnt, diff, tot;
 135         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 136         const struct i2c_mode_info *info;
 137
 138         /*
 139          * Find the period, rise, fall, min tlow, and min thigh in terms of
 140          * counts of the IC clock
 141          */
 142         info = &info_for_mode[mode];
 143         period_cnt = ic_clk / info->speed;
 144         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 145                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 146         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 147                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 148         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 149         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 150         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 151         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 152
 153         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 154               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 155               spk_cnt);
 156
 157         /*
 158          * Back-solve for hcnt and lcnt according to the following equations:
 159          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 160          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 161          */
 162         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 163         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 164
 165         if (hcnt < 0 || lcnt < 0) {
 166                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 167                 return -EINVAL;
 168         }
 169
 170         /*
 171          * Now add things back up to ensure the period is hit. If it is off,
 172          * split the difference and bias to lcnt for remainder
 173          */
 174         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 175
 176         if (tot < period_cnt) {
 177                 diff = (period_cnt - tot) / 2;
 178                 hcnt += diff;
 179                 lcnt += diff;
 180                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 181                 lcnt += period_cnt - tot;
 182         }
 183
 184         config->scl_lcnt = lcnt;
 185         config->scl_hcnt = hcnt;
 186
 187         /* Use internal default unless other value is specified */
 188         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 189                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 190         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 191
 192         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 193               config->sda_hold);
 194
 195         return 0;
 196 }
 197
 198 static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
 199                           struct dw_i2c_speed_config *config)
 200 {
 201         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 202         struct i2c_regs *regs = priv->regs;
 203         enum i2c_speed_mode i2c_spd;
 204         int spk_cnt;
 205         int ret;
 206
 207         if (priv)
 208                 scl_sda_cfg = priv->scl_sda_cfg;
 209         /* Allow high speed if there is no config, or the config allows it */
 210         if (speed >= I2C_SPEED_HIGH_RATE &&
 211             (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
 212                 i2c_spd = IC_SPEED_MODE_HIGH;
 213         else if (speed >= I2C_SPEED_FAST_RATE)
 214                 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
 215         else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
 216                 i2c_spd = IC_SPEED_MODE_FAST;
 217         else
 218                 i2c_spd = IC_SPEED_MODE_STANDARD;
 219
 220         /* Get the proper spike-suppression count based on target speed */
 221         if (!priv || !priv->has_spk_cnt)
 222                 spk_cnt = 0;
 223         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 224                 spk_cnt = readl(&regs->hs_spklen);
 225         else
 226                 spk_cnt = readl(&regs->fs_spklen);
 227         if (scl_sda_cfg) {
 228                 config->sda_hold = scl_sda_cfg->sda_hold;
 229                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 230                         config->scl_hcnt = scl_sda_cfg->ss_hcnt;
 231                         config->scl_lcnt = scl_sda_cfg->ss_lcnt;
 232                 } else {
 233                         config->scl_hcnt = scl_sda_cfg->fs_hcnt;
 234                         config->scl_lcnt = scl_sda_cfg->fs_lcnt;
 235                 }
 236         } else {
 237                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 238                                          config);
 239                 if (ret)
 240                         return log_msg_ret("gen_confg", ret);
 241         }
 242         config->speed_mode = i2c_spd;
 243
 244         return 0;
 245 }
 246
 247 /*
 248  * _dw_i2c_set_bus_speed - Set the i2c speed
 249  * @speed:      required i2c speed
 250  *
 251  * Set the i2c speed.
 252  */
 253 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 254                                  unsigned int speed, unsigned int bus_clk)
 255 {
 256         struct dw_i2c_speed_config config;
 257         unsigned int cntl;
 258         unsigned int ena;
 259         int ret;
 260
 261         ret = calc_bus_speed(priv, speed, bus_clk, &config);
 262         if (ret)
 263                 return ret;
 264
 265         /* Get enable setting for restore later */
 266         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 267
 268         /* to set speed cltr must be disabled */
 269         dw_i2c_enable(i2c_base, false);
 270
 271         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 272
 273         switch (config.speed_mode) {
 274         case IC_SPEED_MODE_HIGH:
 275                 cntl |= IC_CON_SPD_SS;
 276                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 277                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 278                 break;
 279         case IC_SPEED_MODE_STANDARD:
 280                 cntl |= IC_CON_SPD_SS;
 281                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 282                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 283                 break;
 284         case IC_SPEED_MODE_FAST_PLUS:
 285         case IC_SPEED_MODE_FAST:
 286         default:
 287                 cntl |= IC_CON_SPD_FS;
 288                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 289                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 290                 break;
 291         }
 292
 293         writel(cntl, &i2c_base->ic_con);
 294
 295         /* Configure SDA Hold Time if required */
 296         if (config.sda_hold)
 297                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 298
 299         /* Restore back i2c now speed set */
 300         if (ena == IC_ENABLE_0B)
 301                 dw_i2c_enable(i2c_base, true);
 302
 303         return 0;
 304 }
 305
 306 /*
 307  * i2c_setaddress - Sets the target slave address
 308  * @i2c_addr:   target i2c address
 309  *
 310  * Sets the target slave address.
 311  */
 312 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 313 {
 314         /* Disable i2c */
 315         dw_i2c_enable(i2c_base, false);
 316
 317         writel(i2c_addr, &i2c_base->ic_tar);
 318
 319         /* Enable i2c */
 320         dw_i2c_enable(i2c_base, true);
 321 }
 322
 323 /*
 324  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 325  *
 326  * Flushes the i2c RX FIFO
 327  */
 328 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 329 {
 330         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 331                 readl(&i2c_base->ic_cmd_data);
 332 }
 333
 334 /*
 335  * i2c_wait_for_bb - Waits for bus busy
 336  *
 337  * Waits for bus busy
 338  */
 339 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 340 {
 341         unsigned long start_time_bb = get_timer(0);
 342
 343         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 344                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 345
 346                 /* Evaluate timeout */
 347                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 348                         return 1;
 349         }
 350
 351         return 0;
 352 }
 353
 354 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 355                          int alen)
 356 {
 357         if (i2c_wait_for_bb(i2c_base))
 358                 return 1;
 359
 360         i2c_setaddress(i2c_base, chip);
 361         while (alen) {
 362                 alen--;
 363                 /* high byte address going out first */
 364                 writel((addr >> (alen * 8)) & 0xff,
 365                        &i2c_base->ic_cmd_data);
 366         }
 367         return 0;
 368 }
 369
 370 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 371 {
 372         ulong start_stop_det = get_timer(0);
 373
 374         while (1) {
 375                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 376                         readl(&i2c_base->ic_clr_stop_det);
 377                         break;
 378                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 379                         break;
 380                 }
 381         }
 382
 383         if (i2c_wait_for_bb(i2c_base)) {
 384                 printf("Timed out waiting for bus\n");
 385                 return 1;
 386         }
 387
 388         i2c_flush_rxfifo(i2c_base);
 389
 390         return 0;
 391 }
 392
 393 /*
 394  * i2c_read - Read from i2c memory
 395  * @chip:       target i2c address
 396  * @addr:       address to read from
 397  * @alen:
 398  * @buffer:     buffer for read data
 399  * @len:        no of bytes to be read
 400  *
 401  * Read from i2c memory.
 402  */
 403 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 404                          int alen, u8 *buffer, int len)
 405 {
 406         unsigned long start_time_rx;
 407         unsigned int active = 0;
 408
 409 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 410         /*
 411          * EEPROM chips that implement "address overflow" are ones
 412          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 413          * address and the extra bits end up in the "chip address"
 414          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 415          * four 256 byte chips.
 416          *
 417          * Note that we consider the length of the address field to
 418          * still be one byte because the extra address bits are
 419          * hidden in the chip address.
 420          */
 421         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 422         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 423
 424         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 425               addr);
 426 #endif
 427
 428         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 429                 return 1;
 430
 431         start_time_rx = get_timer(0);
 432         while (len) {
 433                 if (!active) {
 434                         /*
 435                          * Avoid writing to ic_cmd_data multiple times
 436                          * in case this loop spins too quickly and the
 437                          * ic_status RFNE bit isn't set after the first
 438                          * write. Subsequent writes to ic_cmd_data can
 439                          * trigger spurious i2c transfer.
 440                          */
 441                         if (len == 1)
 442                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 443                         else
 444                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 445                         active = 1;
 446                 }
 447
 448                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 449                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 450                         len--;
 451                         start_time_rx = get_timer(0);
 452                         active = 0;
 453                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 454                         return 1;
 455                 }
 456         }
 457
 458         return i2c_xfer_finish(i2c_base);
 459 }
 460
 461 /*
 462  * i2c_write - Write to i2c memory
 463  * @chip:       target i2c address
 464  * @addr:       address to read from
 465  * @alen:
 466  * @buffer:     buffer for read data
 467  * @len:        no of bytes to be read
 468  *
 469  * Write to i2c memory.
 470  */
 471 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 472                           int alen, u8 *buffer, int len)
 473 {
 474         int nb = len;
 475         unsigned long start_time_tx;
 476
 477 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 478         /*
 479          * EEPROM chips that implement "address overflow" are ones
 480          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 481          * address and the extra bits end up in the "chip address"
 482          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 483          * four 256 byte chips.
 484          *
 485          * Note that we consider the length of the address field to
 486          * still be one byte because the extra address bits are
 487          * hidden in the chip address.
 488          */
 489         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 490         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 491
 492         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 493               addr);
 494 #endif
 495
 496         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 497                 return 1;
 498
 499         start_time_tx = get_timer(0);
 500         while (len) {
 501                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 502                         if (--len == 0) {
 503                                 writel(*buffer | IC_STOP,
 504                                        &i2c_base->ic_cmd_data);
 505                         } else {
 506                                 writel(*buffer, &i2c_base->ic_cmd_data);
 507                         }
 508                         buffer++;
 509                         start_time_tx = get_timer(0);
 510
 511                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 512                                 printf("Timed out. i2c write Failed\n");
 513                                 return 1;
 514                 }
 515         }
 516
 517         return i2c_xfer_finish(i2c_base);
 518 }
 519
 520 /*
 521  * __dw_i2c_init - Init function
 522  * @speed:      required i2c speed
 523  * @slaveaddr:  slave address for the device
 524  *
 525  * Initialization function.
 526  */
 527 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 528 {
 529         int ret;
 530
 531         /* Disable i2c */
 532         ret = dw_i2c_enable(i2c_base, false);
 533         if (ret)
 534                 return ret;
 535
 536         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 537                &i2c_base->ic_con);
 538         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 539         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 540         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 541 #ifndef CONFIG_DM_I2C
 542         _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 543         writel(slaveaddr, &i2c_base->ic_sar);
 544 #endif
 545
 546         /* Enable i2c */
 547         ret = dw_i2c_enable(i2c_base, true);
 548         if (ret)
 549                 return ret;
 550
 551         return 0;
 552 }
 553
 554 #ifndef CONFIG_DM_I2C
 555 /*
 556  * The legacy I2C functions. These need to get removed once
 557  * all users of this driver are converted to DM.
 558  */
 559 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 560 {
 561         switch (adap->hwadapnr) {
 562 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 563         case 3:
 564                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 565 #endif
 566 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 567         case 2:
 568                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 569 #endif
 570 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 571         case 1:
 572                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 573 #endif
 574         case 0:
 575                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 576         default:
 577                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 578         }
 579
 580         return NULL;
 581 }
 582
 583 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 584                                          unsigned int speed)
 585 {
 586         adap->speed = speed;
 587         return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 588 }
 589
 590 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 591 {
 592         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 593 }
 594
 595 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 596                        int alen, u8 *buffer, int len)
 597 {
 598         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 599 }
 600
 601 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 602                         int alen, u8 *buffer, int len)
 603 {
 604         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 605 }
 606
 607 /* dw_i2c_probe - Probe the i2c chip */
 608 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 609 {
 610         struct i2c_regs *i2c_base = i2c_get_base(adap);
 611         u32 tmp;
 612         int ret;
 613
 614         /*
 615          * Try to read the first location of the chip.
 616          */
 617         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 618         if (ret)
 619                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 620
 621         return ret;
 622 }
 623
 624 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 625                          dw_i2c_write, dw_i2c_set_bus_speed,
 626                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 627
 628 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 629 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 630                          dw_i2c_write, dw_i2c_set_bus_speed,
 631                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 632 #endif
 633
 634 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 635 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 636                          dw_i2c_write, dw_i2c_set_bus_speed,
 637                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 638 #endif
 639
 640 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 641 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 642                          dw_i2c_write, dw_i2c_set_bus_speed,
 643                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 644 #endif
 645
 646 #else /* CONFIG_DM_I2C */
 647 /* The DM I2C functions */
 648
 649 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 650                                int nmsgs)
 651 {
 652         struct dw_i2c *i2c = dev_get_priv(bus);
 653         int ret;
 654
 655         debug("i2c_xfer: %d messages\n", nmsgs);
 656         for (; nmsgs > 0; nmsgs--, msg++) {
 657                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 658                 if (msg->flags & I2C_M_RD) {
 659                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 660                                             msg->buf, msg->len);
 661                 } else {
 662                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 663                                              msg->buf, msg->len);
 664                 }
 665                 if (ret) {
 666                         debug("i2c_write: error sending\n");
 667                         return -EREMOTEIO;
 668                 }
 669         }
 670
 671         return 0;
 672 }
 673
 674 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 675 {
 676         struct dw_i2c *i2c = dev_get_priv(bus);
 677         ulong rate;
 678
 679 #if CONFIG_IS_ENABLED(CLK)
 680         rate = clk_get_rate(&i2c->clk);
 681         if (IS_ERR_VALUE(rate))
 682                 return -EINVAL;
 683 #else
 684         rate = IC_CLK;
 685 #endif
 686         return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 687 }
 688
 689 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 690                                      uint chip_flags)
 691 {
 692         struct dw_i2c *i2c = dev_get_priv(bus);
 693         struct i2c_regs *i2c_base = i2c->regs;
 694         u32 tmp;
 695         int ret;
 696
 697         /* Try to read the first location of the chip */
 698         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 699         if (ret)
 700                 __dw_i2c_init(i2c_base, 0, 0);
 701
 702         return ret;
 703 }
 704
 705 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 706 {
 707         struct dw_i2c *priv = dev_get_priv(bus);
 708         int ret;
 709
 710         if (!priv->regs)
 711                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 712         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 713         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 714         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 715
 716         ret = reset_get_bulk(bus, &priv->resets);
 717         if (ret)
 718                 dev_warn(bus, "Can't get reset: %d\n", ret);
 719         else
 720                 reset_deassert_bulk(&priv->resets);
 721
 722 #if CONFIG_IS_ENABLED(CLK)
 723         ret = clk_get_by_index(bus, 0, &priv->clk);
 724         if (ret)
 725                 return ret;
 726
 727         ret = clk_enable(&priv->clk);
 728         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 729                 clk_free(&priv->clk);
 730                 dev_err(bus, "failed to enable clock\n");
 731                 return ret;
 732         }
 733 #endif
 734
 735         return 0;
 736 }
 737
 738 int designware_i2c_probe(struct udevice *bus)
 739 {
 740         struct dw_i2c *priv = dev_get_priv(bus);
 741
 742         return __dw_i2c_init(priv->regs, 0, 0);
 743 }
 744
 745 int designware_i2c_remove(struct udevice *dev)
 746 {
 747         struct dw_i2c *priv = dev_get_priv(dev);
 748
 749 #if CONFIG_IS_ENABLED(CLK)
 750         clk_disable(&priv->clk);
 751         clk_free(&priv->clk);
 752 #endif
 753
 754         return reset_release_bulk(&priv->resets);
 755 }
 756
 757 const struct dm_i2c_ops designware_i2c_ops = {
 758         .xfer           = designware_i2c_xfer,
 759         .probe_chip     = designware_i2c_probe_chip,
 760         .set_bus_speed  = designware_i2c_set_bus_speed,
 761 };
 762
 763 static const struct udevice_id designware_i2c_ids[] = {
 764         { .compatible = "snps,designware-i2c" },
 765         { }
 766 };
 767
 768 U_BOOT_DRIVER(i2c_designware) = {
 769         .name   = "i2c_designware",
 770         .id     = UCLASS_I2C,
 771         .of_match = designware_i2c_ids,
 772         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 773         .probe  = designware_i2c_probe,
 774         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 775         .remove = designware_i2c_remove,
 776         .flags  = DM_FLAG_OS_PREPARE,
 777         .ops    = &designware_i2c_ops,
 778 };
 779
 780 #endif /* CONFIG_DM_I2C */