drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <pci.h>
  14 #include <reset.h>
  15 #include <asm/io.h>
  16 #include <linux/delay.h>
  17 #include "designware_i2c.h"
  18 #include <dm/device_compat.h>
  19 #include <linux/err.h>
  20
  21 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  22 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  23 {
  24         u32 ena = enable ? IC_ENABLE_0B : 0;
  25
  26         writel(ena, &i2c_base->ic_enable);
  27
  28         return 0;
  29 }
  30 #else
  31 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  32 {
  33         u32 ena = enable ? IC_ENABLE_0B : 0;
  34         int timeout = 100;
  35
  36         do {
  37                 writel(ena, &i2c_base->ic_enable);
  38                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  39                         return 0;
  40
  41                 /*
  42                  * Wait 10 times the signaling period of the highest I2C
  43                  * transfer supported by the driver (for 400KHz this is
  44                  * 25us) as described in the DesignWare I2C databook.
  45                  */
  46                 udelay(25);
  47         } while (timeout--);
  48         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  49
  50         return -ETIMEDOUT;
  51 }
  52 #endif
  53
  54 /* High and low times in different speed modes (in ns) */
  55 enum {
  56         /* SDA Hold Time */
  57         DEFAULT_SDA_HOLD_TIME           = 300,
  58 };
  59
  60 /**
  61  * calc_counts() - Convert a period to a number of IC clk cycles
  62  *
  63  * @ic_clk: Input clock in Hz
  64  * @period_ns: Period to represent, in ns
  65  * @return calculated count
  66  */
  67 static uint calc_counts(uint ic_clk, uint period_ns)
  68 {
  69         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  70 }
  71
  72 /**
  73  * struct i2c_mode_info - Information about an I2C speed mode
  74  *
  75  * Each speed mode has its own characteristics. This struct holds these to aid
  76  * calculations in dw_i2c_calc_timing().
  77  *
  78  * @speed: Speed in Hz
  79  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  80  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  81  * @def_rise_time_ns: Default rise time in ns
  82  * @def_fall_time_ns: Default fall time in ns
  83  */
  84 struct i2c_mode_info {
  85         int speed;
  86         int min_scl_hightime_ns;
  87         int min_scl_lowtime_ns;
  88         int def_rise_time_ns;
  89         int def_fall_time_ns;
  90 };
  91
  92 static const struct i2c_mode_info info_for_mode[] = {
  93         [IC_SPEED_MODE_STANDARD] = {
  94                 I2C_SPEED_STANDARD_RATE,
  95                 MIN_SS_SCL_HIGHTIME,
  96                 MIN_SS_SCL_LOWTIME,
  97                 1000,
  98                 300,
  99         },
 100         [IC_SPEED_MODE_FAST] = {
 101                 I2C_SPEED_FAST_RATE,
 102                 MIN_FS_SCL_HIGHTIME,
 103                 MIN_FS_SCL_LOWTIME,
 104                 300,
 105                 300,
 106         },
 107         [IC_SPEED_MODE_FAST_PLUS] = {
 108                 I2C_SPEED_FAST_PLUS_RATE,
 109                 MIN_FP_SCL_HIGHTIME,
 110                 MIN_FP_SCL_LOWTIME,
 111                 260,
 112                 500,
 113         },
 114         [IC_SPEED_MODE_HIGH] = {
 115                 I2C_SPEED_HIGH_RATE,
 116                 MIN_HS_SCL_HIGHTIME,
 117                 MIN_HS_SCL_LOWTIME,
 118                 120,
 119                 120,
 120         },
 121 };
 122
 123 /**
 124  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 125  *
 126  * @priv: Bus private information (NULL if not using driver model)
 127  * @mode: Speed mode to use
 128  * @ic_clk: IC clock speed in Hz
 129  * @spk_cnt: Spike-suppression count
 130  * @config: Returns value to use
 131  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 132  */
 133 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 134                               int ic_clk, int spk_cnt,
 135                               struct dw_i2c_speed_config *config)
 136 {
 137         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 138         int hcnt, lcnt, period_cnt, diff, tot;
 139         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 140         const struct i2c_mode_info *info;
 141
 142         /*
 143          * Find the period, rise, fall, min tlow, and min thigh in terms of
 144          * counts of the IC clock
 145          */
 146         info = &info_for_mode[mode];
 147         period_cnt = ic_clk / info->speed;
 148         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 149                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 150         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 151                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 152         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 153         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 154         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 155         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 156
 157         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 158               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 159               spk_cnt);
 160
 161         /*
 162          * Back-solve for hcnt and lcnt according to the following equations:
 163          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 164          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 165          */
 166         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 167         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 168
 169         if (hcnt < 0 || lcnt < 0) {
 170                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 171                 return -EINVAL;
 172         }
 173
 174         /*
 175          * Now add things back up to ensure the period is hit. If it is off,
 176          * split the difference and bias to lcnt for remainder
 177          */
 178         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 179
 180         if (tot < period_cnt) {
 181                 diff = (period_cnt - tot) / 2;
 182                 hcnt += diff;
 183                 lcnt += diff;
 184                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 185                 lcnt += period_cnt - tot;
 186         }
 187
 188         config->scl_lcnt = lcnt;
 189         config->scl_hcnt = hcnt;
 190
 191         /* Use internal default unless other value is specified */
 192         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 193                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 194         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 195
 196         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 197               config->sda_hold);
 198
 199         return 0;
 200 }
 201
 202 static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
 203                           struct dw_i2c_speed_config *config)
 204 {
 205         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 206         struct i2c_regs *regs = priv->regs;
 207         enum i2c_speed_mode i2c_spd;
 208         u32 comp_param1;
 209         int spk_cnt;
 210         int ret;
 211
 212         comp_param1 = readl(&regs->comp_param1);
 213
 214         if (priv)
 215                 scl_sda_cfg = priv->scl_sda_cfg;
 216         /* Allow high speed if there is no config, or the config allows it */
 217         if (speed >= I2C_SPEED_HIGH_RATE)
 218                 i2c_spd = IC_SPEED_MODE_HIGH;
 219         else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
 220                 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
 221         else if (speed >= I2C_SPEED_FAST_RATE)
 222                 i2c_spd = IC_SPEED_MODE_FAST;
 223         else
 224                 i2c_spd = IC_SPEED_MODE_STANDARD;
 225
 226         /* Check is high speed possible and fall back to fast mode if not */
 227         if (i2c_spd == IC_SPEED_MODE_HIGH) {
 228                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 229                                 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
 230                         i2c_spd = IC_SPEED_MODE_FAST;
 231         }
 232
 233         /* Get the proper spike-suppression count based on target speed */
 234         if (!priv || !priv->has_spk_cnt)
 235                 spk_cnt = 0;
 236         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 237                 spk_cnt = readl(&regs->hs_spklen);
 238         else
 239                 spk_cnt = readl(&regs->fs_spklen);
 240         if (scl_sda_cfg) {
 241                 config->sda_hold = scl_sda_cfg->sda_hold;
 242                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 243                         config->scl_hcnt = scl_sda_cfg->ss_hcnt;
 244                         config->scl_lcnt = scl_sda_cfg->ss_lcnt;
 245                 } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
 246                         config->scl_hcnt = scl_sda_cfg->hs_hcnt;
 247                         config->scl_lcnt = scl_sda_cfg->hs_lcnt;
 248                 } else {
 249                         config->scl_hcnt = scl_sda_cfg->fs_hcnt;
 250                         config->scl_lcnt = scl_sda_cfg->fs_lcnt;
 251                 }
 252         } else {
 253                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 254                                          config);
 255                 if (ret)
 256                         return log_msg_ret("gen_confg", ret);
 257         }
 258         config->speed_mode = i2c_spd;
 259
 260         return 0;
 261 }
 262
 263 /*
 264  * _dw_i2c_set_bus_speed - Set the i2c speed
 265  * @speed:      required i2c speed
 266  *
 267  * Set the i2c speed.
 268  */
 269 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 270                                  unsigned int speed, unsigned int bus_clk)
 271 {
 272         struct dw_i2c_speed_config config;
 273         unsigned int cntl;
 274         unsigned int ena;
 275         int ret;
 276
 277         ret = calc_bus_speed(priv, speed, bus_clk, &config);
 278         if (ret)
 279                 return ret;
 280
 281         /* Get enable setting for restore later */
 282         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 283
 284         /* to set speed cltr must be disabled */
 285         dw_i2c_enable(i2c_base, false);
 286
 287         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 288
 289         switch (config.speed_mode) {
 290         case IC_SPEED_MODE_HIGH:
 291                 cntl |= IC_CON_SPD_HS;
 292                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 293                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 294                 break;
 295         case IC_SPEED_MODE_STANDARD:
 296                 cntl |= IC_CON_SPD_SS;
 297                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 298                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 299                 break;
 300         case IC_SPEED_MODE_FAST_PLUS:
 301         case IC_SPEED_MODE_FAST:
 302         default:
 303                 cntl |= IC_CON_SPD_FS;
 304                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 305                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 306                 break;
 307         }
 308
 309         writel(cntl, &i2c_base->ic_con);
 310
 311         /* Configure SDA Hold Time if required */
 312         if (config.sda_hold)
 313                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 314
 315         /* Restore back i2c now speed set */
 316         if (ena == IC_ENABLE_0B)
 317                 dw_i2c_enable(i2c_base, true);
 318
 319         return 0;
 320 }
 321
 322 /*
 323  * i2c_setaddress - Sets the target slave address
 324  * @i2c_addr:   target i2c address
 325  *
 326  * Sets the target slave address.
 327  */
 328 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 329 {
 330         /* Disable i2c */
 331         dw_i2c_enable(i2c_base, false);
 332
 333         writel(i2c_addr, &i2c_base->ic_tar);
 334
 335         /* Enable i2c */
 336         dw_i2c_enable(i2c_base, true);
 337 }
 338
 339 /*
 340  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 341  *
 342  * Flushes the i2c RX FIFO
 343  */
 344 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 345 {
 346         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 347                 readl(&i2c_base->ic_cmd_data);
 348 }
 349
 350 /*
 351  * i2c_wait_for_bb - Waits for bus busy
 352  *
 353  * Waits for bus busy
 354  */
 355 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 356 {
 357         unsigned long start_time_bb = get_timer(0);
 358
 359         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 360                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 361
 362                 /* Evaluate timeout */
 363                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 364                         return 1;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 371                          int alen)
 372 {
 373         if (i2c_wait_for_bb(i2c_base))
 374                 return 1;
 375
 376         i2c_setaddress(i2c_base, chip);
 377         while (alen) {
 378                 alen--;
 379                 /* high byte address going out first */
 380                 writel((addr >> (alen * 8)) & 0xff,
 381                        &i2c_base->ic_cmd_data);
 382         }
 383         return 0;
 384 }
 385
 386 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 387 {
 388         ulong start_stop_det = get_timer(0);
 389
 390         while (1) {
 391                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 392                         readl(&i2c_base->ic_clr_stop_det);
 393                         break;
 394                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 395                         break;
 396                 }
 397         }
 398
 399         if (i2c_wait_for_bb(i2c_base)) {
 400                 printf("Timed out waiting for bus\n");
 401                 return 1;
 402         }
 403
 404         i2c_flush_rxfifo(i2c_base);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * i2c_read - Read from i2c memory
 411  * @chip:       target i2c address
 412  * @addr:       address to read from
 413  * @alen:
 414  * @buffer:     buffer for read data
 415  * @len:        no of bytes to be read
 416  *
 417  * Read from i2c memory.
 418  */
 419 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 420                          int alen, u8 *buffer, int len)
 421 {
 422         unsigned long start_time_rx;
 423         unsigned int active = 0;
 424
 425 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 426         /*
 427          * EEPROM chips that implement "address overflow" are ones
 428          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 429          * address and the extra bits end up in the "chip address"
 430          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 431          * four 256 byte chips.
 432          *
 433          * Note that we consider the length of the address field to
 434          * still be one byte because the extra address bits are
 435          * hidden in the chip address.
 436          */
 437         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 438         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 439
 440         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 441               addr);
 442 #endif
 443
 444         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 445                 return 1;
 446
 447         start_time_rx = get_timer(0);
 448         while (len) {
 449                 if (!active) {
 450                         /*
 451                          * Avoid writing to ic_cmd_data multiple times
 452                          * in case this loop spins too quickly and the
 453                          * ic_status RFNE bit isn't set after the first
 454                          * write. Subsequent writes to ic_cmd_data can
 455                          * trigger spurious i2c transfer.
 456                          */
 457                         if (len == 1)
 458                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 459                         else
 460                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 461                         active = 1;
 462                 }
 463
 464                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 465                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 466                         len--;
 467                         start_time_rx = get_timer(0);
 468                         active = 0;
 469                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 470                         return 1;
 471                 }
 472         }
 473
 474         return i2c_xfer_finish(i2c_base);
 475 }
 476
 477 /*
 478  * i2c_write - Write to i2c memory
 479  * @chip:       target i2c address
 480  * @addr:       address to read from
 481  * @alen:
 482  * @buffer:     buffer for read data
 483  * @len:        no of bytes to be read
 484  *
 485  * Write to i2c memory.
 486  */
 487 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 488                           int alen, u8 *buffer, int len)
 489 {
 490         int nb = len;
 491         unsigned long start_time_tx;
 492
 493 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 494         /*
 495          * EEPROM chips that implement "address overflow" are ones
 496          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 497          * address and the extra bits end up in the "chip address"
 498          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 499          * four 256 byte chips.
 500          *
 501          * Note that we consider the length of the address field to
 502          * still be one byte because the extra address bits are
 503          * hidden in the chip address.
 504          */
 505         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 506         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 507
 508         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 509               addr);
 510 #endif
 511
 512         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 513                 return 1;
 514
 515         start_time_tx = get_timer(0);
 516         while (len) {
 517                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 518                         if (--len == 0) {
 519                                 writel(*buffer | IC_STOP,
 520                                        &i2c_base->ic_cmd_data);
 521                         } else {
 522                                 writel(*buffer, &i2c_base->ic_cmd_data);
 523                         }
 524                         buffer++;
 525                         start_time_tx = get_timer(0);
 526
 527                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 528                                 printf("Timed out. i2c write Failed\n");
 529                                 return 1;
 530                 }
 531         }
 532
 533         return i2c_xfer_finish(i2c_base);
 534 }
 535
 536 /*
 537  * __dw_i2c_init - Init function
 538  * @speed:      required i2c speed
 539  * @slaveaddr:  slave address for the device
 540  *
 541  * Initialization function.
 542  */
 543 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 544 {
 545         int ret;
 546
 547         /* Disable i2c */
 548         ret = dw_i2c_enable(i2c_base, false);
 549         if (ret)
 550                 return ret;
 551
 552         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 553                &i2c_base->ic_con);
 554         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 555         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 556         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 557 #ifndef CONFIG_DM_I2C
 558         _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 559         writel(slaveaddr, &i2c_base->ic_sar);
 560 #endif
 561
 562         /* Enable i2c */
 563         ret = dw_i2c_enable(i2c_base, true);
 564         if (ret)
 565                 return ret;
 566
 567         return 0;
 568 }
 569
 570 #ifndef CONFIG_DM_I2C
 571 /*
 572  * The legacy I2C functions. These need to get removed once
 573  * all users of this driver are converted to DM.
 574  */
 575 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 576 {
 577         switch (adap->hwadapnr) {
 578 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 579         case 3:
 580                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 581 #endif
 582 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 583         case 2:
 584                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 585 #endif
 586 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 587         case 1:
 588                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 589 #endif
 590         case 0:
 591                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 592         default:
 593                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 594         }
 595
 596         return NULL;
 597 }
 598
 599 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 600                                          unsigned int speed)
 601 {
 602         adap->speed = speed;
 603         return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 604 }
 605
 606 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 607 {
 608         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 609 }
 610
 611 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 612                        int alen, u8 *buffer, int len)
 613 {
 614         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 615 }
 616
 617 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 618                         int alen, u8 *buffer, int len)
 619 {
 620         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 621 }
 622
 623 /* dw_i2c_probe - Probe the i2c chip */
 624 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 625 {
 626         struct i2c_regs *i2c_base = i2c_get_base(adap);
 627         u32 tmp;
 628         int ret;
 629
 630         /*
 631          * Try to read the first location of the chip.
 632          */
 633         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 634         if (ret)
 635                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 636
 637         return ret;
 638 }
 639
 640 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 641                          dw_i2c_write, dw_i2c_set_bus_speed,
 642                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 643
 644 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 645 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 646                          dw_i2c_write, dw_i2c_set_bus_speed,
 647                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 648 #endif
 649
 650 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 651 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 652                          dw_i2c_write, dw_i2c_set_bus_speed,
 653                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 654 #endif
 655
 656 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 657 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 658                          dw_i2c_write, dw_i2c_set_bus_speed,
 659                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 660 #endif
 661
 662 #else /* CONFIG_DM_I2C */
 663 /* The DM I2C functions */
 664
 665 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 666                                int nmsgs)
 667 {
 668         struct dw_i2c *i2c = dev_get_priv(bus);
 669         int ret;
 670
 671         debug("i2c_xfer: %d messages\n", nmsgs);
 672         for (; nmsgs > 0; nmsgs--, msg++) {
 673                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 674                 if (msg->flags & I2C_M_RD) {
 675                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 676                                             msg->buf, msg->len);
 677                 } else {
 678                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 679                                              msg->buf, msg->len);
 680                 }
 681                 if (ret) {
 682                         debug("i2c_write: error sending\n");
 683                         return -EREMOTEIO;
 684                 }
 685         }
 686
 687         return 0;
 688 }
 689
 690 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 691 {
 692         struct dw_i2c *i2c = dev_get_priv(bus);
 693         ulong rate;
 694
 695 #if CONFIG_IS_ENABLED(CLK)
 696         rate = clk_get_rate(&i2c->clk);
 697         if (IS_ERR_VALUE(rate))
 698                 return -EINVAL;
 699 #else
 700         rate = IC_CLK;
 701 #endif
 702         return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 703 }
 704
 705 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 706                                      uint chip_flags)
 707 {
 708         struct dw_i2c *i2c = dev_get_priv(bus);
 709         struct i2c_regs *i2c_base = i2c->regs;
 710         u32 tmp;
 711         int ret;
 712
 713         /* Try to read the first location of the chip */
 714         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 715         if (ret)
 716                 __dw_i2c_init(i2c_base, 0, 0);
 717
 718         return ret;
 719 }
 720
 721 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 722 {
 723         struct dw_i2c *priv = dev_get_priv(bus);
 724         int ret;
 725
 726         if (!priv->regs)
 727                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 728         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 729         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 730         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 731
 732         ret = reset_get_bulk(bus, &priv->resets);
 733         if (ret)
 734                 dev_warn(bus, "Can't get reset: %d\n", ret);
 735         else
 736                 reset_deassert_bulk(&priv->resets);
 737
 738 #if CONFIG_IS_ENABLED(CLK)
 739         ret = clk_get_by_index(bus, 0, &priv->clk);
 740         if (ret)
 741                 return ret;
 742
 743         ret = clk_enable(&priv->clk);
 744         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 745                 clk_free(&priv->clk);
 746                 dev_err(bus, "failed to enable clock\n");
 747                 return ret;
 748         }
 749 #endif
 750
 751         return 0;
 752 }
 753
 754 int designware_i2c_probe(struct udevice *bus)
 755 {
 756         struct dw_i2c *priv = dev_get_priv(bus);
 757
 758         return __dw_i2c_init(priv->regs, 0, 0);
 759 }
 760
 761 int designware_i2c_remove(struct udevice *dev)
 762 {
 763         struct dw_i2c *priv = dev_get_priv(dev);
 764
 765 #if CONFIG_IS_ENABLED(CLK)
 766         clk_disable(&priv->clk);
 767         clk_free(&priv->clk);
 768 #endif
 769
 770         return reset_release_bulk(&priv->resets);
 771 }
 772
 773 const struct dm_i2c_ops designware_i2c_ops = {
 774         .xfer           = designware_i2c_xfer,
 775         .probe_chip     = designware_i2c_probe_chip,
 776         .set_bus_speed  = designware_i2c_set_bus_speed,
 777 };
 778
 779 static const struct udevice_id designware_i2c_ids[] = {
 780         { .compatible = "snps,designware-i2c" },
 781         { }
 782 };
 783
 784 U_BOOT_DRIVER(i2c_designware) = {
 785         .name   = "i2c_designware",
 786         .id     = UCLASS_I2C,
 787         .of_match = designware_i2c_ids,
 788         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 789         .probe  = designware_i2c_probe,
 790         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 791         .remove = designware_i2c_remove,
 792         .flags  = DM_FLAG_OS_PREPARE,
 793         .ops    = &designware_i2c_ops,
 794 };
 795
 796 #endif /* CONFIG_DM_I2C */