drivers/i2c/davinci_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI DaVinci (TMS320DM644x) I2C driver.
   4  *
   5  * (C) Copyright 2012-2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
   8  * --------------------------------------------------------
   9  *
  10  * NOTE: This driver should be converted to driver model before June 2017.
  11  * Please see doc/driver-model/i2c-howto.rst for instructions.
  12  */
  13
  14 #include <common.h>
  15 #include <i2c.h>
  16 #include <dm.h>
  17 #include <log.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/i2c_defs.h>
  20 #include <asm/io.h>
  21 #include "davinci_i2c.h"
  22
  23 #ifdef CONFIG_DM_I2C
  24 /* Information about i2c controller */
  25 struct i2c_bus {
  26         int                     id;
  27         uint                    speed;
  28         struct i2c_regs         *regs;
  29 };
  30 #endif
  31
  32 #define CHECK_NACK() \
  33         do {\
  34                 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
  35                         REG(&(i2c_base->i2c_con)) = 0;\
  36                         return 1;\
  37                 } \
  38         } while (0)
  39
  40 static int _wait_for_bus(struct i2c_regs *i2c_base)
  41 {
  42         int     stat, timeout;
  43
  44         REG(&(i2c_base->i2c_stat)) = 0xffff;
  45
  46         for (timeout = 0; timeout < 10; timeout++) {
  47                 stat = REG(&(i2c_base->i2c_stat));
  48                 if (!((stat) & I2C_STAT_BB)) {
  49                         REG(&(i2c_base->i2c_stat)) = 0xffff;
  50                         return 0;
  51                 }
  52
  53                 REG(&(i2c_base->i2c_stat)) = stat;
  54                 udelay(50000);
  55         }
  56
  57         REG(&(i2c_base->i2c_stat)) = 0xffff;
  58         return 1;
  59 }
  60
  61 static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
  62 {
  63         int     stat, timeout;
  64
  65         for (timeout = 0; timeout < 10; timeout++) {
  66                 udelay(1000);
  67                 stat = REG(&(i2c_base->i2c_stat));
  68                 if (stat & mask)
  69                         return stat;
  70         }
  71
  72         REG(&(i2c_base->i2c_stat)) = 0xffff;
  73         return stat | I2C_TIMEOUT;
  74 }
  75
  76 static void _flush_rx(struct i2c_regs *i2c_base)
  77 {
  78         while (1) {
  79                 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
  80                         break;
  81
  82                 REG(&(i2c_base->i2c_drr));
  83                 REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
  84                 udelay(1000);
  85         }
  86 }
  87
  88 static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
  89                                   uint speed)
  90 {
  91         uint32_t        div, psc;
  92
  93         psc = 2;
  94         /* SCLL + SCLH */
  95         div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
  96         REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
  97         REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
  98         REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
  99
 100         return 0;
 101 }
 102
 103 static void _davinci_i2c_init(struct i2c_regs *i2c_base,
 104                               uint speed, int slaveadd)
 105 {
 106         if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
 107                 REG(&(i2c_base->i2c_con)) = 0;
 108                 udelay(50000);
 109         }
 110
 111         _davinci_i2c_setspeed(i2c_base, speed);
 112
 113         REG(&(i2c_base->i2c_oa)) = slaveadd;
 114         REG(&(i2c_base->i2c_cnt)) = 0;
 115
 116         /* Interrupts must be enabled or I2C module won't work */
 117         REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
 118                 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
 119
 120         /* Now enable I2C controller (get it out of reset) */
 121         REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
 122
 123         udelay(1000);
 124 }
 125
 126 static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
 127                              uint32_t addr, int alen, uint8_t *buf, int len)
 128 {
 129         uint32_t        tmp;
 130         int             i;
 131
 132         if ((alen < 0) || (alen > 2)) {
 133                 printf("%s(): bogus address length %x\n", __func__, alen);
 134                 return 1;
 135         }
 136
 137         if (_wait_for_bus(i2c_base))
 138                 return 1;
 139
 140         if (alen != 0) {
 141                 /* Start address phase */
 142                 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
 143                 REG(&(i2c_base->i2c_cnt)) = alen;
 144                 REG(&(i2c_base->i2c_sa)) = chip;
 145                 REG(&(i2c_base->i2c_con)) = tmp;
 146
 147                 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 148
 149                 CHECK_NACK();
 150
 151                 switch (alen) {
 152                 case 2:
 153                         /* Send address MSByte */
 154                         if (tmp & I2C_STAT_XRDY) {
 155                                 REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
 156                         } else {
 157                                 REG(&(i2c_base->i2c_con)) = 0;
 158                                 return 1;
 159                         }
 160
 161                         tmp = _poll_i2c_irq(i2c_base,
 162                                             I2C_STAT_XRDY | I2C_STAT_NACK);
 163
 164                         CHECK_NACK();
 165                         /* No break, fall through */
 166                 case 1:
 167                         /* Send address LSByte */
 168                         if (tmp & I2C_STAT_XRDY) {
 169                                 REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
 170                         } else {
 171                                 REG(&(i2c_base->i2c_con)) = 0;
 172                                 return 1;
 173                         }
 174
 175                         tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY |
 176                                             I2C_STAT_NACK | I2C_STAT_ARDY);
 177
 178                         CHECK_NACK();
 179
 180                         if (!(tmp & I2C_STAT_ARDY)) {
 181                                 REG(&(i2c_base->i2c_con)) = 0;
 182                                 return 1;
 183                         }
 184                 }
 185         }
 186
 187         /* Address phase is over, now read 'len' bytes and stop */
 188         tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
 189         REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
 190         REG(&(i2c_base->i2c_sa)) = chip;
 191         REG(&(i2c_base->i2c_con)) = tmp;
 192
 193         for (i = 0; i < len; i++) {
 194                 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
 195                                    I2C_STAT_ROVR);
 196
 197                 CHECK_NACK();
 198
 199                 if (tmp & I2C_STAT_RRDY) {
 200                         buf[i] = REG(&(i2c_base->i2c_drr));
 201                 } else {
 202                         REG(&(i2c_base->i2c_con)) = 0;
 203                         return 1;
 204                 }
 205         }
 206
 207         tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
 208
 209         CHECK_NACK();
 210
 211         if (!(tmp & I2C_STAT_SCD)) {
 212                 REG(&(i2c_base->i2c_con)) = 0;
 213                 return 1;
 214         }
 215
 216         _flush_rx(i2c_base);
 217         REG(&(i2c_base->i2c_stat)) = 0xffff;
 218         REG(&(i2c_base->i2c_cnt)) = 0;
 219         REG(&(i2c_base->i2c_con)) = 0;
 220
 221         return 0;
 222 }
 223
 224 static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
 225                               uint32_t addr, int alen, uint8_t *buf, int len)
 226 {
 227         uint32_t        tmp;
 228         int             i;
 229
 230         if ((alen < 0) || (alen > 2)) {
 231                 printf("%s(): bogus address length %x\n", __func__, alen);
 232                 return 1;
 233         }
 234         if (len < 0) {
 235                 printf("%s(): bogus length %x\n", __func__, len);
 236                 return 1;
 237         }
 238
 239         if (_wait_for_bus(i2c_base))
 240                 return 1;
 241
 242         /* Start address phase */
 243         tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
 244                 I2C_CON_TRX | I2C_CON_STP;
 245         REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
 246                 len & 0xffff : (len & 0xffff) + alen;
 247         REG(&(i2c_base->i2c_sa)) = chip;
 248         REG(&(i2c_base->i2c_con)) = tmp;
 249
 250         switch (alen) {
 251         case 2:
 252                 /* Send address MSByte */
 253                 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 254
 255                 CHECK_NACK();
 256
 257                 if (tmp & I2C_STAT_XRDY) {
 258                         REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
 259                 } else {
 260                         REG(&(i2c_base->i2c_con)) = 0;
 261                         return 1;
 262                 }
 263                 /* No break, fall through */
 264         case 1:
 265                 /* Send address LSByte */
 266                 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 267
 268                 CHECK_NACK();
 269
 270                 if (tmp & I2C_STAT_XRDY) {
 271                         REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
 272                 } else {
 273                         REG(&(i2c_base->i2c_con)) = 0;
 274                         return 1;
 275                 }
 276         }
 277
 278         for (i = 0; i < len; i++) {
 279                 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
 280
 281                 CHECK_NACK();
 282
 283                 if (tmp & I2C_STAT_XRDY)
 284                         REG(&(i2c_base->i2c_dxr)) = buf[i];
 285                 else
 286                         return 1;
 287         }
 288
 289         tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
 290
 291         CHECK_NACK();
 292
 293         if (!(tmp & I2C_STAT_SCD)) {
 294                 REG(&(i2c_base->i2c_con)) = 0;
 295                 return 1;
 296         }
 297
 298         _flush_rx(i2c_base);
 299         REG(&(i2c_base->i2c_stat)) = 0xffff;
 300         REG(&(i2c_base->i2c_cnt)) = 0;
 301         REG(&(i2c_base->i2c_con)) = 0;
 302
 303         return 0;
 304 }
 305
 306 static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
 307 {
 308         int     rc = 1;
 309
 310         if (chip == REG(&(i2c_base->i2c_oa)))
 311                 return rc;
 312
 313         REG(&(i2c_base->i2c_con)) = 0;
 314         if (_wait_for_bus(i2c_base))
 315                 return 1;
 316
 317         /* try to read one byte from current (or only) address */
 318         REG(&(i2c_base->i2c_cnt)) = 1;
 319         REG(&(i2c_base->i2c_sa))  = chip;
 320         REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
 321                                      I2C_CON_STP);
 322         udelay(50000);
 323
 324         if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
 325                 rc = 0;
 326                 _flush_rx(i2c_base);
 327                 REG(&(i2c_base->i2c_stat)) = 0xffff;
 328         } else {
 329                 REG(&(i2c_base->i2c_stat)) = 0xffff;
 330                 REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
 331                 udelay(20000);
 332                 if (_wait_for_bus(i2c_base))
 333                         return 1;
 334         }
 335
 336         _flush_rx(i2c_base);
 337         REG(&(i2c_base->i2c_stat)) = 0xffff;
 338         REG(&(i2c_base->i2c_cnt)) = 0;
 339         return rc;
 340 }
 341
 342 #ifndef CONFIG_DM_I2C
 343 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
 344 {
 345         switch (adap->hwadapnr) {
 346 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 347         case 2:
 348                 return (struct i2c_regs *)I2C2_BASE;
 349 #endif
 350 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 351         case 1:
 352                 return (struct i2c_regs *)I2C1_BASE;
 353 #endif
 354         case 0:
 355                 return (struct i2c_regs *)I2C_BASE;
 356
 357         default:
 358                 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
 359         }
 360
 361         return NULL;
 362 }
 363
 364 static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 365 {
 366         struct i2c_regs *i2c_base = davinci_get_base(adap);
 367         uint ret;
 368
 369         adap->speed = speed;
 370         ret =  _davinci_i2c_setspeed(i2c_base, speed);
 371
 372         return ret;
 373 }
 374
 375 static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
 376                              int slaveadd)
 377 {
 378         struct i2c_regs *i2c_base = davinci_get_base(adap);
 379
 380         adap->speed = speed;
 381         _davinci_i2c_init(i2c_base, speed, slaveadd);
 382
 383         return;
 384 }
 385
 386 static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 387                             uint32_t addr, int alen, uint8_t *buf, int len)
 388 {
 389         struct i2c_regs *i2c_base = davinci_get_base(adap);
 390         return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
 391 }
 392
 393 static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
 394                              uint32_t addr, int alen, uint8_t *buf, int len)
 395 {
 396         struct i2c_regs *i2c_base = davinci_get_base(adap);
 397
 398         return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
 399 }
 400
 401 static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
 402 {
 403         struct i2c_regs *i2c_base = davinci_get_base(adap);
 404
 405         return _davinci_i2c_probe_chip(i2c_base, chip);
 406 }
 407
 408 U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
 409                          davinci_i2c_read, davinci_i2c_write,
 410                          davinci_i2c_setspeed,
 411                          CONFIG_SYS_DAVINCI_I2C_SPEED,
 412                          CONFIG_SYS_DAVINCI_I2C_SLAVE,
 413                          0)
 414
 415 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 416 U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
 417                          davinci_i2c_read, davinci_i2c_write,
 418                          davinci_i2c_setspeed,
 419                          CONFIG_SYS_DAVINCI_I2C_SPEED1,
 420                          CONFIG_SYS_DAVINCI_I2C_SLAVE1,
 421                          1)
 422 #endif
 423
 424 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 425 U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
 426                          davinci_i2c_read, davinci_i2c_write,
 427                          davinci_i2c_setspeed,
 428                          CONFIG_SYS_DAVINCI_I2C_SPEED2,
 429                          CONFIG_SYS_DAVINCI_I2C_SLAVE2,
 430                          2)
 431 #endif
 432
 433 #else /* CONFIG_DM_I2C */
 434
 435 static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 436                           int nmsgs)
 437 {
 438         struct i2c_bus *i2c_bus = dev_get_priv(bus);
 439         int ret;
 440
 441         debug("i2c_xfer: %d messages\n", nmsgs);
 442         for (; nmsgs > 0; nmsgs--, msg++) {
 443                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 444                 if (msg->flags & I2C_M_RD) {
 445                         ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
 446                                 0, 0, msg->buf, msg->len);
 447                 } else {
 448                         ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
 449                                 0, 0, msg->buf, msg->len);
 450                 }
 451                 if (ret) {
 452                         debug("i2c_write: error sending\n");
 453                         return -EREMOTEIO;
 454                 }
 455         }
 456
 457         return ret;
 458 }
 459
 460 static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
 461 {
 462         struct i2c_bus *i2c_bus = dev_get_priv(dev);
 463
 464         i2c_bus->speed = speed;
 465         return _davinci_i2c_setspeed(i2c_bus->regs, speed);
 466 }
 467
 468 static int davinci_i2c_probe(struct udevice *dev)
 469 {
 470         struct i2c_bus *i2c_bus = dev_get_priv(dev);
 471
 472         i2c_bus->id = dev->seq;
 473         i2c_bus->regs = (struct i2c_regs *)devfdt_get_addr(dev);
 474
 475         i2c_bus->speed = 100000;
 476          _davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);
 477
 478         return 0;
 479 }
 480
 481 static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 482                                   uint chip_flags)
 483 {
 484         struct i2c_bus *i2c_bus = dev_get_priv(bus);
 485
 486         return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
 487 }
 488
 489 static const struct dm_i2c_ops davinci_i2c_ops = {
 490         .xfer           = davinci_i2c_xfer,
 491         .probe_chip     = davinci_i2c_probe_chip,
 492         .set_bus_speed  = davinci_i2c_set_speed,
 493 };
 494
 495 static const struct udevice_id davinci_i2c_ids[] = {
 496         { .compatible = "ti,davinci-i2c"},
 497         { .compatible = "ti,keystone-i2c"},
 498         { }
 499 };
 500
 501 U_BOOT_DRIVER(i2c_davinci) = {
 502         .name   = "i2c_davinci",
 503         .id     = UCLASS_I2C,
 504         .of_match = davinci_i2c_ids,
 505         .probe  = davinci_i2c_probe,
 506         .priv_auto_alloc_size = sizeof(struct i2c_bus),
 507         .ops    = &davinci_i2c_ops,
 508 };
 509
 510 #endif /* CONFIG_DM_I2C */