1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Copyright 2016 IBM Corporation
5 * Copyright 2017 Google, Inc.
16 #include <asm/arch/scu_ast2500.h>
17 #include <linux/err.h>
21 #define I2C_TIMEOUT_US 100000
22 #define I2C_SLEEP_STEP_US 20
24 #define HIGHSPEED_TTIMEOUT 3
30 /* This device's clock */
32 /* Device registers */
33 struct ast_i2c_regs *regs;
39 * Given desired divider ratio, return the value that needs to be set
40 * in Clock and AC Timing Control register
42 static u32 get_clk_reg_val(ulong divider_ratio)
45 ulong scl_low, scl_high, data;
47 for (div = 0; divider_ratio >= 16; div++) {
48 inc |= (divider_ratio & 1);
52 scl_low = (divider_ratio >> 1) - 1;
53 scl_high = divider_ratio - scl_low - 2;
54 data = I2CD_CACTC_BASE
55 | (scl_high << I2CD_TCKHIGH_SHIFT)
56 | (scl_low << I2CD_TCKLOW_SHIFT)
57 | (div << I2CD_BASE_DIV_SHIFT);
62 static void ast_i2c_clear_interrupts(struct udevice *dev)
64 struct ast_i2c_priv *priv = dev_get_priv(dev);
66 writel(~0, &priv->regs->isr);
69 static void ast_i2c_init_bus(struct udevice *dev)
71 struct ast_i2c_priv *priv = dev_get_priv(dev);
74 writel(0, &priv->regs->fcr);
75 /* Enable Master Mode. Assuming single-master */
78 | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
80 /* Enable Interrupts */
81 writel(I2CD_INTR_TX_ACK
84 | I2CD_INTR_BUS_RECOVER_DONE
85 | I2CD_INTR_NORMAL_STOP
86 | I2CD_INTR_ABNORMAL, &priv->regs->icr);
89 static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
91 struct ast_i2c_priv *priv = dev_get_priv(dev);
94 priv->regs = devfdt_get_addr_ptr(dev);
95 if (IS_ERR(priv->regs))
96 return PTR_ERR(priv->regs);
98 ret = clk_get_by_index(dev, 0, &priv->clk);
100 debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
108 static int ast_i2c_probe(struct udevice *dev)
110 struct ast2500_scu *scu;
112 debug("Enabling I2C%u\n", dev->seq);
115 * Get all I2C devices out of Reset.
116 * Only needs to be done once, but doing it for every
117 * device does not hurt.
121 clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
124 ast_i2c_init_bus(dev);
129 static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
131 struct ast_i2c_priv *priv = dev_get_priv(dev);
132 int timeout = I2C_TIMEOUT_US;
134 while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
135 udelay(I2C_SLEEP_STEP_US);
136 timeout -= I2C_SLEEP_STEP_US;
139 ast_i2c_clear_interrupts(dev);
146 static int ast_i2c_send_stop(struct udevice *dev)
148 struct ast_i2c_priv *priv = dev_get_priv(dev);
150 writel(I2CD_M_STOP_CMD, &priv->regs->csr);
152 return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
155 static int ast_i2c_wait_tx(struct udevice *dev)
157 struct ast_i2c_priv *priv = dev_get_priv(dev);
158 int timeout = I2C_TIMEOUT_US;
159 u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
160 u32 status = readl(&priv->regs->isr) & flag;
163 while (!status && timeout > 0) {
164 status = readl(&priv->regs->isr) & flag;
165 udelay(I2C_SLEEP_STEP_US);
166 timeout -= I2C_SLEEP_STEP_US;
169 if (status == I2CD_INTR_TX_NAK)
175 ast_i2c_clear_interrupts(dev);
180 static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
182 struct ast_i2c_priv *priv = dev_get_priv(dev);
184 /* Start and Send Device Address */
185 writel(devaddr, &priv->regs->trbbr);
186 writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
188 return ast_i2c_wait_tx(dev);
191 static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
192 size_t len, bool send_stop)
194 struct ast_i2c_priv *priv = dev_get_priv(dev);
195 u32 i2c_cmd = I2CD_M_RX_CMD;
198 ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
202 for (; len > 0; len--, buffer++) {
204 i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
205 writel(i2c_cmd, &priv->regs->csr);
206 ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
209 *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
210 >> I2CD_RX_DATA_SHIFT;
212 ast_i2c_clear_interrupts(dev);
215 return ast_i2c_send_stop(dev);
220 static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
221 *buffer, size_t len, bool send_stop)
223 struct ast_i2c_priv *priv = dev_get_priv(dev);
226 ret = ast_i2c_start_txn(dev, (chip_addr << 1));
230 for (; len > 0; len--, buffer++) {
231 writel(*buffer, &priv->regs->trbbr);
232 writel(I2CD_M_TX_CMD, &priv->regs->csr);
233 ret = ast_i2c_wait_tx(dev);
239 return ast_i2c_send_stop(dev);
244 static int ast_i2c_deblock(struct udevice *dev)
246 struct ast_i2c_priv *priv = dev_get_priv(dev);
247 struct ast_i2c_regs *regs = priv->regs;
248 u32 csr = readl(®s->csr);
249 bool sda_high = csr & I2CD_SDA_LINE_STS;
250 bool scl_high = csr & I2CD_SCL_LINE_STS;
253 if (sda_high && scl_high) {
254 /* Bus is idle, no deblocking needed. */
256 } else if (sda_high) {
257 /* Send stop command */
258 debug("Unterminated TXN in (%x), sending stop\n", csr);
259 ret = ast_i2c_send_stop(dev);
260 } else if (scl_high) {
261 /* Possibly stuck slave */
262 debug("Bus stuck (%x), attempting recovery\n", csr);
263 writel(I2CD_BUS_RECOVER_CMD, ®s->csr);
264 ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
266 /* Just try to reinit the device. */
267 ast_i2c_init_bus(dev);
273 static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
277 ret = ast_i2c_deblock(dev);
281 debug("i2c_xfer: %d messages\n", nmsgs);
282 for (; nmsgs > 0; nmsgs--, msg++) {
283 if (msg->flags & I2C_M_RD) {
284 debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
285 msg->addr, msg->len, msg->flags);
286 ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
287 msg->len, (nmsgs == 1));
289 debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
290 msg->addr, msg->len, msg->flags);
291 ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
292 msg->len, (nmsgs == 1));
295 debug("%s: error (%d)\n", __func__, ret);
303 static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
305 struct ast_i2c_priv *priv = dev_get_priv(dev);
306 struct ast_i2c_regs *regs = priv->regs;
307 ulong i2c_rate, divider;
309 debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
311 debug("No valid speed specified\n");
315 i2c_rate = clk_get_rate(&priv->clk);
316 divider = i2c_rate / speed;
319 if (speed > I2C_SPEED_FAST_RATE) {
320 debug("Enable High Speed\n");
321 setbits_le32(®s->fcr, I2CD_M_HIGH_SPEED_EN
322 | I2CD_M_SDA_DRIVE_1T_EN
323 | I2CD_SDA_DRIVE_1T_EN);
324 writel(HIGHSPEED_TTIMEOUT, ®s->cactcr2);
326 debug("Enabling Normal Speed\n");
327 writel(I2CD_NO_TIMEOUT_CTRL, ®s->cactcr2);
330 writel(get_clk_reg_val(divider), ®s->cactcr1);
331 ast_i2c_clear_interrupts(dev);
336 static const struct dm_i2c_ops ast_i2c_ops = {
337 .xfer = ast_i2c_xfer,
338 .set_bus_speed = ast_i2c_set_speed,
339 .deblock = ast_i2c_deblock,
342 static const struct udevice_id ast_i2c_ids[] = {
343 { .compatible = "aspeed,ast2400-i2c-bus" },
344 { .compatible = "aspeed,ast2500-i2c-bus" },
348 U_BOOT_DRIVER(ast_i2c) = {
351 .of_match = ast_i2c_ids,
352 .probe = ast_i2c_probe,
353 .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
354 .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),