drivers/fpga/versalpl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2019, Xilinx, Inc,
   4  * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/sys_proto.h>
   9 #include <memalign.h>
  10 #include <versalpl.h>
  11
  12 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
  13 {
  14         ulong *new_buf;
  15
  16         if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  17                 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  18                 memcpy(new_buf, buf, len);
  19                 buf = new_buf;
  20         }
  21
  22         return (ulong)buf;
  23 }
  24
  25 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
  26                        bitstream_type bstype)
  27 {
  28         ulong bin_buf;
  29         int ret;
  30         u32 buf_lo, buf_hi;
  31         u32 ret_payload[5];
  32
  33         bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
  34
  35         debug("%s called!\n", __func__);
  36         flush_dcache_range(bin_buf, bin_buf + bsize);
  37
  38         buf_lo = lower_32_bits(bin_buf);
  39         buf_hi = upper_32_bits(bin_buf);
  40
  41         ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
  42                                 buf_hi, 0, ret_payload);
  43         if (ret)
  44                 puts("PL FPGA LOAD fail\n");
  45
  46         return ret;
  47 }
  48
  49 struct xilinx_fpga_op versal_op = {
  50         .load = versal_load,
  51 };