drivers/fpga/versalpl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2019, Xilinx, Inc,
   4  * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/sys_proto.h>
   9 #include <memalign.h>
  10 #include <versalpl.h>
  11 #include <zynqmp_firmware.h>
  12
  13 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
  14 {
  15         ulong *new_buf;
  16
  17         if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  18                 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  19                 memcpy(new_buf, buf, len);
  20                 buf = new_buf;
  21         }
  22
  23         return (ulong)buf;
  24 }
  25
  26 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
  27                        bitstream_type bstype)
  28 {
  29         ulong bin_buf;
  30         int ret;
  31         u32 buf_lo, buf_hi;
  32         u32 ret_payload[5];
  33
  34         bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
  35
  36         debug("%s called!\n", __func__);
  37         flush_dcache_range(bin_buf, bin_buf + bsize);
  38
  39         buf_lo = lower_32_bits(bin_buf);
  40         buf_hi = upper_32_bits(bin_buf);
  41
  42         ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
  43                                 buf_hi, 0, ret_payload);
  44         if (ret)
  45                 puts("PL FPGA LOAD fail\n");
  46
  47         return ret;
  48 }
  49
  50 struct xilinx_fpga_op versal_op = {
  51         .load = versal_load,
  52 };