1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Intel Corporation <www.intel.com>
9 #include <asm/arch/mailbox_s10.h>
11 #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
12 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
14 static const struct mbox_cfgstat_state {
16 const char *error_name;
17 } mbox_cfgstat_state[] = {
18 {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
19 {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
20 {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
21 {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
22 {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
23 {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
24 {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
25 {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
26 {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
27 {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
28 {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
29 {MBOX_RESP_ERROR, "Mailbox general error!"},
30 {-ETIMEDOUT, "I/O timeout error"},
31 {-1, "Unknown error!"}
34 #define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
36 static const char *mbox_cfgstat_to_str(int err)
40 for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
41 if (mbox_cfgstat_state[i].err_no == err)
42 return mbox_cfgstat_state[i].error_name;
45 return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
49 * Add the ongoing transaction's command ID into pending list and return
50 * the command ID for next transfer.
52 static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
56 for (i = 0; i < list_size; i++) {
57 if (xfer_pending_list[i])
59 xfer_pending_list[i] = id;
60 debug("ID(%d) added to transaction pending list\n", id);
62 * Increment command ID for next transaction.
63 * Valid command ID (4 bits) is from 1 to 15.
73 * Check whether response ID match the command ID in the transfer
74 * pending list. If a match is found in the transfer pending list,
75 * it clears the transfer pending list and return the matched
78 static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
83 for (i = 0; i < list_size; i++) {
84 if (id != xfer_pending_list[i])
86 xfer_pending_list[i] = 0;
94 * Polling the FPGA configuration status.
95 * Return 0 for success, non-zero for error.
97 static int reconfig_status_polling_resp(void)
100 unsigned long start = get_timer(0);
103 ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
105 return 0; /* configuration success */
107 if (ret != MBOX_CFGSTAT_STATE_CONFIG)
110 if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
111 break; /* time out */
114 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
120 static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
121 u32 *resp_buf, u32 buf_size, u32 client_id)
123 u32 buf[MBOX_RESP_BUFFER_SIZE];
129 if (*resp_count < buf_size) {
130 u32 rcv_len_max = buf_size - *resp_count;
132 if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
133 rcv_len_max = MBOX_RESP_BUFFER_SIZE;
134 resp_len = mbox_rcv_resp(buf, rcv_len_max);
136 for (i = 0; i < resp_len; i++) {
137 resp_buf[(*w_index)++] = buf[i];
138 *w_index %= buf_size;
143 /* No response in buffer */
144 if (*resp_count == 0)
147 mbox_hdr = resp_buf[*r_index];
149 hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
151 /* Insufficient header length to return a mailbox header */
152 if ((*resp_count - 1) < hdr_len)
155 *r_index += (hdr_len + 1);
156 *r_index %= buf_size;
157 *resp_count -= (hdr_len + 1);
159 /* Make sure response belongs to us */
160 if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
166 /* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
167 static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
168 u32 xfer_max, u32 buf_size_max)
170 u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
171 u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
181 debug("SDM xfer_max = %d\n", xfer_max);
182 debug("SDM buf_size_max = %x\n\n", buf_size_max);
184 memset(xfer_pending, 0, sizeof(xfer_pending));
186 while (rbf_size || xfer_count) {
187 if (!resp_err && rbf_size && xfer_count < xfer_max) {
188 args[0] = MBOX_ARG_DESC_COUNT(1);
189 args[1] = (u64)rbf_data;
190 if (rbf_size >= buf_size_max) {
191 args[2] = buf_size_max;
192 rbf_size -= buf_size_max;
193 rbf_data += buf_size_max;
195 args[2] = (u64)rbf_size;
199 resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
200 MBOX_CMD_INDIRECT, 3, args);
203 cmd_id = add_transfer(xfer_pending,
204 MBOX_RESP_BUFFER_SIZE,
209 u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
212 MBOX_RESP_BUFFER_SIZE,
213 MBOX_CLIENT_ID_UBOOT);
216 * If no valid response header found or
217 * non-zero length from RECONFIG_DATA
219 if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
222 /* Check for response's status */
224 resp_err = MBOX_RESP_ERR_GET(resp_hdr);
225 debug("Response error code: %08x\n", resp_err);
228 ret = get_and_clr_transfer(xfer_pending,
229 MBOX_RESP_BUFFER_SIZE,
230 MBOX_RESP_ID_GET(resp_hdr));
232 /* Claim and reuse the ID */
237 if (resp_err && !xfer_count)
246 * This is the interface used by FPGA driver.
247 * Return 0 for success, non-zero for error.
249 int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
255 debug("Sending MBOX_RECONFIG...\n");
256 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
257 NULL, 0, &resp_len, resp_buf);
259 puts("Failure in RECONFIG mailbox command!\n");
263 ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
265 printf("RECONFIG_DATA error: %08x, %s\n", ret,
266 mbox_cfgstat_to_str(ret));
270 /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
271 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
273 debug("Polling with MBOX_RECONFIG_STATUS...\n");
274 ret = reconfig_status_polling_resp();
276 printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
277 mbox_cfgstat_to_str(ret));
281 puts("FPGA reconfiguration OK!\n");