drivers/fpga/socfpga_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  */
   5 #include <image.h>
   6 #include <log.h>
   7 #include <asm/io.h>
   8 #include <asm/arch/fpga_manager.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/misc.h>
  13 #include <altera.h>
  14 #include <asm/arch/pinmux.h>
  15 #include <common.h>
  16 #include <dm/ofnode.h>
  17 #include <errno.h>
  18 #include <fs_loader.h>
  19 #include <wait_bit.h>
  20 #include <watchdog.h>
  21
  22 #define CFGWDTH_32      1
  23 #define MIN_BITSTREAM_SIZECHECK 230
  24 #define ENCRYPTION_OFFSET       69
  25 #define COMPRESSION_OFFSET      229
  26 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  27 #define FPGA_TIMEOUT_CNT        0x1000000
  28 #define DEFAULT_DDR_LOAD_ADDRESS        0x400
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static const struct socfpga_fpga_manager *fpga_manager_base =
  33                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  34
  35 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  36
  37 static uint32_t fpgamgr_get_msel(void)
  38 {
  39         u32 reg;
  40
  41         reg = readl(&fpga_manager_base->imgcfg_stat);
  42         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  43                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  44
  45         return reg;
  46 }
  47
  48 static void fpgamgr_set_cfgwdth(int width)
  49 {
  50         if (width)
  51                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  52                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  53         else
  54                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  55                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  56 }
  57
  58 int is_fpgamgr_user_mode(void)
  59 {
  60         return (readl(&fpga_manager_base->imgcfg_stat) &
  61                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  62 }
  63
  64 static int wait_for_user_mode(void)
  65 {
  66         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  67                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  68                 1, FPGA_TIMEOUT_MSEC, false);
  69 }
  70
  71 int is_fpgamgr_early_user_mode(void)
  72 {
  73         return (readl(&fpga_manager_base->imgcfg_stat) &
  74                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  75 }
  76
  77 int fpgamgr_wait_early_user_mode(void)
  78 {
  79         u32 sync_data = 0xffffffff;
  80         u32 i = 0;
  81         unsigned start = get_timer(0);
  82         unsigned long cd_ratio;
  83
  84         /* Getting existing CDRATIO */
  85         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  86                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  87                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  88
  89         /* Using CDRATIO_X1 for better compatibility */
  90         fpgamgr_set_cd_ratio(CDRATIO_x1);
  91
  92         while (!is_fpgamgr_early_user_mode()) {
  93                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  94                         return -ETIMEDOUT;
  95                 fpgamgr_program_write((const long unsigned int *)&sync_data,
  96                                 sizeof(sync_data));
  97                 udelay(FPGA_TIMEOUT_MSEC);
  98                 i++;
  99         }
 100
 101         debug("FPGA: Additional %i sync word needed\n", i);
 102
 103         /* restoring original CDRATIO */
 104         fpgamgr_set_cd_ratio(cd_ratio);
 105
 106         return 0;
 107 }
 108
 109 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 110 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 111 {
 112         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 113                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 114
 115         /*
 116          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 117          * de-asserted, timeout at 1000ms
 118          */
 119         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 120                                  true, FPGA_TIMEOUT_MSEC, false);
 121 }
 122
 123 static int wait_for_f2s_nstatus_pin(unsigned long value)
 124 {
 125         /* Poll until f2s to specific value, timeout at 1000ms */
 126         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 127                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 128                 value, FPGA_TIMEOUT_MSEC, false);
 129 }
 130
 131 /* set CD ratio */
 132 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 133 {
 134         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 135                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 136
 137         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 138                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 139                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 140 }
 141
 142 /* get the MSEL value, verify we are set for FPP configuration mode */
 143 static int fpgamgr_verify_msel(void)
 144 {
 145         u32 msel = fpgamgr_get_msel();
 146
 147         if (msel & ~BIT(0)) {
 148                 printf("Fail: read msel=%d\n", msel);
 149                 return -EPERM;
 150         }
 151
 152         return 0;
 153 }
 154
 155 /*
 156  * Write cdratio and cdwidth based on whether the bitstream is compressed
 157  * and/or encoded
 158  */
 159 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 160                                        size_t rbf_size)
 161 {
 162         unsigned int cd_ratio;
 163         bool encrypt, compress;
 164
 165         /*
 166          * According to the bitstream specification,
 167          * both encryption and compression status are
 168          * in location before offset 230 of the buffer.
 169          */
 170         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 171                 return -EINVAL;
 172
 173         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 174         encrypt = encrypt != 0;
 175
 176         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 177         compress = !compress;
 178
 179         debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
 180         debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
 181         debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
 182              compress);
 183
 184         /*
 185          * from the register map description of cdratio in imgcfg_ctrl_02:
 186          *  Normal Configuration    : 32bit Passive Parallel
 187          *  Partial Reconfiguration : 16bit Passive Parallel
 188          */
 189
 190         /*
 191          * cd ratio is dependent on cfg width and whether the bitstream
 192          * is encrypted and/or compressed.
 193          *
 194          * | width | encr. | compr. | cd ratio |
 195          * |  16   |   0   |   0    |     1    |
 196          * |  16   |   0   |   1    |     4    |
 197          * |  16   |   1   |   0    |     2    |
 198          * |  16   |   1   |   1    |     4    |
 199          * |  32   |   0   |   0    |     1    |
 200          * |  32   |   0   |   1    |     8    |
 201          * |  32   |   1   |   0    |     4    |
 202          * |  32   |   1   |   1    |     8    |
 203          */
 204         if (!compress && !encrypt) {
 205                 cd_ratio = CDRATIO_x1;
 206         } else {
 207                 if (compress)
 208                         cd_ratio = CDRATIO_x4;
 209                 else
 210                         cd_ratio = CDRATIO_x2;
 211
 212                 /* if 32 bit, double the cd ratio (so register
 213                    field setting is incremented) */
 214                 if (cfg_width == CFGWDTH_32)
 215                         cd_ratio += 1;
 216         }
 217
 218         fpgamgr_set_cfgwdth(cfg_width);
 219         fpgamgr_set_cd_ratio(cd_ratio);
 220
 221         return 0;
 222 }
 223
 224 static int fpgamgr_reset(void)
 225 {
 226         unsigned long reg;
 227
 228         /* S2F_NCONFIG = 0 */
 229         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 230                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 231
 232         /* Wait for f2s_nstatus == 0 */
 233         if (wait_for_f2s_nstatus_pin(0))
 234                 return -ETIME;
 235
 236         /* S2F_NCONFIG = 1 */
 237         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 238                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 239
 240         /* Wait for f2s_nstatus == 1 */
 241         if (wait_for_f2s_nstatus_pin(1))
 242                 return -ETIME;
 243
 244         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 245         reg = readl(&fpga_manager_base->imgcfg_stat);
 246         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 247                 return -EPERM;
 248
 249         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 250                 return -EPERM;
 251
 252         return 0;
 253 }
 254
 255 /* Start the FPGA programming by initialize the FPGA Manager */
 256 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 257 {
 258         int ret;
 259
 260         /* Step 1 */
 261         if (fpgamgr_verify_msel())
 262                 return -EPERM;
 263
 264         /* Step 2 */
 265         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 266                 return -EPERM;
 267
 268         /*
 269          * Step 3:
 270          * Make sure no other external devices are trying to interfere with
 271          * programming:
 272          */
 273         if (wait_for_nconfig_pin_and_nstatus_pin())
 274                 return -ETIME;
 275
 276         /*
 277          * Step 4:
 278          * Deassert the signal drives from HPS
 279          *
 280          * S2F_NCE = 1
 281          * S2F_PR_REQUEST = 0
 282          * EN_CFG_CTRL = 0
 283          * EN_CFG_DATA = 0
 284          * S2F_NCONFIG = 1
 285          * S2F_NSTATUS_OE = 0
 286          * S2F_CONDONE_OE = 0
 287          */
 288         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 289                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 290
 291         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 292                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 293
 294         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 295                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 296                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 297
 298         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 299                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 300
 301         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 302                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 303                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 304
 305         /*
 306          * Step 5:
 307          * Enable overrides
 308          * S2F_NENABLE_CONFIG = 0
 309          * S2F_NENABLE_NCONFIG = 0
 310          */
 311         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 312                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 313         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 314                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 315
 316         /*
 317          * Disable driving signals that HPS doesn't need to drive.
 318          * S2F_NENABLE_NSTATUS = 1
 319          * S2F_NENABLE_CONDONE = 1
 320          */
 321         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 322                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 323                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 324
 325         /*
 326          * Step 6:
 327          * Drive chip select S2F_NCE = 0
 328          */
 329          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 330                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 331
 332         /* Step 7 */
 333         if (wait_for_nconfig_pin_and_nstatus_pin())
 334                 return -ETIME;
 335
 336         /* Step 8 */
 337         ret = fpgamgr_reset();
 338
 339         if (ret)
 340                 return ret;
 341
 342         /*
 343          * Step 9:
 344          * EN_CFG_CTRL and EN_CFG_DATA = 1
 345          */
 346         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 347                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 348                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 349
 350         return 0;
 351 }
 352
 353 /* Ensure the FPGA entering config done */
 354 static int fpgamgr_program_poll_cd(void)
 355 {
 356         unsigned long reg, i;
 357
 358         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 359                 reg = readl(&fpga_manager_base->imgcfg_stat);
 360                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 361                         return 0;
 362
 363                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 364                         printf("nstatus == 0 while waiting for condone\n");
 365                         return -EPERM;
 366                 }
 367                 WATCHDOG_RESET();
 368         }
 369
 370         if (i == FPGA_TIMEOUT_CNT)
 371                 return -ETIME;
 372
 373         return 0;
 374 }
 375
 376 /* Ensure the FPGA entering user mode */
 377 static int fpgamgr_program_poll_usermode(void)
 378 {
 379         unsigned long reg;
 380         int ret = 0;
 381
 382         if (fpgamgr_dclkcnt_set(0xf))
 383                 return -ETIME;
 384
 385         ret = wait_for_user_mode();
 386         if (ret < 0) {
 387                 printf("%s: Failed to enter user mode with ", __func__);
 388                 printf("error code %d\n", ret);
 389                 return ret;
 390         }
 391
 392         /*
 393          * Step 14:
 394          * Stop DATA path and Dclk
 395          * EN_CFG_CTRL and EN_CFG_DATA = 0
 396          */
 397         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 398                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 399                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 400
 401         /*
 402          * Step 15:
 403          * Disable overrides
 404          * S2F_NENABLE_CONFIG = 1
 405          * S2F_NENABLE_NCONFIG = 1
 406          */
 407         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 408                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 409         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 410                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 411
 412         /* Disable chip select S2F_NCE = 1 */
 413         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 414                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 415
 416         /*
 417          * Step 16:
 418          * Final check
 419          */
 420         reg = readl(&fpga_manager_base->imgcfg_stat);
 421         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 422                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 423             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 424                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 425             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 426                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 427                 return -EPERM;
 428
 429         return 0;
 430 }
 431
 432 int fpgamgr_program_finish(void)
 433 {
 434         /* Ensure the FPGA entering config done */
 435         int status = fpgamgr_program_poll_cd();
 436
 437         if (status) {
 438                 printf("FPGA: Poll CD failed with error code %d\n", status);
 439                 return -EPERM;
 440         }
 441
 442         /* Ensure the FPGA entering user mode */
 443         status = fpgamgr_program_poll_usermode();
 444         if (status) {
 445                 printf("FPGA: Poll usermode failed with error code %d\n",
 446                         status);
 447                 return -EPERM;
 448         }
 449
 450         printf("Full Configuration Succeeded.\n");
 451
 452         return 0;
 453 }
 454
 455 ofnode get_fpga_mgr_ofnode(ofnode from)
 456 {
 457         return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
 458 }
 459
 460 const char *get_fpga_filename(void)
 461 {
 462         const char *fpga_filename = NULL;
 463
 464         ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
 465
 466         if (ofnode_valid(fpgamgr_node))
 467                 fpga_filename = ofnode_read_string(fpgamgr_node,
 468                                                 "altr,bitstream");
 469
 470         return fpga_filename;
 471 }
 472
 473 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 474 {
 475         /*
 476          * Magic ID starting at:
 477          * -> 1st dword[15:0] in periph.rbf
 478          * -> 2nd dword[15:0] in core.rbf
 479          * Note: dword == 32 bits
 480          */
 481         u32 word_reading_max = 2;
 482         u32 i;
 483
 484         for (i = 0; i < word_reading_max; i++) {
 485                 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 486                         rbf->security = unencrypted;
 487                 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 488                         rbf->security = encrypted;
 489                 } else if (*(buffer + i + 1) ==
 490                                 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 491                         rbf->security = unencrypted;
 492                 } else if (*(buffer + i + 1) ==
 493                                 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 494                         rbf->security = encrypted;
 495                 } else {
 496                         rbf->security = invalid;
 497                         continue;
 498                 }
 499
 500                 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
 501                 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 502                         rbf->section = periph_section;
 503                         break;
 504                 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
 505                         rbf->section = core_section;
 506                         break;
 507                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 508                         rbf->section = periph_section;
 509                         break;
 510                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
 511                         rbf->section = core_section;
 512                         break;
 513                 }
 514
 515                 rbf->section = unknown;
 516                 break;
 517
 518                 WATCHDOG_RESET();
 519         }
 520 }
 521
 522 #ifdef CONFIG_FS_LOADER
 523 static int first_loading_rbf_to_buffer(struct udevice *dev,
 524                                 struct fpga_loadfs_info *fpga_loadfs,
 525                                 u32 *buffer, size_t *buffer_bsize)
 526 {
 527         u32 *buffer_p = (u32 *)*buffer;
 528         u32 *loadable = buffer_p;
 529         size_t buffer_size = *buffer_bsize;
 530         size_t fit_size;
 531         int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
 532         const char *fpga_node_name = NULL;
 533         const char *uname = NULL;
 534
 535         /* Load image header into buffer */
 536         ret = request_firmware_into_buf(dev,
 537                                         fpga_loadfs->fpga_fsinfo->filename,
 538                                         buffer_p, sizeof(struct image_header),
 539                                         0);
 540         if (ret < 0) {
 541                 debug("FPGA: Failed to read image header from flash.\n");
 542                 return -ENOENT;
 543         }
 544
 545         if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
 546                 debug("FPGA: No FDT magic was found.\n");
 547                 return -EBADF;
 548         }
 549
 550         fit_size = fdt_totalsize(buffer_p);
 551
 552         if (fit_size > buffer_size) {
 553                 debug("FPGA: FIT image is larger than available buffer.\n");
 554                 debug("Please use FIT external data or increasing buffer.\n");
 555                 return -ENOMEM;
 556         }
 557
 558         /* Load entire FIT into buffer */
 559         ret = request_firmware_into_buf(dev,
 560                                         fpga_loadfs->fpga_fsinfo->filename,
 561                                         buffer_p, fit_size, 0);
 562         if (ret < 0)
 563                 return ret;
 564
 565         ret = fit_check_format(buffer_p);
 566         if (!ret) {
 567                 debug("FPGA: No valid FIT image was found.\n");
 568                 return -EBADF;
 569         }
 570
 571         confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
 572         images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
 573         if (confs_noffset < 0 || images_noffset < 0) {
 574                 debug("FPGA: No Configurations or images nodes were found.\n");
 575                 return -ENOENT;
 576         }
 577
 578         /* Get default configuration unit name from default property */
 579         confs_noffset = fit_conf_get_node(buffer_p, NULL);
 580         if (confs_noffset < 0) {
 581                 debug("FPGA: No default configuration was found in config.\n");
 582                 return -ENOENT;
 583         }
 584
 585         count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
 586                                             FIT_FPGA_PROP);
 587         if (count < 0) {
 588                 debug("FPGA: Invalid configuration format for FPGA node.\n");
 589                 return count;
 590         }
 591         debug("FPGA: FPGA node count: %d\n", count);
 592
 593         for (i = 0; i < count; i++) {
 594                 images_noffset = fit_conf_get_prop_node_index(buffer_p,
 595                                                              confs_noffset,
 596                                                              FIT_FPGA_PROP, i);
 597                 uname = fit_get_name(buffer_p, images_noffset, NULL);
 598                 if (uname) {
 599                         debug("FPGA: %s\n", uname);
 600
 601                         if (strstr(uname, "fpga-periph") &&
 602                                 (!is_fpgamgr_early_user_mode() ||
 603                                 is_fpgamgr_user_mode())) {
 604                                 fpga_node_name = uname;
 605                                 printf("FPGA: Start to program ");
 606                                 printf("peripheral/full bitstream ...\n");
 607                                 break;
 608                         } else if (strstr(uname, "fpga-core") &&
 609                                         (is_fpgamgr_early_user_mode() &&
 610                                         !is_fpgamgr_user_mode())) {
 611                                 fpga_node_name = uname;
 612                                 printf("FPGA: Start to program core ");
 613                                 printf("bitstream ...\n");
 614                                 break;
 615                         }
 616                 }
 617                 WATCHDOG_RESET();
 618         }
 619
 620         if (!fpga_node_name) {
 621                 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
 622                 return 1;
 623         }
 624
 625         images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
 626         if (images_noffset < 0) {
 627                 debug("FPGA: No node '%s' was found in FIT.\n",
 628                      fpga_node_name);
 629                 return -ENOENT;
 630         }
 631
 632         if (!fit_image_get_data_position(buffer_p, images_noffset,
 633                                         &rbf_offset)) {
 634                 debug("FPGA: Data position was found.\n");
 635         } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
 636                   &rbf_offset)) {
 637                 /*
 638                  * For FIT with external data, figure out where
 639                  * the external images start. This is the base
 640                  * for the data-offset properties in each image.
 641                  */
 642                 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
 643                 debug("FPGA: Data offset was found.\n");
 644         } else {
 645                 debug("FPGA: No data position/offset was found.\n");
 646                 return -ENOENT;
 647         }
 648
 649         ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
 650         if (ret < 0) {
 651                 debug("FPGA: No data size was found (err=%d).\n", ret);
 652                 return -ENOENT;
 653         }
 654
 655         if (gd->ram_size < rbf_size) {
 656                 debug("FPGA: Using default OCRAM buffer and size.\n");
 657         } else {
 658                 ret = fit_image_get_load(buffer_p, images_noffset,
 659                                         (ulong *)loadable);
 660                 if (ret < 0) {
 661                         buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
 662                         debug("FPGA: No loadable was found.\n");
 663                         debug("FPGA: Using default DDR load address: 0x%x .\n",
 664                              DEFAULT_DDR_LOAD_ADDRESS);
 665                 } else {
 666                         buffer_p = (u32 *)*loadable;
 667                         debug("FPGA: Found loadable address = 0x%x.\n",
 668                              *loadable);
 669                 }
 670
 671                 buffer_size = rbf_size;
 672         }
 673
 674         debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
 675               rbf_offset, rbf_size);
 676
 677         fpga_loadfs->remaining = rbf_size;
 678
 679         /*
 680          * Determine buffer size vs bitstream size, and calculating number of
 681          * chunk by chunk transfer is required due to smaller buffer size
 682          * compare to bitstream
 683          */
 684         if (rbf_size <= buffer_size) {
 685                 /* Loading whole bitstream into buffer */
 686                 buffer_size = rbf_size;
 687                 fpga_loadfs->remaining = 0;
 688         } else {
 689                 fpga_loadfs->remaining -= buffer_size;
 690         }
 691
 692         fpga_loadfs->offset = rbf_offset;
 693         /* Loading bitstream into buffer */
 694         ret = request_firmware_into_buf(dev,
 695                                         fpga_loadfs->fpga_fsinfo->filename,
 696                                         buffer_p, buffer_size,
 697                                         fpga_loadfs->offset);
 698         if (ret < 0) {
 699                 debug("FPGA: Failed to read bitstream from flash.\n");
 700                 return -ENOENT;
 701         }
 702
 703         /* Getting info about bitstream types */
 704         get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
 705
 706         /* Update next reading bitstream offset */
 707         fpga_loadfs->offset += buffer_size;
 708
 709         /* Update the final addr for bitstream */
 710         *buffer = (u32)buffer_p;
 711
 712         /* Update the size of bitstream to be programmed into FPGA */
 713         *buffer_bsize = buffer_size;
 714
 715         return 0;
 716 }
 717
 718 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
 719                                         struct fpga_loadfs_info *fpga_loadfs,
 720                                         u32 *buffer, size_t *buffer_bsize)
 721 {
 722         int ret = 0;
 723         u32 *buffer_p = (u32 *)*buffer;
 724
 725         /* Read the bitstream chunk by chunk. */
 726         if (fpga_loadfs->remaining > *buffer_bsize) {
 727                 fpga_loadfs->remaining -= *buffer_bsize;
 728         } else {
 729                 *buffer_bsize = fpga_loadfs->remaining;
 730                 fpga_loadfs->remaining = 0;
 731         }
 732
 733         ret = request_firmware_into_buf(dev,
 734                                         fpga_loadfs->fpga_fsinfo->filename,
 735                                         buffer_p, *buffer_bsize,
 736                                         fpga_loadfs->offset);
 737         if (ret < 0) {
 738                 debug("FPGA: Failed to read bitstream from flash.\n");
 739                 return -ENOENT;
 740         }
 741
 742         /* Update next reading bitstream offset */
 743         fpga_loadfs->offset += *buffer_bsize;
 744
 745         return 0;
 746 }
 747
 748 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 749                         u32 offset)
 750 {
 751         struct fpga_loadfs_info fpga_loadfs;
 752         struct udevice *dev;
 753         int status, ret, size;
 754         u32 buffer = (uintptr_t)buf;
 755         size_t buffer_sizebytes = bsize;
 756         size_t buffer_sizebytes_ori = bsize;
 757         size_t total_sizeof_image = 0;
 758         ofnode node;
 759         const fdt32_t *phandle_p;
 760         u32 phandle;
 761
 762         node = get_fpga_mgr_ofnode(ofnode_null());
 763
 764         if (ofnode_valid(node)) {
 765                 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
 766                 if (!phandle_p) {
 767                         node = ofnode_path("/chosen");
 768                         if (!ofnode_valid(node)) {
 769                                 debug("FPGA: /chosen node was not found.\n");
 770                                 return -ENOENT;
 771                         }
 772
 773                         phandle_p = ofnode_get_property(node, "firmware-loader",
 774                                                        &size);
 775                         if (!phandle_p) {
 776                                 debug("FPGA: firmware-loader property was not");
 777                                 debug(" found.\n");
 778                                 return -ENOENT;
 779                         }
 780                 }
 781         } else {
 782                 debug("FPGA: FPGA manager node was not found.\n");
 783                 return -ENOENT;
 784         }
 785
 786         phandle = fdt32_to_cpu(*phandle_p);
 787         ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
 788                                              phandle, &dev);
 789         if (ret)
 790                 return ret;
 791
 792         memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
 793
 794         fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
 795         fpga_loadfs.offset = offset;
 796
 797         printf("FPGA: Checking FPGA configuration setting ...\n");
 798
 799         /*
 800          * Note: Both buffer and buffer_sizebytes values can be altered by
 801          * function below.
 802          */
 803         ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
 804                                            &buffer_sizebytes);
 805         if (ret == 1) {
 806                 printf("FPGA: Skipping configuration ...\n");
 807                 return 0;
 808         } else if (ret) {
 809                 return ret;
 810         }
 811
 812         if (fpga_loadfs.rbfinfo.section == core_section &&
 813                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 814                 debug("FPGA : Must be in Early Release mode to program ");
 815                 debug("core bitstream.\n");
 816                 return -EPERM;
 817         }
 818
 819         /* Disable all signals from HPS peripheral controller to FPGA */
 820         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 821
 822         /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 823         socfpga_bridges_reset();
 824
 825         if (fpga_loadfs.rbfinfo.section == periph_section) {
 826                 /* Initialize the FPGA Manager */
 827                 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
 828                 if (status) {
 829                         debug("FPGA: Init with peripheral bitstream failed.\n");
 830                         return -EPERM;
 831                 }
 832         }
 833
 834         /* Transfer bitstream to FPGA Manager */
 835         fpgamgr_program_write((void *)buffer, buffer_sizebytes);
 836
 837         total_sizeof_image += buffer_sizebytes;
 838
 839         while (fpga_loadfs.remaining) {
 840                 ret = subsequent_loading_rbf_to_buffer(dev,
 841                                                         &fpga_loadfs,
 842                                                         &buffer,
 843                                                         &buffer_sizebytes_ori);
 844
 845                 if (ret)
 846                         return ret;
 847
 848                 /* Transfer data to FPGA Manager */
 849                 fpgamgr_program_write((void *)buffer,
 850                                         buffer_sizebytes_ori);
 851
 852                 total_sizeof_image += buffer_sizebytes_ori;
 853
 854                 WATCHDOG_RESET();
 855         }
 856
 857         if (fpga_loadfs.rbfinfo.section == periph_section) {
 858                 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
 859                         config_pins(gd->fdt_blob, "shared");
 860                         puts("FPGA: Early Release Succeeded.\n");
 861                 } else {
 862                         debug("FPGA: Failed to see Early Release.\n");
 863                         return -EIO;
 864                 }
 865
 866                 /* For monolithic bitstream */
 867                 if (is_fpgamgr_user_mode()) {
 868                         /* Ensure the FPGA entering config done */
 869                         status = fpgamgr_program_finish();
 870                         if (status)
 871                                 return status;
 872
 873                         config_pins(gd->fdt_blob, "fpga");
 874                         puts("FPGA: Enter user mode.\n");
 875                 }
 876         } else if (fpga_loadfs.rbfinfo.section == core_section) {
 877                 /* Ensure the FPGA entering config done */
 878                 status = fpgamgr_program_finish();
 879                 if (status)
 880                         return status;
 881
 882                 config_pins(gd->fdt_blob, "fpga");
 883                 puts("FPGA: Enter user mode.\n");
 884         } else {
 885                 debug("FPGA: Config Error: Unsupported bitstream type.\n");
 886                 return -ENOEXEC;
 887         }
 888
 889         return (int)total_sizeof_image;
 890 }
 891
 892 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
 893 {
 894         fpga_fs_info fpga_fsinfo;
 895
 896         fpga_fsinfo.filename = get_fpga_filename();
 897
 898         if (fpga_fsinfo.filename)
 899                 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
 900 }
 901 #endif
 902
 903 /* This function is used to load the core bitstream from the OCRAM. */
 904 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 905 {
 906         unsigned long status;
 907         struct rbf_info rbfinfo;
 908
 909         memset(&rbfinfo, 0, sizeof(rbfinfo));
 910
 911         /* Disable all signals from hps peripheral controller to fpga */
 912         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 913
 914         /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 915         socfpga_bridges_reset();
 916
 917         /* Getting info about bitstream types */
 918         get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
 919
 920         if (rbfinfo.section == periph_section) {
 921                 /* Initialize the FPGA Manager */
 922                 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 923                 if (status)
 924                         return status;
 925         }
 926
 927         if (rbfinfo.section == core_section &&
 928                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 929                 debug("FPGA : Must be in early release mode to program ");
 930                 debug("core bitstream.\n");
 931                 return -EPERM;
 932         }
 933
 934         /* Write the bitstream to FPGA Manager */
 935         fpgamgr_program_write(rbf_data, rbf_size);
 936
 937         status = fpgamgr_program_finish();
 938         if (status)
 939                 return status;
 940
 941         config_pins(gd->fdt_blob, "fpga");
 942         puts("FPGA: Enter user mode.\n");
 943
 944         return status;
 945 }