drivers/dma/ti/k3-udma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
   4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  */
   6 #define pr_fmt(fmt) "udma: " fmt
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/cache.h>
  12 #include <asm/io.h>
  13 #include <asm/bitops.h>
  14 #include <malloc.h>
  15 #include <linux/bitops.h>
  16 #include <linux/dma-mapping.h>
  17 #include <dm.h>
  18 #include <dm/device_compat.h>
  19 #include <dm/devres.h>
  20 #include <dm/read.h>
  21 #include <dm/of_access.h>
  22 #include <dma.h>
  23 #include <dma-uclass.h>
  24 #include <linux/delay.h>
  25 #include <dt-bindings/dma/k3-udma.h>
  26 #include <linux/bitmap.h>
  27 #include <linux/err.h>
  28 #include <linux/soc/ti/k3-navss-ringacc.h>
  29 #include <linux/soc/ti/cppi5.h>
  30 #include <linux/soc/ti/ti-udma.h>
  31 #include <linux/soc/ti/ti_sci_protocol.h>
  32
  33 #include "k3-udma-hwdef.h"
  34
  35 #if BITS_PER_LONG == 64
  36 #define RINGACC_RING_USE_PROXY  (0)
  37 #else
  38 #define RINGACC_RING_USE_PROXY  (1)
  39 #endif
  40
  41 #define K3_UDMA_MAX_RFLOWS 1024
  42
  43 struct udma_chan;
  44
  45 enum udma_mmr {
  46         MMR_GCFG = 0,
  47         MMR_RCHANRT,
  48         MMR_TCHANRT,
  49         MMR_LAST,
  50 };
  51
  52 static const char * const mmr_names[] = {
  53         "gcfg", "rchanrt", "tchanrt"
  54 };
  55
  56 struct udma_tchan {
  57         void __iomem *reg_rt;
  58
  59         int id;
  60         struct k3_nav_ring *t_ring; /* Transmit ring */
  61         struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
  62 };
  63
  64 struct udma_rchan {
  65         void __iomem *reg_rt;
  66
  67         int id;
  68         struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
  69         struct k3_nav_ring *r_ring; /* Receive ring*/
  70 };
  71
  72 struct udma_rflow {
  73         int id;
  74 };
  75
  76 enum udma_rm_range {
  77         RM_RANGE_TCHAN = 0,
  78         RM_RANGE_RCHAN,
  79         RM_RANGE_RFLOW,
  80         RM_RANGE_LAST,
  81 };
  82
  83 struct udma_tisci_rm {
  84         const struct ti_sci_handle *tisci;
  85         const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
  86         u32  tisci_dev_id;
  87
  88         /* tisci information for PSI-L thread pairing/unpairing */
  89         const struct ti_sci_rm_psil_ops *tisci_psil_ops;
  90         u32  tisci_navss_dev_id;
  91
  92         struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
  93 };
  94
  95 struct udma_dev {
  96         struct udevice *dev;
  97         void __iomem *mmrs[MMR_LAST];
  98
  99         struct udma_tisci_rm tisci_rm;
 100         struct k3_nav_ringacc *ringacc;
 101
 102         u32 features;
 103
 104         int tchan_cnt;
 105         int echan_cnt;
 106         int rchan_cnt;
 107         int rflow_cnt;
 108         unsigned long *tchan_map;
 109         unsigned long *rchan_map;
 110         unsigned long *rflow_map;
 111         unsigned long *rflow_map_reserved;
 112
 113         struct udma_tchan *tchans;
 114         struct udma_rchan *rchans;
 115         struct udma_rflow *rflows;
 116
 117         struct udma_chan *channels;
 118         u32 psil_base;
 119
 120         u32 ch_count;
 121 };
 122
 123 struct udma_chan {
 124         struct udma_dev *ud;
 125         char name[20];
 126
 127         struct udma_tchan *tchan;
 128         struct udma_rchan *rchan;
 129         struct udma_rflow *rflow;
 130
 131         struct ti_udma_drv_chan_cfg_data cfg_data;
 132
 133         u32 bcnt; /* number of bytes completed since the start of the channel */
 134
 135         bool pkt_mode; /* TR or packet */
 136         bool needs_epib; /* EPIB is needed for the communication or not */
 137         u32 psd_size; /* size of Protocol Specific Data */
 138         u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
 139         int slave_thread_id;
 140         u32 src_thread;
 141         u32 dst_thread;
 142         u32 static_tr_type;
 143
 144         u32 id;
 145         enum dma_direction dir;
 146
 147         struct cppi5_host_desc_t *desc_tx;
 148         u32 hdesc_size;
 149         bool in_use;
 150         void    *desc_rx;
 151         u32     num_rx_bufs;
 152         u32     desc_rx_cur;
 153
 154 };
 155
 156 #define UDMA_CH_1000(ch)                (ch * 0x1000)
 157 #define UDMA_CH_100(ch)                 (ch * 0x100)
 158 #define UDMA_CH_40(ch)                  (ch * 0x40)
 159
 160 #ifdef PKTBUFSRX
 161 #define UDMA_RX_DESC_NUM PKTBUFSRX
 162 #else
 163 #define UDMA_RX_DESC_NUM 4
 164 #endif
 165
 166 /* Generic register access functions */
 167 static inline u32 udma_read(void __iomem *base, int reg)
 168 {
 169         u32 v;
 170
 171         v = __raw_readl(base + reg);
 172         pr_debug("READL(32): v(%08X)<--reg(%p)\n", v, base + reg);
 173         return v;
 174 }
 175
 176 static inline void udma_write(void __iomem *base, int reg, u32 val)
 177 {
 178         pr_debug("WRITEL(32): v(%08X)-->reg(%p)\n", val, base + reg);
 179         __raw_writel(val, base + reg);
 180 }
 181
 182 static inline void udma_update_bits(void __iomem *base, int reg,
 183                                     u32 mask, u32 val)
 184 {
 185         u32 tmp, orig;
 186
 187         orig = udma_read(base, reg);
 188         tmp = orig & ~mask;
 189         tmp |= (val & mask);
 190
 191         if (tmp != orig)
 192                 udma_write(base, reg, tmp);
 193 }
 194
 195 /* TCHANRT */
 196 static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg)
 197 {
 198         if (!tchan)
 199                 return 0;
 200         return udma_read(tchan->reg_rt, reg);
 201 }
 202
 203 static inline void udma_tchanrt_write(struct udma_tchan *tchan,
 204                                       int reg, u32 val)
 205 {
 206         if (!tchan)
 207                 return;
 208         udma_write(tchan->reg_rt, reg, val);
 209 }
 210
 211 /* RCHANRT */
 212 static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg)
 213 {
 214         if (!rchan)
 215                 return 0;
 216         return udma_read(rchan->reg_rt, reg);
 217 }
 218
 219 static inline void udma_rchanrt_write(struct udma_rchan *rchan,
 220                                       int reg, u32 val)
 221 {
 222         if (!rchan)
 223                 return;
 224         udma_write(rchan->reg_rt, reg, val);
 225 }
 226
 227 static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
 228                                        u32 dst_thread)
 229 {
 230         struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
 231
 232         dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
 233
 234         return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci,
 235                                               tisci_rm->tisci_navss_dev_id,
 236                                               src_thread, dst_thread);
 237 }
 238
 239 static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
 240                                          u32 dst_thread)
 241 {
 242         struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
 243
 244         dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
 245
 246         return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci,
 247                                                 tisci_rm->tisci_navss_dev_id,
 248                                                 src_thread, dst_thread);
 249 }
 250
 251 static inline char *udma_get_dir_text(enum dma_direction dir)
 252 {
 253         switch (dir) {
 254         case DMA_DEV_TO_MEM:
 255                 return "DEV_TO_MEM";
 256         case DMA_MEM_TO_DEV:
 257                 return "MEM_TO_DEV";
 258         case DMA_MEM_TO_MEM:
 259                 return "MEM_TO_MEM";
 260         case DMA_DEV_TO_DEV:
 261                 return "DEV_TO_DEV";
 262         default:
 263                 break;
 264         }
 265
 266         return "invalid";
 267 }
 268
 269 static inline bool udma_is_chan_running(struct udma_chan *uc)
 270 {
 271         u32 trt_ctl = 0;
 272         u32 rrt_ctl = 0;
 273
 274         switch (uc->dir) {
 275         case DMA_DEV_TO_MEM:
 276                 rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 277                 pr_debug("%s: rrt_ctl: 0x%08x (peer: 0x%08x)\n",
 278                          __func__, rrt_ctl,
 279                          udma_rchanrt_read(uc->rchan,
 280                                            UDMA_RCHAN_RT_PEER_RT_EN_REG));
 281                 break;
 282         case DMA_MEM_TO_DEV:
 283                 trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 284                 pr_debug("%s: trt_ctl: 0x%08x (peer: 0x%08x)\n",
 285                          __func__, trt_ctl,
 286                          udma_tchanrt_read(uc->tchan,
 287                                            UDMA_TCHAN_RT_PEER_RT_EN_REG));
 288                 break;
 289         case DMA_MEM_TO_MEM:
 290                 trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 291                 rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 292                 break;
 293         default:
 294                 break;
 295         }
 296
 297         if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
 298                 return true;
 299
 300         return false;
 301 }
 302
 303 static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
 304 {
 305         struct k3_nav_ring *ring = NULL;
 306         int ret = -ENOENT;
 307
 308         switch (uc->dir) {
 309         case DMA_DEV_TO_MEM:
 310                 ring = uc->rchan->r_ring;
 311                 break;
 312         case DMA_MEM_TO_DEV:
 313                 ring = uc->tchan->tc_ring;
 314                 break;
 315         case DMA_MEM_TO_MEM:
 316                 ring = uc->tchan->tc_ring;
 317                 break;
 318         default:
 319                 break;
 320         }
 321
 322         if (ring && k3_nav_ringacc_ring_get_occ(ring))
 323                 ret = k3_nav_ringacc_ring_pop(ring, addr);
 324
 325         return ret;
 326 }
 327
 328 static void udma_reset_rings(struct udma_chan *uc)
 329 {
 330         struct k3_nav_ring *ring1 = NULL;
 331         struct k3_nav_ring *ring2 = NULL;
 332
 333         switch (uc->dir) {
 334         case DMA_DEV_TO_MEM:
 335                 ring1 = uc->rchan->fd_ring;
 336                 ring2 = uc->rchan->r_ring;
 337                 break;
 338         case DMA_MEM_TO_DEV:
 339                 ring1 = uc->tchan->t_ring;
 340                 ring2 = uc->tchan->tc_ring;
 341                 break;
 342         case DMA_MEM_TO_MEM:
 343                 ring1 = uc->tchan->t_ring;
 344                 ring2 = uc->tchan->tc_ring;
 345                 break;
 346         default:
 347                 break;
 348         }
 349
 350         if (ring1)
 351                 k3_nav_ringacc_ring_reset_dma(ring1, 0);
 352         if (ring2)
 353                 k3_nav_ringacc_ring_reset(ring2);
 354 }
 355
 356 static void udma_reset_counters(struct udma_chan *uc)
 357 {
 358         u32 val;
 359
 360         if (uc->tchan) {
 361                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
 362                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
 363
 364                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG);
 365                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG, val);
 366
 367                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
 368                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
 369
 370                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
 371                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
 372         }
 373
 374         if (uc->rchan) {
 375                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_BCNT_REG);
 376                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_BCNT_REG, val);
 377
 378                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG);
 379                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG, val);
 380
 381                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PCNT_REG);
 382                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PCNT_REG, val);
 383
 384                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG);
 385                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG, val);
 386         }
 387
 388         uc->bcnt = 0;
 389 }
 390
 391 static inline int udma_stop_hard(struct udma_chan *uc)
 392 {
 393         pr_debug("%s: ENTER (chan%d)\n", __func__, uc->id);
 394
 395         switch (uc->dir) {
 396         case DMA_DEV_TO_MEM:
 397                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
 398                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 399                 break;
 400         case DMA_MEM_TO_DEV:
 401                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 402                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG, 0);
 403                 break;
 404         case DMA_MEM_TO_MEM:
 405                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 406                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 407                 break;
 408         default:
 409                 return -EINVAL;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int udma_start(struct udma_chan *uc)
 416 {
 417         /* Channel is already running, no need to proceed further */
 418         if (udma_is_chan_running(uc))
 419                 goto out;
 420
 421         pr_debug("%s: chan:%d dir:%s (static_tr_type: %d)\n",
 422                  __func__, uc->id, udma_get_dir_text(uc->dir),
 423                  uc->static_tr_type);
 424
 425         /* Make sure that we clear the teardown bit, if it is set */
 426         udma_stop_hard(uc);
 427
 428         /* Reset all counters */
 429         udma_reset_counters(uc);
 430
 431         switch (uc->dir) {
 432         case DMA_DEV_TO_MEM:
 433                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
 434                                    UDMA_CHAN_RT_CTL_EN);
 435
 436                 /* Enable remote */
 437                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
 438                                    UDMA_PEER_RT_EN_ENABLE);
 439
 440                 pr_debug("%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
 441                          __func__,
 442                          udma_rchanrt_read(uc->rchan,
 443                                            UDMA_RCHAN_RT_CTL_REG),
 444                          udma_rchanrt_read(uc->rchan,
 445                                            UDMA_RCHAN_RT_PEER_RT_EN_REG));
 446                 break;
 447         case DMA_MEM_TO_DEV:
 448                 /* Enable remote */
 449                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
 450                                    UDMA_PEER_RT_EN_ENABLE);
 451
 452                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 453                                    UDMA_CHAN_RT_CTL_EN);
 454
 455                 pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
 456                          __func__,
 457                          udma_tchanrt_read(uc->tchan,
 458                                            UDMA_TCHAN_RT_CTL_REG),
 459                          udma_tchanrt_read(uc->tchan,
 460                                            UDMA_TCHAN_RT_PEER_RT_EN_REG));
 461                 break;
 462         case DMA_MEM_TO_MEM:
 463                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
 464                                    UDMA_CHAN_RT_CTL_EN);
 465                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 466                                    UDMA_CHAN_RT_CTL_EN);
 467
 468                 break;
 469         default:
 470                 return -EINVAL;
 471         }
 472
 473         pr_debug("%s: DONE chan:%d\n", __func__, uc->id);
 474 out:
 475         return 0;
 476 }
 477
 478 static inline void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
 479 {
 480         int i = 0;
 481         u32 val;
 482
 483         udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 484                            UDMA_CHAN_RT_CTL_EN |
 485                            UDMA_CHAN_RT_CTL_TDOWN);
 486
 487         val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 488
 489         while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
 490                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 491                 udelay(1);
 492                 if (i > 1000) {
 493                         printf(" %s TIMEOUT !\n", __func__);
 494                         break;
 495                 }
 496                 i++;
 497         }
 498
 499         val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
 500         if (val & UDMA_PEER_RT_EN_ENABLE)
 501                 printf("%s: peer not stopped TIMEOUT !\n", __func__);
 502 }
 503
 504 static inline void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
 505 {
 506         int i = 0;
 507         u32 val;
 508
 509         udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
 510                            UDMA_PEER_RT_EN_ENABLE |
 511                            UDMA_PEER_RT_EN_TEARDOWN);
 512
 513         val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 514
 515         while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
 516                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 517                 udelay(1);
 518                 if (i > 1000) {
 519                         printf("%s TIMEOUT !\n", __func__);
 520                         break;
 521                 }
 522                 i++;
 523         }
 524
 525         val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
 526         if (val & UDMA_PEER_RT_EN_ENABLE)
 527                 printf("%s: peer not stopped TIMEOUT !\n", __func__);
 528 }
 529
 530 static inline int udma_stop(struct udma_chan *uc)
 531 {
 532         pr_debug("%s: chan:%d dir:%s\n",
 533                  __func__, uc->id, udma_get_dir_text(uc->dir));
 534
 535         udma_reset_counters(uc);
 536         switch (uc->dir) {
 537         case DMA_DEV_TO_MEM:
 538                 udma_stop_dev2mem(uc, true);
 539                 break;
 540         case DMA_MEM_TO_DEV:
 541                 udma_stop_mem2dev(uc, true);
 542                 break;
 543         case DMA_MEM_TO_MEM:
 544                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 545                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 546                 break;
 547         default:
 548                 return -EINVAL;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr)
 555 {
 556         int i = 1;
 557
 558         while (udma_pop_from_ring(uc, paddr)) {
 559                 udelay(1);
 560                 if (!(i % 1000000))
 561                         printf(".");
 562                 i++;
 563         }
 564 }
 565
 566 static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)
 567 {
 568         DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
 569
 570         if (id >= 0) {
 571                 if (test_bit(id, ud->rflow_map)) {
 572                         dev_err(ud->dev, "rflow%d is in use\n", id);
 573                         return ERR_PTR(-ENOENT);
 574                 }
 575         } else {
 576                 bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
 577                           ud->rflow_cnt);
 578
 579                 id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
 580                 if (id >= ud->rflow_cnt)
 581                         return ERR_PTR(-ENOENT);
 582         }
 583
 584         __set_bit(id, ud->rflow_map);
 585         return &ud->rflows[id];
 586 }
 587
 588 #define UDMA_RESERVE_RESOURCE(res)                                      \
 589 static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud,     \
 590                                                int id)                  \
 591 {                                                                       \
 592         if (id >= 0) {                                                  \
 593                 if (test_bit(id, ud->res##_map)) {                      \
 594                         dev_err(ud->dev, "res##%d is in use\n", id);    \
 595                         return ERR_PTR(-ENOENT);                        \
 596                 }                                                       \
 597         } else {                                                        \
 598                 id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
 599                 if (id == ud->res##_cnt) {                              \
 600                         return ERR_PTR(-ENOENT);                        \
 601                 }                                                       \
 602         }                                                               \
 603                                                                         \
 604         __set_bit(id, ud->res##_map);                                   \
 605         return &ud->res##s[id];                                         \
 606 }
 607
 608 UDMA_RESERVE_RESOURCE(tchan);
 609 UDMA_RESERVE_RESOURCE(rchan);
 610
 611 static int udma_get_tchan(struct udma_chan *uc)
 612 {
 613         struct udma_dev *ud = uc->ud;
 614
 615         if (uc->tchan) {
 616                 dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
 617                         uc->id, uc->tchan->id);
 618                 return 0;
 619         }
 620
 621         uc->tchan = __udma_reserve_tchan(ud, -1);
 622         if (IS_ERR(uc->tchan))
 623                 return PTR_ERR(uc->tchan);
 624
 625         pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
 626
 627         return 0;
 628 }
 629
 630 static int udma_get_rchan(struct udma_chan *uc)
 631 {
 632         struct udma_dev *ud = uc->ud;
 633
 634         if (uc->rchan) {
 635                 dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
 636                         uc->id, uc->rchan->id);
 637                 return 0;
 638         }
 639
 640         uc->rchan = __udma_reserve_rchan(ud, -1);
 641         if (IS_ERR(uc->rchan))
 642                 return PTR_ERR(uc->rchan);
 643
 644         pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id);
 645
 646         return 0;
 647 }
 648
 649 static int udma_get_chan_pair(struct udma_chan *uc)
 650 {
 651         struct udma_dev *ud = uc->ud;
 652         int chan_id, end;
 653
 654         if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
 655                 dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
 656                          uc->id, uc->tchan->id);
 657                 return 0;
 658         }
 659
 660         if (uc->tchan) {
 661                 dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
 662                         uc->id, uc->tchan->id);
 663                 return -EBUSY;
 664         } else if (uc->rchan) {
 665                 dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
 666                         uc->id, uc->rchan->id);
 667                 return -EBUSY;
 668         }
 669
 670         /* Can be optimized, but let's have it like this for now */
 671         end = min(ud->tchan_cnt, ud->rchan_cnt);
 672         for (chan_id = 0; chan_id < end; chan_id++) {
 673                 if (!test_bit(chan_id, ud->tchan_map) &&
 674                     !test_bit(chan_id, ud->rchan_map))
 675                         break;
 676         }
 677
 678         if (chan_id == end)
 679                 return -ENOENT;
 680
 681         __set_bit(chan_id, ud->tchan_map);
 682         __set_bit(chan_id, ud->rchan_map);
 683         uc->tchan = &ud->tchans[chan_id];
 684         uc->rchan = &ud->rchans[chan_id];
 685
 686         pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id);
 687
 688         return 0;
 689 }
 690
 691 static int udma_get_rflow(struct udma_chan *uc, int flow_id)
 692 {
 693         struct udma_dev *ud = uc->ud;
 694
 695         if (uc->rflow) {
 696                 dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
 697                         uc->id, uc->rflow->id);
 698                 return 0;
 699         }
 700
 701         if (!uc->rchan)
 702                 dev_warn(ud->dev, "chan%d: does not have rchan??\n", uc->id);
 703
 704         uc->rflow = __udma_reserve_rflow(ud, flow_id);
 705         if (IS_ERR(uc->rflow))
 706                 return PTR_ERR(uc->rflow);
 707
 708         pr_debug("chan%d: got rflow%d\n", uc->id, uc->rflow->id);
 709         return 0;
 710 }
 711
 712 static void udma_put_rchan(struct udma_chan *uc)
 713 {
 714         struct udma_dev *ud = uc->ud;
 715
 716         if (uc->rchan) {
 717                 dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
 718                         uc->rchan->id);
 719                 __clear_bit(uc->rchan->id, ud->rchan_map);
 720                 uc->rchan = NULL;
 721         }
 722 }
 723
 724 static void udma_put_tchan(struct udma_chan *uc)
 725 {
 726         struct udma_dev *ud = uc->ud;
 727
 728         if (uc->tchan) {
 729                 dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
 730                         uc->tchan->id);
 731                 __clear_bit(uc->tchan->id, ud->tchan_map);
 732                 uc->tchan = NULL;
 733         }
 734 }
 735
 736 static void udma_put_rflow(struct udma_chan *uc)
 737 {
 738         struct udma_dev *ud = uc->ud;
 739
 740         if (uc->rflow) {
 741                 dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
 742                         uc->rflow->id);
 743                 __clear_bit(uc->rflow->id, ud->rflow_map);
 744                 uc->rflow = NULL;
 745         }
 746 }
 747
 748 static void udma_free_tx_resources(struct udma_chan *uc)
 749 {
 750         if (!uc->tchan)
 751                 return;
 752
 753         k3_nav_ringacc_ring_free(uc->tchan->t_ring);
 754         k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
 755         uc->tchan->t_ring = NULL;
 756         uc->tchan->tc_ring = NULL;
 757
 758         udma_put_tchan(uc);
 759 }
 760
 761 static int udma_alloc_tx_resources(struct udma_chan *uc)
 762 {
 763         struct k3_nav_ring_cfg ring_cfg;
 764         struct udma_dev *ud = uc->ud;
 765         int ret;
 766
 767         ret = udma_get_tchan(uc);
 768         if (ret)
 769                 return ret;
 770
 771         uc->tchan->t_ring = k3_nav_ringacc_request_ring(
 772                                 ud->ringacc, uc->tchan->id,
 773                                 RINGACC_RING_USE_PROXY);
 774         if (!uc->tchan->t_ring) {
 775                 ret = -EBUSY;
 776                 goto err_tx_ring;
 777         }
 778
 779         uc->tchan->tc_ring = k3_nav_ringacc_request_ring(
 780                                 ud->ringacc, -1, RINGACC_RING_USE_PROXY);
 781         if (!uc->tchan->tc_ring) {
 782                 ret = -EBUSY;
 783                 goto err_txc_ring;
 784         }
 785
 786         memset(&ring_cfg, 0, sizeof(ring_cfg));
 787         ring_cfg.size = 16;
 788         ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
 789         ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
 790
 791         ret = k3_nav_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
 792         ret |= k3_nav_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
 793
 794         if (ret)
 795                 goto err_ringcfg;
 796
 797         return 0;
 798
 799 err_ringcfg:
 800         k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
 801         uc->tchan->tc_ring = NULL;
 802 err_txc_ring:
 803         k3_nav_ringacc_ring_free(uc->tchan->t_ring);
 804         uc->tchan->t_ring = NULL;
 805 err_tx_ring:
 806         udma_put_tchan(uc);
 807
 808         return ret;
 809 }
 810
 811 static void udma_free_rx_resources(struct udma_chan *uc)
 812 {
 813         if (!uc->rchan)
 814                 return;
 815
 816         k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
 817         k3_nav_ringacc_ring_free(uc->rchan->r_ring);
 818         uc->rchan->fd_ring = NULL;
 819         uc->rchan->r_ring = NULL;
 820
 821         udma_put_rflow(uc);
 822         udma_put_rchan(uc);
 823 }
 824
 825 static int udma_alloc_rx_resources(struct udma_chan *uc)
 826 {
 827         struct k3_nav_ring_cfg ring_cfg;
 828         struct udma_dev *ud = uc->ud;
 829         int fd_ring_id;
 830         int ret;
 831
 832         ret = udma_get_rchan(uc);
 833         if (ret)
 834                 return ret;
 835
 836         /* For MEM_TO_MEM we don't need rflow or rings */
 837         if (uc->dir == DMA_MEM_TO_MEM)
 838                 return 0;
 839
 840         ret = udma_get_rflow(uc, uc->rchan->id);
 841         if (ret) {
 842                 ret = -EBUSY;
 843                 goto err_rflow;
 844         }
 845
 846         fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id;
 847
 848         uc->rchan->fd_ring = k3_nav_ringacc_request_ring(
 849                                 ud->ringacc, fd_ring_id,
 850                                 RINGACC_RING_USE_PROXY);
 851         if (!uc->rchan->fd_ring) {
 852                 ret = -EBUSY;
 853                 goto err_rx_ring;
 854         }
 855
 856         uc->rchan->r_ring = k3_nav_ringacc_request_ring(
 857                                 ud->ringacc, -1, RINGACC_RING_USE_PROXY);
 858         if (!uc->rchan->r_ring) {
 859                 ret = -EBUSY;
 860                 goto err_rxc_ring;
 861         }
 862
 863         memset(&ring_cfg, 0, sizeof(ring_cfg));
 864         ring_cfg.size = 16;
 865         ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
 866         ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
 867
 868         ret = k3_nav_ringacc_ring_cfg(uc->rchan->fd_ring, &ring_cfg);
 869         ret |= k3_nav_ringacc_ring_cfg(uc->rchan->r_ring, &ring_cfg);
 870
 871         if (ret)
 872                 goto err_ringcfg;
 873
 874         return 0;
 875
 876 err_ringcfg:
 877         k3_nav_ringacc_ring_free(uc->rchan->r_ring);
 878         uc->rchan->r_ring = NULL;
 879 err_rxc_ring:
 880         k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
 881         uc->rchan->fd_ring = NULL;
 882 err_rx_ring:
 883         udma_put_rflow(uc);
 884 err_rflow:
 885         udma_put_rchan(uc);
 886
 887         return ret;
 888 }
 889
 890 static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
 891 {
 892         struct udma_dev *ud = uc->ud;
 893         int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
 894         struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
 895         struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
 896         u32 mode;
 897         int ret;
 898
 899         if (uc->pkt_mode)
 900                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
 901         else
 902                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
 903
 904         req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
 905                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
 906                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID;
 907         req.nav_id = tisci_rm->tisci_dev_id;
 908         req.index = uc->tchan->id;
 909         req.tx_chan_type = mode;
 910         if (uc->dir == DMA_MEM_TO_MEM)
 911                 req.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
 912         else
 913                 req.tx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
 914                                                           uc->psd_size,
 915                                                           0) >> 2;
 916         req.txcq_qnum = tc_ring;
 917
 918         ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
 919         if (ret)
 920                 dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
 921
 922         return ret;
 923 }
 924
 925 static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
 926 {
 927         struct udma_dev *ud = uc->ud;
 928         int fd_ring = k3_nav_ringacc_get_ring_id(uc->rchan->fd_ring);
 929         int rx_ring = k3_nav_ringacc_get_ring_id(uc->rchan->r_ring);
 930         int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
 931         struct ti_sci_msg_rm_udmap_rx_ch_cfg req = { 0 };
 932         struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
 933         struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
 934         u32 mode;
 935         int ret;
 936
 937         if (uc->pkt_mode)
 938                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
 939         else
 940                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
 941
 942         req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
 943                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
 944                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
 945                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
 946                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
 947         req.nav_id = tisci_rm->tisci_dev_id;
 948         req.index = uc->rchan->id;
 949         req.rx_chan_type = mode;
 950         if (uc->dir == DMA_MEM_TO_MEM) {
 951                 req.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
 952                 req.rxcq_qnum = tc_ring;
 953         } else {
 954                 req.rx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
 955                                                           uc->psd_size,
 956                                                           0) >> 2;
 957                 req.rxcq_qnum = rx_ring;
 958         }
 959         if (uc->rflow->id != uc->rchan->id && uc->dir != DMA_MEM_TO_MEM) {
 960                 req.flowid_start = uc->rflow->id;
 961                 req.flowid_cnt = 1;
 962         }
 963
 964         ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
 965         if (ret) {
 966                 dev_err(ud->dev, "tisci rx %u cfg failed %d\n",
 967                         uc->rchan->id, ret);
 968                 return ret;
 969         }
 970         if (uc->dir == DMA_MEM_TO_MEM)
 971                 return ret;
 972
 973         flow_req.valid_params =
 974                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
 975                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
 976                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID |
 977                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID |
 978                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
 979                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID |
 980                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID |
 981                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID |
 982                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID |
 983                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
 984                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
 985                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
 986                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID |
 987                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID;
 988
 989         flow_req.nav_id = tisci_rm->tisci_dev_id;
 990         flow_req.flow_index = uc->rflow->id;
 991
 992         if (uc->needs_epib)
 993                 flow_req.rx_einfo_present = 1;
 994         else
 995                 flow_req.rx_einfo_present = 0;
 996
 997         if (uc->psd_size)
 998                 flow_req.rx_psinfo_present = 1;
 999         else
1000                 flow_req.rx_psinfo_present = 0;
1001
1002         flow_req.rx_error_handling = 0;
1003         flow_req.rx_desc_type = 0;
1004         flow_req.rx_dest_qnum = rx_ring;
1005         flow_req.rx_src_tag_hi_sel = 2;
1006         flow_req.rx_src_tag_lo_sel = 4;
1007         flow_req.rx_dest_tag_hi_sel = 5;
1008         flow_req.rx_dest_tag_lo_sel = 4;
1009         flow_req.rx_fdq0_sz0_qnum = fd_ring;
1010         flow_req.rx_fdq1_qnum = fd_ring;
1011         flow_req.rx_fdq2_qnum = fd_ring;
1012         flow_req.rx_fdq3_qnum = fd_ring;
1013         flow_req.rx_ps_location = 0;
1014
1015         ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci,
1016                                                      &flow_req);
1017         if (ret)
1018                 dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
1019                         uc->rchan->id, uc->rflow->id, ret);
1020
1021         return ret;
1022 }
1023
1024 static int udma_alloc_chan_resources(struct udma_chan *uc)
1025 {
1026         struct udma_dev *ud = uc->ud;
1027         int ret;
1028
1029         pr_debug("%s: chan:%d as %s\n",
1030                  __func__, uc->id, udma_get_dir_text(uc->dir));
1031
1032         switch (uc->dir) {
1033         case DMA_MEM_TO_MEM:
1034                 /* Non synchronized - mem to mem type of transfer */
1035                 ret = udma_get_chan_pair(uc);
1036                 if (ret)
1037                         return ret;
1038
1039                 ret = udma_alloc_tx_resources(uc);
1040                 if (ret)
1041                         goto err_free_res;
1042
1043                 ret = udma_alloc_rx_resources(uc);
1044                 if (ret)
1045                         goto err_free_res;
1046
1047                 uc->src_thread = ud->psil_base + uc->tchan->id;
1048                 uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
1049                 break;
1050         case DMA_MEM_TO_DEV:
1051                 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
1052                 ret = udma_alloc_tx_resources(uc);
1053                 if (ret)
1054                         goto err_free_res;
1055
1056                 uc->src_thread = ud->psil_base + uc->tchan->id;
1057                 uc->dst_thread = uc->slave_thread_id;
1058                 if (!(uc->dst_thread & 0x8000))
1059                         uc->dst_thread |= 0x8000;
1060
1061                 break;
1062         case DMA_DEV_TO_MEM:
1063                 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
1064                 ret = udma_alloc_rx_resources(uc);
1065                 if (ret)
1066                         goto err_free_res;
1067
1068                 uc->src_thread = uc->slave_thread_id;
1069                 uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
1070
1071                 break;
1072         default:
1073                 /* Can not happen */
1074                 pr_debug("%s: chan:%d invalid direction (%u)\n",
1075                          __func__, uc->id, uc->dir);
1076                 return -EINVAL;
1077         }
1078
1079         /* We have channel indexes and rings */
1080         if (uc->dir == DMA_MEM_TO_MEM) {
1081                 ret = udma_alloc_tchan_sci_req(uc);
1082                 if (ret)
1083                         goto err_free_res;
1084
1085                 ret = udma_alloc_rchan_sci_req(uc);
1086                 if (ret)
1087                         goto err_free_res;
1088         } else {
1089                 /* Slave transfer */
1090                 if (uc->dir == DMA_MEM_TO_DEV) {
1091                         ret = udma_alloc_tchan_sci_req(uc);
1092                         if (ret)
1093                                 goto err_free_res;
1094                 } else {
1095                         ret = udma_alloc_rchan_sci_req(uc);
1096                         if (ret)
1097                                 goto err_free_res;
1098                 }
1099         }
1100
1101         if (udma_is_chan_running(uc)) {
1102                 dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
1103                 udma_stop(uc);
1104                 if (udma_is_chan_running(uc)) {
1105                         dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
1106                         goto err_free_res;
1107                 }
1108         }
1109
1110         /* PSI-L pairing */
1111         ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread);
1112         if (ret) {
1113                 dev_err(ud->dev, "k3_nav_psil_request_link fail\n");
1114                 goto err_free_res;
1115         }
1116
1117         return 0;
1118
1119 err_free_res:
1120         udma_free_tx_resources(uc);
1121         udma_free_rx_resources(uc);
1122         uc->slave_thread_id = -1;
1123         return ret;
1124 }
1125
1126 static void udma_free_chan_resources(struct udma_chan *uc)
1127 {
1128         /* Some configuration to UDMA-P channel: disable, reset, whatever */
1129
1130         /* Release PSI-L pairing */
1131         udma_navss_psil_unpair(uc->ud, uc->src_thread, uc->dst_thread);
1132
1133         /* Reset the rings for a new start */
1134         udma_reset_rings(uc);
1135         udma_free_tx_resources(uc);
1136         udma_free_rx_resources(uc);
1137
1138         uc->slave_thread_id = -1;
1139         uc->dir = DMA_MEM_TO_MEM;
1140 }
1141
1142 static int udma_get_mmrs(struct udevice *dev)
1143 {
1144         struct udma_dev *ud = dev_get_priv(dev);
1145         int i;
1146
1147         for (i = 0; i < MMR_LAST; i++) {
1148                 ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
1149                                 mmr_names[i]);
1150                 if (!ud->mmrs[i])
1151                         return -EINVAL;
1152         }
1153
1154         return 0;
1155 }
1156
1157 static int udma_setup_resources(struct udma_dev *ud)
1158 {
1159         struct udevice *dev = ud->dev;
1160         int ch_count, i;
1161         u32 cap2, cap3;
1162         struct ti_sci_resource_desc *rm_desc;
1163         struct ti_sci_resource *rm_res;
1164         struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
1165         static const char * const range_names[] = { "ti,sci-rm-range-tchan",
1166                                                     "ti,sci-rm-range-rchan",
1167                                                     "ti,sci-rm-range-rflow" };
1168
1169         cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
1170         cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
1171
1172         ud->rflow_cnt = cap3 & 0x3fff;
1173         ud->tchan_cnt = cap2 & 0x1ff;
1174         ud->echan_cnt = (cap2 >> 9) & 0x1ff;
1175         ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
1176         ch_count  = ud->tchan_cnt + ud->rchan_cnt;
1177
1178         ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
1179                                            sizeof(unsigned long), GFP_KERNEL);
1180         ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
1181                                   GFP_KERNEL);
1182         ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
1183                                            sizeof(unsigned long), GFP_KERNEL);
1184         ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
1185                                   GFP_KERNEL);
1186         ud->rflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt),
1187                                            sizeof(unsigned long), GFP_KERNEL);
1188         ud->rflow_map_reserved = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
1189                                               sizeof(unsigned long),
1190                                               GFP_KERNEL);
1191         ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
1192                                   GFP_KERNEL);
1193
1194         if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map ||
1195             !ud->rflow_map_reserved || !ud->tchans || !ud->rchans ||
1196             !ud->rflows)
1197                 return -ENOMEM;
1198
1199         /*
1200          * RX flows with the same Ids as RX channels are reserved to be used
1201          * as default flows if remote HW can't generate flow_ids. Those
1202          * RX flows can be requested only explicitly by id.
1203          */
1204         bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
1205
1206         /* Get resource ranges from tisci */
1207         for (i = 0; i < RM_RANGE_LAST; i++)
1208                 tisci_rm->rm_ranges[i] =
1209                         devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
1210                                                     tisci_rm->tisci_dev_id,
1211                                                     (char *)range_names[i]);
1212
1213         /* tchan ranges */
1214         rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
1215         if (IS_ERR(rm_res)) {
1216                 bitmap_zero(ud->tchan_map, ud->tchan_cnt);
1217         } else {
1218                 bitmap_fill(ud->tchan_map, ud->tchan_cnt);
1219                 for (i = 0; i < rm_res->sets; i++) {
1220                         rm_desc = &rm_res->desc[i];
1221                         bitmap_clear(ud->tchan_map, rm_desc->start,
1222                                      rm_desc->num);
1223                 }
1224         }
1225
1226         /* rchan and matching default flow ranges */
1227         rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
1228         if (IS_ERR(rm_res)) {
1229                 bitmap_zero(ud->rchan_map, ud->rchan_cnt);
1230                 bitmap_zero(ud->rflow_map, ud->rchan_cnt);
1231         } else {
1232                 bitmap_fill(ud->rchan_map, ud->rchan_cnt);
1233                 bitmap_fill(ud->rflow_map, ud->rchan_cnt);
1234                 for (i = 0; i < rm_res->sets; i++) {
1235                         rm_desc = &rm_res->desc[i];
1236                         bitmap_clear(ud->rchan_map, rm_desc->start,
1237                                      rm_desc->num);
1238                         bitmap_clear(ud->rflow_map, rm_desc->start,
1239                                      rm_desc->num);
1240                 }
1241         }
1242
1243         /* GP rflow ranges */
1244         rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
1245         if (IS_ERR(rm_res)) {
1246                 bitmap_clear(ud->rflow_map, ud->rchan_cnt,
1247                              ud->rflow_cnt - ud->rchan_cnt);
1248         } else {
1249                 bitmap_set(ud->rflow_map, ud->rchan_cnt,
1250                            ud->rflow_cnt - ud->rchan_cnt);
1251                 for (i = 0; i < rm_res->sets; i++) {
1252                         rm_desc = &rm_res->desc[i];
1253                         bitmap_clear(ud->rflow_map, rm_desc->start,
1254                                      rm_desc->num);
1255                 }
1256         }
1257
1258         ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
1259         ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
1260         if (!ch_count)
1261                 return -ENODEV;
1262
1263         ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
1264                                     GFP_KERNEL);
1265         if (!ud->channels)
1266                 return -ENOMEM;
1267
1268         dev_info(dev,
1269                  "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n",
1270                  ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
1271                  ud->rflow_cnt);
1272
1273         return ch_count;
1274 }
1275 static int udma_probe(struct udevice *dev)
1276 {
1277         struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
1278         struct udma_dev *ud = dev_get_priv(dev);
1279         int i, ret;
1280         struct udevice *tmp;
1281         struct udevice *tisci_dev = NULL;
1282         struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
1283         ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
1284
1285
1286         ret = udma_get_mmrs(dev);
1287         if (ret)
1288                 return ret;
1289
1290         ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
1291                                            "ti,ringacc", &tmp);
1292         ud->ringacc = dev_get_priv(tmp);
1293         if (IS_ERR(ud->ringacc))
1294                 return PTR_ERR(ud->ringacc);
1295
1296         ud->psil_base = dev_read_u32_default(dev, "ti,psil-base", 0);
1297         if (!ud->psil_base) {
1298                 dev_info(dev,
1299                          "Missing ti,psil-base property, using %d.\n", ret);
1300                 return -EINVAL;
1301         }
1302
1303         ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
1304                                            "ti,sci", &tisci_dev);
1305         if (ret) {
1306                 debug("Failed to get TISCI phandle (%d)\n", ret);
1307                 tisci_rm->tisci = NULL;
1308                 return -EINVAL;
1309         }
1310         tisci_rm->tisci = (struct ti_sci_handle *)
1311                           (ti_sci_get_handle_from_sysfw(tisci_dev));
1312
1313         tisci_rm->tisci_dev_id = -1;
1314         ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
1315         if (ret) {
1316                 dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
1317                 return ret;
1318         }
1319
1320         tisci_rm->tisci_navss_dev_id = -1;
1321         ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
1322                               &tisci_rm->tisci_navss_dev_id);
1323         if (ret) {
1324                 dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
1325                 return ret;
1326         }
1327
1328         tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
1329         tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
1330
1331         ud->dev = dev;
1332         ud->ch_count = udma_setup_resources(ud);
1333         if (ud->ch_count <= 0)
1334                 return ud->ch_count;
1335
1336         dev_info(dev,
1337                  "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
1338                  ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
1339                  tisci_rm->tisci_dev_id);
1340         dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
1341
1342         for (i = 0; i < ud->tchan_cnt; i++) {
1343                 struct udma_tchan *tchan = &ud->tchans[i];
1344
1345                 tchan->id = i;
1346                 tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
1347         }
1348
1349         for (i = 0; i < ud->rchan_cnt; i++) {
1350                 struct udma_rchan *rchan = &ud->rchans[i];
1351
1352                 rchan->id = i;
1353                 rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
1354         }
1355
1356         for (i = 0; i < ud->rflow_cnt; i++) {
1357                 struct udma_rflow *rflow = &ud->rflows[i];
1358
1359                 rflow->id = i;
1360         }
1361
1362         for (i = 0; i < ud->ch_count; i++) {
1363                 struct udma_chan *uc = &ud->channels[i];
1364
1365                 uc->ud = ud;
1366                 uc->id = i;
1367                 uc->slave_thread_id = -1;
1368                 uc->tchan = NULL;
1369                 uc->rchan = NULL;
1370                 uc->dir = DMA_MEM_TO_MEM;
1371                 sprintf(uc->name, "UDMA chan%d\n", i);
1372                 if (!i)
1373                         uc->in_use = true;
1374         }
1375
1376         pr_debug("UDMA(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1377                  udma_read(ud->mmrs[MMR_GCFG], 0),
1378                  udma_read(ud->mmrs[MMR_GCFG], 0x20),
1379                  udma_read(ud->mmrs[MMR_GCFG], 0x24),
1380                  udma_read(ud->mmrs[MMR_GCFG], 0x28),
1381                  udma_read(ud->mmrs[MMR_GCFG], 0x2c));
1382
1383         uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
1384
1385         return ret;
1386 }
1387
1388 static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem)
1389 {
1390         u64 addr = 0;
1391
1392         memcpy(&addr, &elem, sizeof(elem));
1393         return k3_nav_ringacc_ring_push(ring, &addr);
1394 }
1395
1396 static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
1397                                  dma_addr_t src, size_t len)
1398 {
1399         u32 tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
1400         struct cppi5_tr_type15_t *tr_req;
1401         int num_tr;
1402         size_t tr_size = sizeof(struct cppi5_tr_type15_t);
1403         u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
1404         unsigned long dummy;
1405         void *tr_desc;
1406         size_t desc_size;
1407
1408         if (len < SZ_64K) {
1409                 num_tr = 1;
1410                 tr0_cnt0 = len;
1411                 tr0_cnt1 = 1;
1412         } else {
1413                 unsigned long align_to = __ffs(src | dest);
1414
1415                 if (align_to > 3)
1416                         align_to = 3;
1417                 /*
1418                  * Keep simple: tr0: SZ_64K-alignment blocks,
1419                  *              tr1: the remaining
1420                  */
1421                 num_tr = 2;
1422                 tr0_cnt0 = (SZ_64K - BIT(align_to));
1423                 if (len / tr0_cnt0 >= SZ_64K) {
1424                         dev_err(uc->ud->dev, "size %zu is not supported\n",
1425                                 len);
1426                         return NULL;
1427                 }
1428
1429                 tr0_cnt1 = len / tr0_cnt0;
1430                 tr1_cnt0 = len % tr0_cnt0;
1431         }
1432
1433         desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
1434         tr_desc = dma_alloc_coherent(desc_size, &dummy);
1435         if (!tr_desc)
1436                 return NULL;
1437         memset(tr_desc, 0, desc_size);
1438
1439         cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
1440         cppi5_desc_set_pktids(tr_desc, uc->id, 0x3fff);
1441         cppi5_desc_set_retpolicy(tr_desc, 0, tc_ring_id);
1442
1443         tr_req = tr_desc + tr_size;
1444
1445         cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
1446                       CPPI5_TR_EVENT_SIZE_COMPLETION, 1);
1447         cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
1448
1449         tr_req[0].addr = src;
1450         tr_req[0].icnt0 = tr0_cnt0;
1451         tr_req[0].icnt1 = tr0_cnt1;
1452         tr_req[0].icnt2 = 1;
1453         tr_req[0].icnt3 = 1;
1454         tr_req[0].dim1 = tr0_cnt0;
1455
1456         tr_req[0].daddr = dest;
1457         tr_req[0].dicnt0 = tr0_cnt0;
1458         tr_req[0].dicnt1 = tr0_cnt1;
1459         tr_req[0].dicnt2 = 1;
1460         tr_req[0].dicnt3 = 1;
1461         tr_req[0].ddim1 = tr0_cnt0;
1462
1463         if (num_tr == 2) {
1464                 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
1465                               CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
1466                 cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
1467
1468                 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
1469                 tr_req[1].icnt0 = tr1_cnt0;
1470                 tr_req[1].icnt1 = 1;
1471                 tr_req[1].icnt2 = 1;
1472                 tr_req[1].icnt3 = 1;
1473
1474                 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
1475                 tr_req[1].dicnt0 = tr1_cnt0;
1476                 tr_req[1].dicnt1 = 1;
1477                 tr_req[1].dicnt2 = 1;
1478                 tr_req[1].dicnt3 = 1;
1479         }
1480
1481         cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
1482
1483         flush_dcache_range((unsigned long)tr_desc,
1484                            ALIGN((unsigned long)tr_desc + desc_size,
1485                                  ARCH_DMA_MINALIGN));
1486
1487         udma_push_to_ring(uc->tchan->t_ring, tr_desc);
1488
1489         return 0;
1490 }
1491
1492 static int udma_transfer(struct udevice *dev, int direction,
1493                          void *dst, void *src, size_t len)
1494 {
1495         struct udma_dev *ud = dev_get_priv(dev);
1496         /* Channel0 is reserved for memcpy */
1497         struct udma_chan *uc = &ud->channels[0];
1498         dma_addr_t paddr = 0;
1499         int ret;
1500
1501         ret = udma_alloc_chan_resources(uc);
1502         if (ret)
1503                 return ret;
1504
1505         udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len);
1506         udma_start(uc);
1507         udma_poll_completion(uc, &paddr);
1508         udma_stop(uc);
1509
1510         udma_free_chan_resources(uc);
1511         return 0;
1512 }
1513
1514 static int udma_request(struct dma *dma)
1515 {
1516         struct udma_dev *ud = dev_get_priv(dma->dev);
1517         struct udma_chan *uc;
1518         unsigned long dummy;
1519         int ret;
1520
1521         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1522                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1523                 return -EINVAL;
1524         }
1525
1526         uc = &ud->channels[dma->id];
1527         ret = udma_alloc_chan_resources(uc);
1528         if (ret) {
1529                 dev_err(dma->dev, "alloc dma res failed %d\n", ret);
1530                 return -EINVAL;
1531         }
1532
1533         uc->hdesc_size = cppi5_hdesc_calc_size(uc->needs_epib,
1534                                                uc->psd_size, 0);
1535         uc->hdesc_size = ALIGN(uc->hdesc_size, ARCH_DMA_MINALIGN);
1536
1537         if (uc->dir == DMA_MEM_TO_DEV) {
1538                 uc->desc_tx = dma_alloc_coherent(uc->hdesc_size, &dummy);
1539                 memset(uc->desc_tx, 0, uc->hdesc_size);
1540         } else {
1541                 uc->desc_rx = dma_alloc_coherent(
1542                                 uc->hdesc_size * UDMA_RX_DESC_NUM, &dummy);
1543                 memset(uc->desc_rx, 0, uc->hdesc_size * UDMA_RX_DESC_NUM);
1544         }
1545
1546         uc->in_use = true;
1547         uc->desc_rx_cur = 0;
1548         uc->num_rx_bufs = 0;
1549
1550         if (uc->dir == DMA_DEV_TO_MEM) {
1551                 uc->cfg_data.flow_id_base = uc->rflow->id;
1552                 uc->cfg_data.flow_id_cnt = 1;
1553         }
1554
1555         return 0;
1556 }
1557
1558 static int udma_rfree(struct dma *dma)
1559 {
1560         struct udma_dev *ud = dev_get_priv(dma->dev);
1561         struct udma_chan *uc;
1562
1563         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1564                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1565                 return -EINVAL;
1566         }
1567         uc = &ud->channels[dma->id];
1568
1569         if (udma_is_chan_running(uc))
1570                 udma_stop(uc);
1571         udma_free_chan_resources(uc);
1572
1573         uc->in_use = false;
1574
1575         return 0;
1576 }
1577
1578 static int udma_enable(struct dma *dma)
1579 {
1580         struct udma_dev *ud = dev_get_priv(dma->dev);
1581         struct udma_chan *uc;
1582         int ret;
1583
1584         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1585                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1586                 return -EINVAL;
1587         }
1588         uc = &ud->channels[dma->id];
1589
1590         ret = udma_start(uc);
1591
1592         return ret;
1593 }
1594
1595 static int udma_disable(struct dma *dma)
1596 {
1597         struct udma_dev *ud = dev_get_priv(dma->dev);
1598         struct udma_chan *uc;
1599         int ret = 0;
1600
1601         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1602                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1603                 return -EINVAL;
1604         }
1605         uc = &ud->channels[dma->id];
1606
1607         if (udma_is_chan_running(uc))
1608                 ret = udma_stop(uc);
1609         else
1610                 dev_err(dma->dev, "%s not running\n", __func__);
1611
1612         return ret;
1613 }
1614
1615 static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
1616 {
1617         struct udma_dev *ud = dev_get_priv(dma->dev);
1618         struct cppi5_host_desc_t *desc_tx;
1619         dma_addr_t dma_src = (dma_addr_t)src;
1620         struct ti_udma_drv_packet_data packet_data = { 0 };
1621         dma_addr_t paddr;
1622         struct udma_chan *uc;
1623         u32 tc_ring_id;
1624         int ret;
1625
1626         if (metadata)
1627                 packet_data = *((struct ti_udma_drv_packet_data *)metadata);
1628
1629         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1630                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1631                 return -EINVAL;
1632         }
1633         uc = &ud->channels[dma->id];
1634
1635         if (uc->dir != DMA_MEM_TO_DEV)
1636                 return -EINVAL;
1637
1638         tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
1639
1640         desc_tx = uc->desc_tx;
1641
1642         cppi5_hdesc_reset_hbdesc(desc_tx);
1643
1644         cppi5_hdesc_init(desc_tx,
1645                          uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
1646                          uc->psd_size);
1647         cppi5_hdesc_set_pktlen(desc_tx, len);
1648         cppi5_hdesc_attach_buf(desc_tx, dma_src, len, dma_src, len);
1649         cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
1650         cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, tc_ring_id);
1651         /* pass below information from caller */
1652         cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
1653         cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
1654
1655         flush_dcache_range((unsigned long)dma_src,
1656                            ALIGN((unsigned long)dma_src + len,
1657                                  ARCH_DMA_MINALIGN));
1658         flush_dcache_range((unsigned long)desc_tx,
1659                            ALIGN((unsigned long)desc_tx + uc->hdesc_size,
1660                                  ARCH_DMA_MINALIGN));
1661
1662         ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx);
1663         if (ret) {
1664                 dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
1665                         dma->id, ret);
1666                 return ret;
1667         }
1668
1669         udma_poll_completion(uc, &paddr);
1670
1671         return 0;
1672 }
1673
1674 static int udma_receive(struct dma *dma, void **dst, void *metadata)
1675 {
1676         struct udma_dev *ud = dev_get_priv(dma->dev);
1677         struct cppi5_host_desc_t *desc_rx;
1678         dma_addr_t buf_dma;
1679         struct udma_chan *uc;
1680         u32 buf_dma_len, pkt_len;
1681         u32 port_id = 0;
1682         int ret;
1683
1684         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1685                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1686                 return -EINVAL;
1687         }
1688         uc = &ud->channels[dma->id];
1689
1690         if (uc->dir != DMA_DEV_TO_MEM)
1691                 return -EINVAL;
1692         if (!uc->num_rx_bufs)
1693                 return -EINVAL;
1694
1695         ret = k3_nav_ringacc_ring_pop(uc->rchan->r_ring, &desc_rx);
1696         if (ret && ret != -ENODATA) {
1697                 dev_err(dma->dev, "rx dma fail ch_id:%lu %d\n", dma->id, ret);
1698                 return ret;
1699         } else if (ret == -ENODATA) {
1700                 return 0;
1701         }
1702
1703         /* invalidate cache data */
1704         invalidate_dcache_range((ulong)desc_rx,
1705                                 (ulong)(desc_rx + uc->hdesc_size));
1706
1707         cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
1708         pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
1709
1710         /* invalidate cache data */
1711         invalidate_dcache_range((ulong)buf_dma,
1712                                 (ulong)(buf_dma + buf_dma_len));
1713
1714         cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
1715
1716         *dst = (void *)buf_dma;
1717         uc->num_rx_bufs--;
1718
1719         return pkt_len;
1720 }
1721
1722 static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
1723 {
1724         struct udma_dev *ud = dev_get_priv(dma->dev);
1725         struct udma_chan *uc = &ud->channels[0];
1726         ofnode chconf_node, slave_node;
1727         char prop[50];
1728         u32 val;
1729
1730         for (val = 0; val < ud->ch_count; val++) {
1731                 uc = &ud->channels[val];
1732                 if (!uc->in_use)
1733                         break;
1734         }
1735
1736         if (val == ud->ch_count)
1737                 return -EBUSY;
1738
1739         uc->dir = DMA_DEV_TO_MEM;
1740         if (args->args[2] == UDMA_DIR_TX)
1741                 uc->dir = DMA_MEM_TO_DEV;
1742
1743         slave_node = ofnode_get_by_phandle(args->args[0]);
1744         if (!ofnode_valid(slave_node)) {
1745                 dev_err(ud->dev, "slave node is missing\n");
1746                 return -EINVAL;
1747         }
1748
1749         snprintf(prop, sizeof(prop), "ti,psil-config%u", args->args[1]);
1750         chconf_node = ofnode_find_subnode(slave_node, prop);
1751         if (!ofnode_valid(chconf_node)) {
1752                 dev_err(ud->dev, "Channel configuration node is missing\n");
1753                 return -EINVAL;
1754         }
1755
1756         if (!ofnode_read_u32(chconf_node, "linux,udma-mode", &val)) {
1757                 if (val == UDMA_PKT_MODE)
1758                         uc->pkt_mode = true;
1759         }
1760
1761         if (!ofnode_read_u32(chconf_node, "statictr-type", &val))
1762                 uc->static_tr_type = val;
1763
1764         uc->needs_epib = ofnode_read_bool(chconf_node, "ti,needs-epib");
1765         if (!ofnode_read_u32(chconf_node, "ti,psd-size", &val))
1766                 uc->psd_size = val;
1767         uc->metadata_size = (uc->needs_epib ? 16 : 0) + uc->psd_size;
1768
1769         if (ofnode_read_u32(slave_node, "ti,psil-base", &val)) {
1770                 dev_err(ud->dev, "ti,psil-base is missing\n");
1771                 return -EINVAL;
1772         }
1773
1774         uc->slave_thread_id = val + args->args[1];
1775
1776         dma->id = uc->id;
1777         pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
1778                  dma->id, uc->needs_epib,
1779                  uc->psd_size, uc->metadata_size,
1780                  uc->slave_thread_id);
1781
1782         return 0;
1783 }
1784
1785 int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
1786 {
1787         struct udma_dev *ud = dev_get_priv(dma->dev);
1788         struct cppi5_host_desc_t *desc_rx;
1789         dma_addr_t dma_dst;
1790         struct udma_chan *uc;
1791         u32 desc_num;
1792
1793         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1794                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1795                 return -EINVAL;
1796         }
1797         uc = &ud->channels[dma->id];
1798
1799         if (uc->dir != DMA_DEV_TO_MEM)
1800                 return -EINVAL;
1801
1802         if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
1803                 return -EINVAL;
1804
1805         desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
1806         desc_rx = uc->desc_rx + (desc_num * uc->hdesc_size);
1807         dma_dst = (dma_addr_t)dst;
1808
1809         cppi5_hdesc_reset_hbdesc(desc_rx);
1810
1811         cppi5_hdesc_init(desc_rx,
1812                          uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
1813                          uc->psd_size);
1814         cppi5_hdesc_set_pktlen(desc_rx, size);
1815         cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
1816
1817         flush_dcache_range((unsigned long)desc_rx,
1818                            ALIGN((unsigned long)desc_rx + uc->hdesc_size,
1819                                  ARCH_DMA_MINALIGN));
1820
1821         udma_push_to_ring(uc->rchan->fd_ring, desc_rx);
1822
1823         uc->num_rx_bufs++;
1824         uc->desc_rx_cur++;
1825
1826         return 0;
1827 }
1828
1829 static int udma_get_cfg(struct dma *dma, u32 id, void **data)
1830 {
1831         struct udma_dev *ud = dev_get_priv(dma->dev);
1832         struct udma_chan *uc;
1833
1834         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1835                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1836                 return -EINVAL;
1837         }
1838
1839         switch (id) {
1840         case TI_UDMA_CHAN_PRIV_INFO:
1841                 uc = &ud->channels[dma->id];
1842                 *data = &uc->cfg_data;
1843                 return 0;
1844         }
1845
1846         return -EINVAL;
1847 }
1848
1849 static const struct dma_ops udma_ops = {
1850         .transfer       = udma_transfer,
1851         .of_xlate       = udma_of_xlate,
1852         .request        = udma_request,
1853         .rfree          = udma_rfree,
1854         .enable         = udma_enable,
1855         .disable        = udma_disable,
1856         .send           = udma_send,
1857         .receive        = udma_receive,
1858         .prepare_rcv_buf = udma_prepare_rcv_buf,
1859         .get_cfg        = udma_get_cfg,
1860 };
1861
1862 static const struct udevice_id udma_ids[] = {
1863         { .compatible = "ti,k3-navss-udmap" },
1864         { .compatible = "ti,j721e-navss-mcu-udmap" },
1865         { }
1866 };
1867
1868 U_BOOT_DRIVER(ti_edma3) = {
1869         .name   = "ti-udma",
1870         .id     = UCLASS_DMA,
1871         .of_match = udma_ids,
1872         .ops    = &udma_ops,
1873         .probe  = udma_probe,
1874         .priv_auto_alloc_size = sizeof(struct udma_dev),
1875 };