1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2008 by NXP Semiconductors
5 * @Descr: LPC3250 DMA controller interface support functions
7 * Copyright (c) 2015 Tyco Fire Protection Products.
13 #include <asm/arch/dma.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/sys_proto.h>
18 #include <linux/delay.h>
20 /* DMA controller channel register structure */
21 struct dmac_chan_reg {
30 /* DMA controller register structures */
42 u32 sw_last_burst_req;
43 u32 sw_last_single_req;
47 struct dmac_chan_reg dma_chan[8];
50 #define DMA_NO_OF_CHANNELS 8
52 /* config register definitions */
53 #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
57 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
59 int lpc32xx_dma_get_channel(void)
63 if (!alloc_ch) { /* First time caller */
65 * DMA clock are enable by "lpc32xx_dma_init()" and should
66 * be call by board "board_early_init_f()" function.
70 * Make sure DMA controller and all channels are disabled.
71 * Controller is in little-endian mode. Disable sync signals.
73 writel(0, &dma->config);
74 writel(0, &dma->sync);
76 /* Clear interrupt and error statuses */
77 writel(0xFF, &dma->int_tc_clear);
78 writel(0xFF, &dma->raw_tc_stat);
79 writel(0xFF, &dma->int_err_clear);
80 writel(0xFF, &dma->raw_err_stat);
82 /* Enable DMA controller */
83 writel(DMAC_CTRL_ENABLE, &dma->config);
88 /* Check if all the available channels are busy */
89 if (unlikely(i == DMA_NO_OF_CHANNELS))
91 alloc_ch |= BIT_MASK(i);
95 int lpc32xx_dma_start_xfer(unsigned int channel,
96 const struct lpc32xx_dmac_ll *desc, u32 config)
98 if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) ||
99 (channel >= DMA_NO_OF_CHANNELS))) {
100 pr_err("Request for xfer on unallocated channel %d", channel);
103 writel(BIT_MASK(channel), &dma->int_tc_clear);
104 writel(BIT_MASK(channel), &dma->int_err_clear);
105 writel(desc->dma_src, &dma->dma_chan[channel].src_addr);
106 writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);
107 writel(desc->next_lli, &dma->dma_chan[channel].lli);
108 writel(desc->next_ctrl, &dma->dma_chan[channel].control);
109 writel(config, &dma->dma_chan[channel].config_ch);
114 int lpc32xx_dma_wait_status(unsigned int channel)
119 /* Check if given channel is valid */
120 if (unlikely(channel >= DMA_NO_OF_CHANNELS)) {
121 pr_err("Request for status on unallocated channel %d", channel);
125 start = get_timer(0);
127 reg = readl(&dma->raw_tc_stat);
128 reg |= readl(dma->raw_err_stat);
129 if (reg & BIT_MASK(channel))
132 if (get_timer(start) > CONFIG_SYS_HZ) {
133 pr_err("DMA status timeout channel %d\n", channel);
139 if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {
140 setbits_le32(&dma->int_err_clear, BIT_MASK(channel));
141 setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));
142 pr_err("DMA error on channel %d\n", channel);
145 setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));
146 setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));