drivers/dma/bcm6348-iudma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
   4  *
   5  * Derived from linux/drivers/dma/bcm63xx-iudma.c:
   6  *      Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu>
   7  *
   8  * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
   9  *      Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  10  *
  11  * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
  12  *      Copyright (C) 2000-2010 Broadcom Corporation
  13  *
  14  * Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c:
  15  *      Copyright (C) 2010 Broadcom Corporation
  16  */
  17
  18 #include <common.h>
  19 #include <clk.h>
  20 #include <cpu_func.h>
  21 #include <dm.h>
  22 #include <dma-uclass.h>
  23 #include <log.h>
  24 #include <malloc.h>
  25 #include <memalign.h>
  26 #include <net.h>
  27 #include <reset.h>
  28 #include <asm/io.h>
  29 #include <linux/delay.h>
  30
  31 #define DMA_RX_DESC     6
  32 #define DMA_TX_DESC     1
  33
  34 /* DMA Channels */
  35 #define DMA_CHAN_FLOWC(x)               ((x) >> 1)
  36 #define DMA_CHAN_MAX                    16
  37 #define DMA_CHAN_SIZE                   0x10
  38 #define DMA_CHAN_TOUT                   500
  39
  40 /* DMA Global Configuration register */
  41 #define DMA_CFG_REG                     0x00
  42 #define  DMA_CFG_ENABLE_SHIFT           0
  43 #define  DMA_CFG_ENABLE_MASK            (1 << DMA_CFG_ENABLE_SHIFT)
  44 #define  DMA_CFG_FLOWC_ENABLE(x)        BIT(DMA_CHAN_FLOWC(x) + 1)
  45 #define  DMA_CFG_NCHANS_SHIFT           24
  46 #define  DMA_CFG_NCHANS_MASK            (0xf << DMA_CFG_NCHANS_SHIFT)
  47
  48 /* DMA Global Flow Control registers */
  49 #define DMA_FLOWC_THR_LO_REG(x)         (0x04 + DMA_CHAN_FLOWC(x) * 0x0c)
  50 #define DMA_FLOWC_THR_HI_REG(x)         (0x08 + DMA_CHAN_FLOWC(x) * 0x0c)
  51 #define DMA_FLOWC_ALLOC_REG(x)          (0x0c + DMA_CHAN_FLOWC(x) * 0x0c)
  52 #define  DMA_FLOWC_ALLOC_FORCE_SHIFT    31
  53 #define  DMA_FLOWC_ALLOC_FORCE_MASK     (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT)
  54
  55 /* DMA Global Reset register */
  56 #define DMA_RST_REG                     0x34
  57 #define  DMA_RST_CHAN_SHIFT             0
  58 #define  DMA_RST_CHAN_MASK(x)           (1 << x)
  59
  60 /* DMA Channel Configuration register */
  61 #define DMAC_CFG_REG(x)                 (DMA_CHAN_SIZE * (x) + 0x00)
  62 #define  DMAC_CFG_ENABLE_SHIFT          0
  63 #define  DMAC_CFG_ENABLE_MASK           (1 << DMAC_CFG_ENABLE_SHIFT)
  64 #define  DMAC_CFG_PKT_HALT_SHIFT        1
  65 #define  DMAC_CFG_PKT_HALT_MASK         (1 << DMAC_CFG_PKT_HALT_SHIFT)
  66 #define  DMAC_CFG_BRST_HALT_SHIFT       2
  67 #define  DMAC_CFG_BRST_HALT_MASK        (1 << DMAC_CFG_BRST_HALT_SHIFT)
  68
  69 /* DMA Channel Max Burst Length register */
  70 #define DMAC_BURST_REG(x)               (DMA_CHAN_SIZE * (x) + 0x0c)
  71
  72 /* DMA SRAM Descriptor Ring Start register */
  73 #define DMAS_RSTART_REG(x)              (DMA_CHAN_SIZE * (x) + 0x00)
  74
  75 /* DMA SRAM State/Bytes done/ring offset register */
  76 #define DMAS_STATE_DATA_REG(x)          (DMA_CHAN_SIZE * (x) + 0x04)
  77
  78 /* DMA SRAM Buffer Descriptor status and length register */
  79 #define DMAS_DESC_LEN_STATUS_REG(x)     (DMA_CHAN_SIZE * (x) + 0x08)
  80
  81 /* DMA SRAM Buffer Descriptor status and length register */
  82 #define DMAS_DESC_BASE_BUFPTR_REG(x)    (DMA_CHAN_SIZE * (x) + 0x0c)
  83
  84 /* DMA Descriptor Status */
  85 #define DMAD_ST_CRC_SHIFT               8
  86 #define DMAD_ST_CRC_MASK                (1 << DMAD_ST_CRC_SHIFT)
  87 #define DMAD_ST_WRAP_SHIFT              12
  88 #define DMAD_ST_WRAP_MASK               (1 << DMAD_ST_WRAP_SHIFT)
  89 #define DMAD_ST_SOP_SHIFT               13
  90 #define DMAD_ST_SOP_MASK                (1 << DMAD_ST_SOP_SHIFT)
  91 #define DMAD_ST_EOP_SHIFT               14
  92 #define DMAD_ST_EOP_MASK                (1 << DMAD_ST_EOP_SHIFT)
  93 #define DMAD_ST_OWN_SHIFT               15
  94 #define DMAD_ST_OWN_MASK                (1 << DMAD_ST_OWN_SHIFT)
  95
  96 #define DMAD6348_ST_OV_ERR_SHIFT        0
  97 #define DMAD6348_ST_OV_ERR_MASK         (1 << DMAD6348_ST_OV_ERR_SHIFT)
  98 #define DMAD6348_ST_CRC_ERR_SHIFT       1
  99 #define DMAD6348_ST_CRC_ERR_MASK        (1 << DMAD6348_ST_CRC_ERR_SHIFT)
 100 #define DMAD6348_ST_RX_ERR_SHIFT        2
 101 #define DMAD6348_ST_RX_ERR_MASK         (1 << DMAD6348_ST_RX_ERR_SHIFT)
 102 #define DMAD6348_ST_OS_ERR_SHIFT        4
 103 #define DMAD6348_ST_OS_ERR_MASK         (1 << DMAD6348_ST_OS_ERR_SHIFT)
 104 #define DMAD6348_ST_UN_ERR_SHIFT        9
 105 #define DMAD6348_ST_UN_ERR_MASK         (1 << DMAD6348_ST_UN_ERR_SHIFT)
 106
 107 struct bcm6348_dma_desc {
 108         uint16_t length;
 109         uint16_t status;
 110         uint32_t address;
 111 };
 112
 113 struct bcm6348_chan_priv {
 114         void __iomem *dma_ring;
 115         uint8_t dma_ring_size;
 116         uint8_t desc_id;
 117         uint8_t desc_cnt;
 118         bool *busy_desc;
 119         bool running;
 120 };
 121
 122 struct bcm6348_iudma_hw {
 123         uint16_t err_mask;
 124 };
 125
 126 struct bcm6348_iudma_priv {
 127         const struct bcm6348_iudma_hw *hw;
 128         void __iomem *base;
 129         void __iomem *chan;
 130         void __iomem *sram;
 131         struct bcm6348_chan_priv **ch_priv;
 132         uint8_t n_channels;
 133 };
 134
 135 static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch)
 136 {
 137         return !(ch & 1);
 138 }
 139
 140 static inline void bcm6348_iudma_fdc(void *ptr, ulong size)
 141 {
 142         ulong start = (ulong) ptr;
 143
 144         flush_dcache_range(start, start + size);
 145 }
 146
 147 static inline void bcm6348_iudma_idc(void *ptr, ulong size)
 148 {
 149         ulong start = (ulong) ptr;
 150
 151         invalidate_dcache_range(start, start + size);
 152 }
 153
 154 static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv,
 155                                     uint8_t ch)
 156 {
 157         unsigned int timeout = DMA_CHAN_TOUT;
 158
 159         do {
 160                 uint32_t cfg, halt;
 161
 162                 if (timeout > DMA_CHAN_TOUT / 2)
 163                         halt = DMAC_CFG_PKT_HALT_MASK;
 164                 else
 165                         halt = DMAC_CFG_BRST_HALT_MASK;
 166
 167                 /* try to stop dma channel */
 168                 writel_be(halt, priv->chan + DMAC_CFG_REG(ch));
 169                 mb();
 170
 171                 /* check if channel was stopped */
 172                 cfg = readl_be(priv->chan + DMAC_CFG_REG(ch));
 173                 if (!(cfg & DMAC_CFG_ENABLE_MASK))
 174                         break;
 175
 176                 udelay(1);
 177         } while (--timeout);
 178
 179         if (!timeout)
 180                 pr_err("unable to stop channel %u\n", ch);
 181
 182         /* reset dma channel */
 183         setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
 184         mb();
 185         clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
 186 }
 187
 188 static int bcm6348_iudma_disable(struct dma *dma)
 189 {
 190         struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 191         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 192
 193         /* stop dma channel */
 194         bcm6348_iudma_chan_stop(priv, dma->id);
 195
 196         /* dma flow control */
 197         if (bcm6348_iudma_chan_is_rx(dma->id))
 198                 writel_be(DMA_FLOWC_ALLOC_FORCE_MASK,
 199                           DMA_FLOWC_ALLOC_REG(dma->id));
 200
 201         /* init channel config */
 202         ch_priv->running = false;
 203         ch_priv->desc_id = 0;
 204         if (bcm6348_iudma_chan_is_rx(dma->id))
 205                 ch_priv->desc_cnt = 0;
 206         else
 207                 ch_priv->desc_cnt = ch_priv->dma_ring_size;
 208
 209         return 0;
 210 }
 211
 212 static int bcm6348_iudma_enable(struct dma *dma)
 213 {
 214         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 215         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 216         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 217         uint8_t i;
 218
 219         /* dma ring init */
 220         for (i = 0; i < ch_priv->desc_cnt; i++) {
 221                 if (bcm6348_iudma_chan_is_rx(dma->id)) {
 222                         ch_priv->busy_desc[i] = false;
 223                         dma_desc->status |= DMAD_ST_OWN_MASK;
 224                 } else {
 225                         dma_desc->status = 0;
 226                         dma_desc->length = 0;
 227                         dma_desc->address = 0;
 228                 }
 229
 230                 if (i == ch_priv->desc_cnt - 1)
 231                         dma_desc->status |= DMAD_ST_WRAP_MASK;
 232
 233                 dma_desc++;
 234         }
 235
 236         /* init to first descriptor */
 237         ch_priv->desc_id = 0;
 238
 239         /* force cache writeback */
 240         bcm6348_iudma_fdc(ch_priv->dma_ring,
 241                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 242
 243         /* clear sram */
 244         writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id));
 245         writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id));
 246         writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id));
 247
 248         /* set dma ring start */
 249         writel_be(virt_to_phys(ch_priv->dma_ring),
 250                   priv->sram + DMAS_RSTART_REG(dma->id));
 251
 252         /* set flow control */
 253         if (bcm6348_iudma_chan_is_rx(dma->id)) {
 254                 u32 val;
 255
 256                 setbits_be32(priv->base + DMA_CFG_REG,
 257                              DMA_CFG_FLOWC_ENABLE(dma->id));
 258
 259                 val = ch_priv->desc_cnt / 3;
 260                 writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id));
 261
 262                 val = (ch_priv->desc_cnt * 2) / 3;
 263                 writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id));
 264
 265                 writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id));
 266         }
 267
 268         /* set dma max burst */
 269         writel_be(ch_priv->desc_cnt,
 270                   priv->chan + DMAC_BURST_REG(dma->id));
 271
 272         /* kick rx dma channel */
 273         if (bcm6348_iudma_chan_is_rx(dma->id))
 274                 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
 275                              DMAC_CFG_ENABLE_MASK);
 276
 277         /* channel is now enabled */
 278         ch_priv->running = true;
 279
 280         return 0;
 281 }
 282
 283 static int bcm6348_iudma_request(struct dma *dma)
 284 {
 285         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 286         struct bcm6348_chan_priv *ch_priv;
 287
 288         /* check if channel is valid */
 289         if (dma->id >= priv->n_channels)
 290                 return -ENODEV;
 291
 292         /* alloc channel private data */
 293         priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv));
 294         if (!priv->ch_priv[dma->id])
 295                 return -ENOMEM;
 296         ch_priv = priv->ch_priv[dma->id];
 297
 298         /* alloc dma ring */
 299         if (bcm6348_iudma_chan_is_rx(dma->id))
 300                 ch_priv->dma_ring_size = DMA_RX_DESC;
 301         else
 302                 ch_priv->dma_ring_size = DMA_TX_DESC;
 303
 304         ch_priv->dma_ring =
 305                 malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) *
 306                                      ch_priv->dma_ring_size);
 307         if (!ch_priv->dma_ring)
 308                 return -ENOMEM;
 309
 310         /* init channel config */
 311         ch_priv->running = false;
 312         ch_priv->desc_id = 0;
 313         if (bcm6348_iudma_chan_is_rx(dma->id)) {
 314                 ch_priv->desc_cnt = 0;
 315                 ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
 316         } else {
 317                 ch_priv->desc_cnt = ch_priv->dma_ring_size;
 318                 ch_priv->busy_desc = NULL;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata)
 325 {
 326         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 327         const struct bcm6348_iudma_hw *hw = priv->hw;
 328         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 329         struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring;
 330         int ret;
 331
 332         if (!ch_priv->running)
 333                 return -EINVAL;
 334
 335         /* get dma ring descriptor address */
 336         dma_desc += ch_priv->desc_id;
 337
 338         /* invalidate cache data */
 339         bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
 340
 341         /* check dma own */
 342         if (dma_desc->status & DMAD_ST_OWN_MASK)
 343                 return -EAGAIN;
 344
 345         /* check pkt */
 346         if (!(dma_desc->status & DMAD_ST_EOP_MASK) ||
 347             !(dma_desc->status & DMAD_ST_SOP_MASK) ||
 348             (dma_desc->status & hw->err_mask)) {
 349                 pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n",
 350                        dma->id, ch_priv->desc_id, dma_desc->status);
 351                 ret = -EAGAIN;
 352         } else {
 353                 /* set dma buffer address */
 354                 *dst = phys_to_virt(dma_desc->address);
 355
 356                 /* invalidate cache data */
 357                 bcm6348_iudma_idc(*dst, dma_desc->length);
 358
 359                 /* return packet length */
 360                 ret = dma_desc->length;
 361         }
 362
 363         /* busy dma descriptor */
 364         ch_priv->busy_desc[ch_priv->desc_id] = true;
 365
 366         /* increment dma descriptor */
 367         ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
 368
 369         return ret;
 370 }
 371
 372 static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len,
 373                               void *metadata)
 374 {
 375         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 376         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 377         struct bcm6348_dma_desc *dma_desc;
 378         uint16_t status;
 379
 380         if (!ch_priv->running)
 381                 return -EINVAL;
 382
 383         /* flush cache */
 384         bcm6348_iudma_fdc(src, len);
 385
 386         /* get dma ring descriptor address */
 387         dma_desc = ch_priv->dma_ring;
 388         dma_desc += ch_priv->desc_id;
 389
 390         /* config dma descriptor */
 391         status = (DMAD_ST_OWN_MASK |
 392                   DMAD_ST_EOP_MASK |
 393                   DMAD_ST_CRC_MASK |
 394                   DMAD_ST_SOP_MASK);
 395         if (ch_priv->desc_id == ch_priv->desc_cnt - 1)
 396                 status |= DMAD_ST_WRAP_MASK;
 397
 398         /* set dma descriptor */
 399         dma_desc->address = virt_to_phys(src);
 400         dma_desc->length = len;
 401         dma_desc->status = status;
 402
 403         /* flush cache */
 404         bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
 405
 406         /* kick tx dma channel */
 407         setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK);
 408
 409         /* poll dma status */
 410         do {
 411                 /* invalidate cache */
 412                 bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
 413
 414                 if (!(dma_desc->status & DMAD_ST_OWN_MASK))
 415                         break;
 416         } while(1);
 417
 418         /* increment dma descriptor */
 419         ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
 420
 421         return 0;
 422 }
 423
 424 static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size)
 425 {
 426         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 427         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 428         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 429         uint16_t status;
 430         uint8_t i;
 431         u32 cfg;
 432
 433         /* get dirty dma descriptor */
 434         for (i = 0; i < ch_priv->desc_cnt; i++) {
 435                 if (phys_to_virt(dma_desc->address) == dst)
 436                         break;
 437
 438                 dma_desc++;
 439         }
 440
 441         /* dma descriptor not found */
 442         if (i == ch_priv->desc_cnt) {
 443                 pr_err("dirty dma descriptor not found\n");
 444                 return -ENOENT;
 445         }
 446
 447         /* invalidate cache */
 448         bcm6348_iudma_idc(ch_priv->dma_ring,
 449                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 450
 451         /* free dma descriptor */
 452         ch_priv->busy_desc[i] = false;
 453
 454         status = DMAD_ST_OWN_MASK;
 455         if (i == ch_priv->desc_cnt - 1)
 456                 status |= DMAD_ST_WRAP_MASK;
 457
 458         dma_desc->status |= status;
 459         dma_desc->length = PKTSIZE_ALIGN;
 460
 461         /* tell dma we allocated one buffer */
 462         writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id));
 463
 464         /* flush cache */
 465         bcm6348_iudma_fdc(ch_priv->dma_ring,
 466                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 467
 468         /* kick rx dma channel if disabled */
 469         cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id));
 470         if (!(cfg & DMAC_CFG_ENABLE_MASK))
 471                 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
 472                              DMAC_CFG_ENABLE_MASK);
 473
 474         return 0;
 475 }
 476
 477 static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size)
 478 {
 479         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 480         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 481         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 482
 483         /* no more dma descriptors available */
 484         if (ch_priv->desc_cnt == ch_priv->dma_ring_size) {
 485                 pr_err("max number of buffers reached\n");
 486                 return -EINVAL;
 487         }
 488
 489         /* get next dma descriptor */
 490         dma_desc += ch_priv->desc_cnt;
 491
 492         /* init dma descriptor */
 493         dma_desc->address = virt_to_phys(dst);
 494         dma_desc->length = size;
 495         dma_desc->status = 0;
 496
 497         /* flush cache */
 498         bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
 499
 500         /* increment dma descriptors */
 501         ch_priv->desc_cnt++;
 502
 503         return 0;
 504 }
 505
 506 static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst,
 507                                          size_t size)
 508 {
 509         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 510         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 511
 512         /* only add new rx buffers if channel isn't running */
 513         if (ch_priv->running)
 514                 return bcm6348_iudma_free_rcv_buf(dma, dst, size);
 515         else
 516                 return bcm6348_iudma_add_rcv_buf(dma, dst, size);
 517 }
 518
 519 static const struct dma_ops bcm6348_iudma_ops = {
 520         .disable = bcm6348_iudma_disable,
 521         .enable = bcm6348_iudma_enable,
 522         .prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf,
 523         .request = bcm6348_iudma_request,
 524         .receive = bcm6348_iudma_receive,
 525         .send = bcm6348_iudma_send,
 526 };
 527
 528 static const struct bcm6348_iudma_hw bcm6348_hw = {
 529         .err_mask = (DMAD6348_ST_OV_ERR_MASK |
 530                      DMAD6348_ST_CRC_ERR_MASK |
 531                      DMAD6348_ST_RX_ERR_MASK |
 532                      DMAD6348_ST_OS_ERR_MASK |
 533                      DMAD6348_ST_UN_ERR_MASK),
 534 };
 535
 536 static const struct bcm6348_iudma_hw bcm6368_hw = {
 537         .err_mask = 0,
 538 };
 539
 540 static const struct udevice_id bcm6348_iudma_ids[] = {
 541         {
 542                 .compatible = "brcm,bcm6348-iudma",
 543                 .data = (ulong)&bcm6348_hw,
 544         }, {
 545                 .compatible = "brcm,bcm6368-iudma",
 546                 .data = (ulong)&bcm6368_hw,
 547         }, { /* sentinel */ }
 548 };
 549
 550 static int bcm6348_iudma_probe(struct udevice *dev)
 551 {
 552         struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 553         struct bcm6348_iudma_priv *priv = dev_get_priv(dev);
 554         const struct bcm6348_iudma_hw *hw =
 555                 (const struct bcm6348_iudma_hw *)dev_get_driver_data(dev);
 556         uint8_t ch;
 557         int i;
 558
 559         uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM |
 560                               DMA_SUPPORTS_MEM_TO_DEV);
 561         priv->hw = hw;
 562
 563         /* dma global base address */
 564         priv->base = dev_remap_addr_name(dev, "dma");
 565         if (!priv->base)
 566                 return -EINVAL;
 567
 568         /* dma channels base address */
 569         priv->chan = dev_remap_addr_name(dev, "dma-channels");
 570         if (!priv->chan)
 571                 return -EINVAL;
 572
 573         /* dma sram base address */
 574         priv->sram = dev_remap_addr_name(dev, "dma-sram");
 575         if (!priv->sram)
 576                 return -EINVAL;
 577
 578         /* get number of channels */
 579         priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8);
 580         if (priv->n_channels > DMA_CHAN_MAX)
 581                 return -EINVAL;
 582
 583         /* try to enable clocks */
 584         for (i = 0; ; i++) {
 585                 struct clk clk;
 586                 int ret;
 587
 588                 ret = clk_get_by_index(dev, i, &clk);
 589                 if (ret < 0)
 590                         break;
 591
 592                 ret = clk_enable(&clk);
 593                 if (ret < 0) {
 594                         pr_err("error enabling clock %d\n", i);
 595                         return ret;
 596                 }
 597
 598                 ret = clk_free(&clk);
 599                 if (ret < 0) {
 600                         pr_err("error freeing clock %d\n", i);
 601                         return ret;
 602                 }
 603         }
 604
 605         /* try to perform resets */
 606         for (i = 0; ; i++) {
 607                 struct reset_ctl reset;
 608                 int ret;
 609
 610                 ret = reset_get_by_index(dev, i, &reset);
 611                 if (ret < 0)
 612                         break;
 613
 614                 ret = reset_deassert(&reset);
 615                 if (ret < 0) {
 616                         pr_err("error deasserting reset %d\n", i);
 617                         return ret;
 618                 }
 619
 620                 ret = reset_free(&reset);
 621                 if (ret < 0) {
 622                         pr_err("error freeing reset %d\n", i);
 623                         return ret;
 624                 }
 625         }
 626
 627         /* disable dma controller */
 628         clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
 629
 630         /* alloc channel private data pointers */
 631         priv->ch_priv = calloc(priv->n_channels,
 632                                sizeof(struct bcm6348_chan_priv*));
 633         if (!priv->ch_priv)
 634                 return -ENOMEM;
 635
 636         /* stop dma channels */
 637         for (ch = 0; ch < priv->n_channels; ch++)
 638                 bcm6348_iudma_chan_stop(priv, ch);
 639
 640         /* enable dma controller */
 641         setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
 642
 643         return 0;
 644 }
 645
 646 U_BOOT_DRIVER(bcm6348_iudma) = {
 647         .name = "bcm6348_iudma",
 648         .id = UCLASS_DMA,
 649         .of_match = bcm6348_iudma_ids,
 650         .ops = &bcm6348_iudma_ops,
 651         .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv),
 652         .probe = bcm6348_iudma_probe,
 653 };