drivers/ddr/marvell/axp/ddr3_init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <log.h>
   9 #include <spl.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/soc.h>
  13
  14 #include "ddr3_init.h"
  15
  16 #if defined(MV88F78X60)
  17 #include "ddr3_axp_vars.h"
  18 #elif defined(MV88F67XX)
  19 #include "ddr3_a370_vars.h"
  20 #elif defined(MV88F672X)
  21 #include "ddr3_a375_vars.h"
  22 #endif
  23
  24 #ifdef STATIC_TRAINING
  25 static void ddr3_static_training_init(void);
  26 #endif
  27 #ifdef DUNIT_STATIC
  28 static void ddr3_static_mc_init(void);
  29 #endif
  30 #if defined(DUNIT_STATIC) || defined(STATIC_TRAINING)
  31 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void);
  32 #endif
  33 #if defined(MV88F672X)
  34 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
  35 #endif
  36 u32 mv_board_id_get(void);
  37 extern void ddr3_set_sw_wl_rl_debug(u32);
  38 extern void ddr3_set_pbs(u32);
  39 extern void ddr3_set_log_level(u32 val);
  40
  41 static u32 log_level = DDR3_LOG_LEVEL;
  42
  43 static u32 ddr3_init_main(void);
  44
  45 /*
  46  * Name:     ddr3_set_log_level
  47  * Desc:     This routine initialize the log_level acording to nLogLevel
  48  *           which getting from user
  49  * Args:     nLogLevel
  50  * Notes:
  51  * Returns:  None.
  52  */
  53 void ddr3_set_log_level(u32 val)
  54 {
  55         log_level = val;
  56 }
  57
  58 /*
  59  * Name:     ddr3_get_log_level
  60  * Desc:     This routine returns the log level
  61  * Args:     none
  62  * Notes:
  63  * Returns:  log level.
  64  */
  65 u32 ddr3_get_log_level(void)
  66 {
  67         return log_level;
  68 }
  69
  70 static void debug_print_reg(u32 reg)
  71 {
  72         printf("0x%08x = 0x%08x\n", reg, reg_read(reg));
  73 }
  74
  75 static void print_dunit_setup(void)
  76 {
  77         puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n");
  78
  79 #ifdef DUNIT_STATIC
  80         puts("\nStatic D-UNIT Setup:\n");
  81 #endif
  82 #ifdef DUNIT_SPD
  83         puts("\nDynamic(using SPD) D-UNIT Setup:\n");
  84 #endif
  85         debug_print_reg(REG_SDRAM_CONFIG_ADDR);
  86         debug_print_reg(REG_DUNIT_CTRL_LOW_ADDR);
  87         debug_print_reg(REG_SDRAM_TIMING_LOW_ADDR);
  88         debug_print_reg(REG_SDRAM_TIMING_HIGH_ADDR);
  89         debug_print_reg(REG_SDRAM_ADDRESS_CTRL_ADDR);
  90         debug_print_reg(REG_SDRAM_OPEN_PAGES_ADDR);
  91         debug_print_reg(REG_SDRAM_OPERATION_ADDR);
  92         debug_print_reg(REG_SDRAM_MODE_ADDR);
  93         debug_print_reg(REG_SDRAM_EXT_MODE_ADDR);
  94         debug_print_reg(REG_DDR_CONT_HIGH_ADDR);
  95         debug_print_reg(REG_ODT_TIME_LOW_ADDR);
  96         debug_print_reg(REG_SDRAM_ERROR_ADDR);
  97         debug_print_reg(REG_SDRAM_AUTO_PWR_SAVE_ADDR);
  98         debug_print_reg(REG_OUDDR3_TIMING_ADDR);
  99         debug_print_reg(REG_ODT_TIME_HIGH_ADDR);
 100         debug_print_reg(REG_SDRAM_ODT_CTRL_LOW_ADDR);
 101         debug_print_reg(REG_SDRAM_ODT_CTRL_HIGH_ADDR);
 102         debug_print_reg(REG_DUNIT_ODT_CTRL_ADDR);
 103 #ifndef MV88F67XX
 104         debug_print_reg(REG_DRAM_FIFO_CTRL_ADDR);
 105         debug_print_reg(REG_DRAM_AXI_CTRL_ADDR);
 106         debug_print_reg(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR);
 107         debug_print_reg(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR);
 108         debug_print_reg(REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR);
 109         debug_print_reg(REG_DRAM_MAIN_PADS_CAL_ADDR);
 110         debug_print_reg(REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR);
 111         debug_print_reg(REG_CS_SIZE_SCRATCH_ADDR);
 112         debug_print_reg(REG_DYNAMIC_POWER_SAVE_ADDR);
 113         debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
 114         debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR);
 115         debug_print_reg(REG_DDR3_MR0_ADDR);
 116         debug_print_reg(REG_DDR3_MR1_ADDR);
 117         debug_print_reg(REG_DDR3_MR2_ADDR);
 118         debug_print_reg(REG_DDR3_MR3_ADDR);
 119         debug_print_reg(REG_DDR3_RANK_CTRL_ADDR);
 120         debug_print_reg(REG_DRAM_PHY_CONFIG_ADDR);
 121         debug_print_reg(REG_STATIC_DRAM_DLB_CONTROL);
 122         debug_print_reg(DLB_BUS_OPTIMIZATION_WEIGHTS_REG);
 123         debug_print_reg(DLB_AGING_REGISTER);
 124         debug_print_reg(DLB_EVICTION_CONTROL_REG);
 125         debug_print_reg(DLB_EVICTION_TIMERS_REGISTER_REG);
 126 #if defined(MV88F672X)
 127         debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(0));
 128         debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(0));
 129         debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(1));
 130         debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(1));
 131 #else
 132         debug_print_reg(REG_FASTPATH_WIN_0_CTRL_ADDR);
 133 #endif
 134         debug_print_reg(REG_CDI_CONFIG_ADDR);
 135 #endif
 136 }
 137
 138 #if !defined(STATIC_TRAINING)
 139 static void ddr3_restore_and_set_final_windows(u32 *win_backup)
 140 {
 141         u32 ui, reg, cs;
 142         u32 win_ctrl_reg, num_of_win_regs;
 143         u32 cs_ena = ddr3_get_cs_ena_from_reg();
 144
 145 #if defined(MV88F672X)
 146         if (DDR3_FAST_PATH_EN == 0)
 147                 return;
 148 #endif
 149
 150 #if defined(MV88F672X)
 151         win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
 152         num_of_win_regs = 8;
 153 #else
 154         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 155         num_of_win_regs = 16;
 156 #endif
 157
 158         /* Return XBAR windows 4-7 or 16-19 init configuration */
 159         for (ui = 0; ui < num_of_win_regs; ui++)
 160                 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]);
 161
 162         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n");
 163
 164 #if defined(MV88F672X)
 165         /* Set L2 filtering to 1G */
 166         reg_write(0x8c04, 0x40000000);
 167
 168         /* Open fast path windows */
 169         for (cs = 0; cs < MAX_CS; cs++) {
 170                 if (cs_ena & (1 << cs)) {
 171                         /* set fast path window control for the cs */
 172                         reg = 0x1FFFFFE1;
 173                         reg |= (cs << 2);
 174                         reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
 175                         /* Open fast path Window */
 176                         reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
 177                         /* set fast path window base address for the cs */
 178                         reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000);
 179                         /* Set base address */
 180                         reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
 181                 }
 182         }
 183 #else
 184         reg = 0x1FFFFFE1;
 185         for (cs = 0; cs < MAX_CS; cs++) {
 186                 if (cs_ena & (1 << cs)) {
 187                         reg |= (cs << 2);
 188                         break;
 189                 }
 190         }
 191
 192         /* Open fast path Window to - 0.5G */
 193         reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
 194 #endif
 195 }
 196
 197 static void ddr3_save_and_set_training_windows(u32 *win_backup)
 198 {
 199         u32 cs_ena = ddr3_get_cs_ena_from_reg();
 200         u32 reg, tmp_count, cs, ui;
 201         u32 win_ctrl_reg, win_base_reg, win_remap_reg;
 202         u32 num_of_win_regs, win_jump_index;
 203
 204 #if defined(MV88F672X)
 205         /* Disable L2 filtering */
 206         reg_write(0x8c04, 0);
 207
 208         win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
 209         win_base_reg = REG_XBAR_WIN_16_BASE_ADDR;
 210         win_remap_reg = REG_XBAR_WIN_16_REMAP_ADDR;
 211         win_jump_index = 0x8;
 212         num_of_win_regs = 8;
 213 #else
 214         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 215         win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
 216         win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
 217         win_jump_index = 0x10;
 218         num_of_win_regs = 16;
 219 #endif
 220
 221         /* Close XBAR Window 19 - Not needed */
 222         /* {0x000200e8}  -   Open Mbus Window - 2G */
 223         reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
 224
 225         /* Save XBAR Windows 4-19 init configurations */
 226         for (ui = 0; ui < num_of_win_regs; ui++)
 227                 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
 228
 229         /* Open XBAR Windows 4-7 or 16-19 for other CS */
 230         reg = 0;
 231         tmp_count = 0;
 232         for (cs = 0; cs < MAX_CS; cs++) {
 233                 if (cs_ena & (1 << cs)) {
 234                         switch (cs) {
 235                         case 0:
 236                                 reg = 0x0E00;
 237                                 break;
 238                         case 1:
 239                                 reg = 0x0D00;
 240                                 break;
 241                         case 2:
 242                                 reg = 0x0B00;
 243                                 break;
 244                         case 3:
 245                                 reg = 0x0700;
 246                                 break;
 247                         }
 248                         reg |= (1 << 0);
 249                         reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
 250
 251                         reg_write(win_ctrl_reg + win_jump_index * tmp_count,
 252                                   reg);
 253                         reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000;
 254                         reg_write(win_base_reg + win_jump_index * tmp_count,
 255                                   reg);
 256
 257                         if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR) {
 258                                 reg_write(win_remap_reg +
 259                                           win_jump_index * tmp_count, 0);
 260                         }
 261
 262                         tmp_count++;
 263                 }
 264         }
 265 }
 266 #endif /*  !defined(STATIC_TRAINING) */
 267
 268 /*
 269  * Name:     ddr3_init - Main DDR3 Init function
 270  * Desc:     This routine initialize the DDR3 MC and runs HW training.
 271  * Args:     None.
 272  * Notes:
 273  * Returns:  None.
 274  */
 275 int ddr3_init(void)
 276 {
 277         unsigned int status;
 278
 279         ddr3_set_pbs(DDR3_PBS);
 280         ddr3_set_sw_wl_rl_debug(DDR3_RUN_SW_WHEN_HW_FAIL);
 281
 282         status = ddr3_init_main();
 283         if (status == MV_DDR3_TRAINING_ERR_BAD_SAR)
 284                 DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset");
 285         if (status == MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP)
 286                 DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup");
 287         if (status == MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT)
 288                 DEBUG_INIT_S("DDR3 Training Error: Max CS limit");
 289         if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT)
 290                 DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit");
 291         if (status == MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP)
 292                 DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup");
 293         if (status == MV_DDR3_TRAINING_ERR_TWSI_FAIL)
 294                 DEBUG_INIT_S("DDR3 Training Error: TWSI failure");
 295         if (status == MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH)
 296                 DEBUG_INIT_S("DDR3 Training Error: DIMM type no match");
 297         if (status == MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE)
 298                 DEBUG_INIT_S("DDR3 Training Error: TWSI bad type");
 299         if (status == MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH)
 300                 DEBUG_INIT_S("DDR3 Training Error: bus width no match");
 301         if (status > MV_DDR3_TRAINING_ERR_HW_FAIL_BASE)
 302                 DEBUG_INIT_C("DDR3 Training Error: HW Failure 0x", status, 8);
 303
 304         return status;
 305 }
 306
 307 static void print_ddr_target_freq(u32 cpu_freq, u32 fab_opt)
 308 {
 309         puts("\nDDR3 Training Sequence - Run DDR3 at ");
 310
 311         switch (cpu_freq) {
 312 #if defined(MV88F672X)
 313         case 21:
 314                 puts("533 Mhz\n");
 315                 break;
 316 #else
 317         case 1:
 318                 puts("533 Mhz\n");
 319                 break;
 320         case 2:
 321                 if (fab_opt == 5)
 322                         puts("600 Mhz\n");
 323                 if (fab_opt == 9)
 324                         puts("400 Mhz\n");
 325                 break;
 326         case 3:
 327                 puts("667 Mhz\n");
 328                 break;
 329         case 4:
 330                 if (fab_opt == 5)
 331                         puts("750 Mhz\n");
 332                 if (fab_opt == 9)
 333                         puts("500 Mhz\n");
 334                 break;
 335         case 0xa:
 336                 puts("400 Mhz\n");
 337                 break;
 338         case 0xb:
 339                 if (fab_opt == 5)
 340                         puts("800 Mhz\n");
 341                 if (fab_opt == 9)
 342                         puts("553 Mhz\n");
 343                 if (fab_opt == 0xA)
 344                         puts("640 Mhz\n");
 345                 break;
 346 #endif
 347         default:
 348                 puts("NOT DEFINED FREQ\n");
 349         }
 350 }
 351
 352 static u32 ddr3_init_main(void)
 353 {
 354         u32 target_freq;
 355         u32 reg = 0;
 356         u32 cpu_freq, fab_opt, hclk_time_ps, soc_num;
 357         __maybe_unused u32 ecc = DRAM_ECC;
 358         __maybe_unused int dqs_clk_aligned = 0;
 359         __maybe_unused u32 scrub_offs, scrub_size;
 360         __maybe_unused u32 ddr_width = BUS_WIDTH;
 361         __maybe_unused int status;
 362         __maybe_unused u32 win_backup[16];
 363
 364         /* SoC/Board special Initializtions */
 365         fab_opt = ddr3_get_fab_opt();
 366
 367 #ifdef CONFIG_SPD_EEPROM
 368         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 369 #endif
 370
 371         ddr3_print_version();
 372         DEBUG_INIT_S("4\n");
 373         /* Lib version 5.5.4 */
 374
 375         fab_opt = ddr3_get_fab_opt();
 376
 377         /* Switching CPU to MRVL ID */
 378         soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
 379                 SAR1_CPU_CORE_OFFSET;
 380         switch (soc_num) {
 381         case 0x3:
 382                 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
 383                 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
 384         case 0x1:
 385                 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 386         case 0x0:
 387                 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
 388         default:
 389                 break;
 390         }
 391
 392         /* Power down deskew PLL */
 393 #if !defined(MV88F672X)
 394         /* 0x18780 [25] */
 395         reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25));
 396         reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg);
 397 #endif
 398
 399         /*
 400          * Stage 0 - Set board configuration
 401          */
 402         cpu_freq = ddr3_get_cpu_freq();
 403         if (fab_opt > FAB_OPT)
 404                 fab_opt = FAB_OPT - 1;
 405
 406         if (ddr3_get_log_level() > 0)
 407                 print_ddr_target_freq(cpu_freq, fab_opt);
 408
 409 #if defined(MV88F672X)
 410         get_target_freq(cpu_freq, &target_freq, &hclk_time_ps);
 411 #else
 412         target_freq = cpu_ddr_ratios[fab_opt][cpu_freq];
 413         hclk_time_ps = cpu_fab_clk_to_hclk[fab_opt][cpu_freq];
 414 #endif
 415         if ((target_freq == 0) || (hclk_time_ps == 0)) {
 416                 DEBUG_INIT_S("DDR3 Training Sequence - FAILED - Wrong Sample at Reset Configurations\n");
 417                 if (target_freq == 0) {
 418                         DEBUG_INIT_C("target_freq", target_freq, 2);
 419                         DEBUG_INIT_C("fab_opt", fab_opt, 2);
 420                         DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
 421                 } else if (hclk_time_ps == 0) {
 422                         DEBUG_INIT_C("hclk_time_ps", hclk_time_ps, 2);
 423                         DEBUG_INIT_C("fab_opt", fab_opt, 2);
 424                         DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
 425                 }
 426
 427                 return MV_DDR3_TRAINING_ERR_BAD_SAR;
 428         }
 429
 430 #if defined(ECC_SUPPORT)
 431         scrub_offs = U_BOOT_START_ADDR;
 432         scrub_size = U_BOOT_SCRUB_SIZE;
 433 #else
 434         scrub_offs = 0;
 435         scrub_size = 0;
 436 #endif
 437
 438 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
 439         ecc = 0;
 440         if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC))
 441                 ecc = 1;
 442 #endif
 443
 444 #ifdef DQS_CLK_ALIGNED
 445         dqs_clk_aligned = 1;
 446 #endif
 447
 448         /* Check if DRAM is already initialized  */
 449         if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
 450             (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
 451                 DEBUG_INIT_S("DDR3 Training Sequence - 2nd boot - Skip\n");
 452                 return MV_OK;
 453         }
 454
 455         /*
 456          * Stage 1 - Dunit Setup
 457          */
 458
 459 #ifdef DUNIT_STATIC
 460         /*
 461          * For Static D-Unit Setup use must set the correct static values
 462          * at the ddr3_*soc*_vars.h file
 463          */
 464         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n");
 465         ddr3_static_mc_init();
 466
 467 #ifdef ECC_SUPPORT
 468         ecc = DRAM_ECC;
 469         if (ecc) {
 470                 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 471                 reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS);
 472                 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
 473         }
 474 #endif
 475 #endif
 476
 477 #if defined(MV88F78X60) || defined(MV88F672X)
 478 #if defined(AUTO_DETECTION_SUPPORT)
 479         /*
 480          * Configurations for both static and dynamic MC setups
 481          *
 482          * Dynamically Set 32Bit and ECC for AXP (Relevant only for
 483          * Marvell DB boards)
 484          */
 485         if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_BUS_WIDTH)) {
 486                 ddr_width = 32;
 487                 DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n");
 488         }
 489 #endif
 490
 491 #if defined(MV88F672X)
 492         reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 493         if ((reg >> 15) & 1)
 494                 ddr_width = 32;
 495         else
 496                 ddr_width = 16;
 497 #endif
 498 #endif
 499
 500 #ifdef DUNIT_SPD
 501         status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width);
 502         if (MV_OK != status) {
 503                 DEBUG_INIT_S("DDR3 Training Sequence - FAILED (ddr3 Dunit Setup)\n");
 504                 return status;
 505         }
 506 #endif
 507
 508         /* Fix read ready phases for all SOC in reg 0x15C8 */
 509         reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
 510         reg &= ~(REG_TRAINING_DEBUG_3_MASK);
 511         reg |= 0x4;             /* Phase 0 */
 512         reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
 513         reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 1 */
 514         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
 515         reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 3 */
 516         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
 517         reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
 518         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
 519         reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
 520         reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
 521
 522 #if defined(MV88F672X)
 523         /*
 524          * AxiBrespMode[8] = Compliant,
 525          * AxiAddrDecodeCntrl[11] = Internal,
 526          * AxiDataBusWidth[0] = 128bit
 527          */
 528         /* 0x14A8 - AXI Control Register */
 529         reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
 530 #else
 531         /* 0x14A8 - AXI Control Register */
 532         reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000100);
 533         reg_write(REG_CDI_CONFIG_ADDR, 0x00000006);
 534
 535         if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) &
 536                                   (1 << REG_DDR_IO_CLK_RATIO_OFFS))) {
 537                 /* 0x14A8 - AXI Control Register */
 538                 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000101);
 539                 reg_write(REG_CDI_CONFIG_ADDR, 0x00000007);
 540         }
 541 #endif
 542
 543 #if !defined(MV88F67XX)
 544         /*
 545          * ARMADA-370 activate DLB later at the u-boot,
 546          * Armada38x - No DLB activation at this time
 547          */
 548         reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x18C01E);
 549
 550 #if defined(MV88F78X60)
 551         /* WA according to eratta GL-8672902*/
 552         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV)
 553                 reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0xc19e);
 554 #endif
 555
 556         reg_write(DLB_AGING_REGISTER, 0x0f7f007f);
 557         reg_write(DLB_EVICTION_CONTROL_REG, 0x0);
 558         reg_write(DLB_EVICTION_TIMERS_REGISTER_REG, 0x00FF3C1F);
 559
 560         reg_write(MBUS_UNITS_PRIORITY_CONTROL_REG, 0x55555555);
 561         reg_write(FABRIC_UNITS_PRIORITY_CONTROL_REG, 0xAA);
 562         reg_write(MBUS_UNITS_PREFETCH_CONTROL_REG, 0xffff);
 563         reg_write(FABRIC_UNITS_PREFETCH_CONTROL_REG, 0xf0f);
 564
 565 #if defined(MV88F78X60)
 566         /* WA according to eratta GL-8672902 */
 567         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
 568                 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
 569                 reg |= DLB_ENABLE;
 570                 reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
 571         }
 572 #endif /* end defined(MV88F78X60) */
 573 #endif /* end !defined(MV88F67XX) */
 574
 575         if (ddr3_get_log_level() >= MV_LOG_LEVEL_1)
 576                 print_dunit_setup();
 577
 578         /*
 579          * Stage 2 - Training Values Setup
 580          */
 581 #ifdef STATIC_TRAINING
 582         /*
 583          * DRAM Init - After all the D-unit values are set, its time to init
 584          * the D-unit
 585          */
 586         /* Wait for '0' */
 587         reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
 588         do {
 589                 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
 590                         (1 << REG_SDRAM_INIT_CTRL_OFFS);
 591         } while (reg);
 592
 593         /* ddr3 init using static parameters - HW training is disabled */
 594         DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n");
 595         ddr3_static_training_init();
 596
 597 #if defined(MV88F78X60)
 598         /*
 599          * If ECC is enabled, need to scrub the U-Boot area memory region -
 600          * Run training function with Xor bypass just to scrub the memory
 601          */
 602         status = ddr3_hw_training(target_freq, ddr_width,
 603                                   1, scrub_offs, scrub_size,
 604                                   dqs_clk_aligned, DDR3_TRAINING_DEBUG,
 605                                   REG_DIMM_SKIP_WL);
 606         if (MV_OK != status) {
 607                 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
 608                 return status;
 609         }
 610 #endif
 611 #else
 612         /* Set X-BAR windows for the training sequence */
 613         ddr3_save_and_set_training_windows(win_backup);
 614
 615         /* Run DDR3 Training Sequence */
 616         /* DRAM Init */
 617         reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
 618         do {
 619                 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
 620                         (1 << REG_SDRAM_INIT_CTRL_OFFS);
 621         } while (reg);          /* Wait for '0' */
 622
 623         /* ddr3 init using DDR3 HW training procedure */
 624         DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n");
 625         status = ddr3_hw_training(target_freq, ddr_width,
 626                                   0, scrub_offs, scrub_size,
 627                                   dqs_clk_aligned, DDR3_TRAINING_DEBUG,
 628                                   REG_DIMM_SKIP_WL);
 629         if (MV_OK != status) {
 630                 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
 631                 return status;
 632         }
 633 #endif
 634
 635         /*
 636          * Stage 3 - Finish
 637          */
 638 #if defined(MV88F78X60) || defined(MV88F672X)
 639         /* Disable ECC Ignore bit */
 640         reg = reg_read(REG_SDRAM_CONFIG_ADDR) &
 641                 ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
 642         reg_write(REG_SDRAM_CONFIG_ADDR, reg);
 643 #endif
 644
 645 #if !defined(STATIC_TRAINING)
 646         /* Restore and set windows */
 647         ddr3_restore_and_set_final_windows(win_backup);
 648 #endif
 649
 650         /* Update DRAM init indication in bootROM register */
 651         reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
 652         reg_write(REG_BOOTROM_ROUTINE_ADDR,
 653                   reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
 654
 655 #if !defined(MV88F67XX)
 656 #if defined(MV88F78X60)
 657         if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
 658                 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
 659                 if (ecc == 0)
 660                         reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));
 661         }
 662 #endif /* end defined(MV88F78X60) */
 663
 664         reg_write(DLB_EVICTION_CONTROL_REG, 0x9);
 665
 666         reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
 667         reg |= (DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
 668                 DLB_MBUS_PREFETCH_EN | PREFETCH_NLNSZTR);
 669         reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
 670 #endif /* end !defined(MV88F67XX) */
 671
 672 #ifdef STATIC_TRAINING
 673         DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully (S)\n");
 674 #else
 675         DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully\n");
 676 #endif
 677
 678         return MV_OK;
 679 }
 680
 681 /*
 682  * Name:     ddr3_get_cpu_freq
 683  * Desc:     read S@R and return CPU frequency
 684  * Args:
 685  * Notes:
 686  * Returns:  required value
 687  */
 688
 689 u32 ddr3_get_cpu_freq(void)
 690 {
 691         u32 reg, cpu_freq;
 692
 693 #if defined(MV88F672X)
 694         /* Read sample at reset setting */
 695         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);     /* 0xE8200 */
 696         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 697                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 698 #else
 699         /* Read sample at reset setting */
 700         reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);      /* 0x18230 [23:21] */
 701 #if defined(MV88F78X60)
 702         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 703                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 704         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);     /* 0x18234 [20] */
 705         cpu_freq |= (((reg >> REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS) & 0x1) << 3);
 706 #elif defined(MV88F67XX)
 707         cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
 708                 REG_SAMPLE_RESET_CPU_FREQ_OFFS;
 709 #endif
 710 #endif
 711
 712         return cpu_freq;
 713 }
 714
 715 /*
 716  * Name:     ddr3_get_fab_opt
 717  * Desc:     read S@R and return CPU frequency
 718  * Args:
 719  * Notes:
 720  * Returns:  required value
 721  */
 722 u32 ddr3_get_fab_opt(void)
 723 {
 724         __maybe_unused u32 reg, fab_opt;
 725
 726 #if defined(MV88F672X)
 727         return 0;               /* No fabric */
 728 #else
 729         /* Read sample at reset setting */
 730         reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);
 731         fab_opt = (reg & REG_SAMPLE_RESET_FAB_MASK) >>
 732                 REG_SAMPLE_RESET_FAB_OFFS;
 733
 734 #if defined(MV88F78X60)
 735         reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);
 736         fab_opt |= (((reg >> 19) & 0x1) << 4);
 737 #endif
 738
 739         return fab_opt;
 740 #endif
 741 }
 742
 743 /*
 744  * Name:     ddr3_get_vco_freq
 745  * Desc:     read S@R and return VCO frequency
 746  * Args:
 747  * Notes:
 748  * Returns:  required value
 749  */
 750 u32 ddr3_get_vco_freq(void)
 751 {
 752         u32 fab, cpu_freq, ui_vco_freq;
 753
 754         fab = ddr3_get_fab_opt();
 755         cpu_freq = ddr3_get_cpu_freq();
 756
 757         if (fab == 2 || fab == 3 || fab == 7 || fab == 8 || fab == 10 ||
 758             fab == 15 || fab == 17 || fab == 20)
 759                 ui_vco_freq = cpu_freq + CLK_CPU;
 760         else
 761                 ui_vco_freq = cpu_freq;
 762
 763         return ui_vco_freq;
 764 }
 765
 766 #ifdef STATIC_TRAINING
 767 /*
 768  * Name:     ddr3_static_training_init - Init DDR3 Training with
 769  *           static parameters
 770  * Desc:     Use this routine to init the controller without the HW training
 771  *           procedure
 772  *           User must provide compatible header file with registers data.
 773  * Args:     None.
 774  * Notes:
 775  * Returns:  None.
 776  */
 777 void ddr3_static_training_init(void)
 778 {
 779         MV_DRAM_MODES *ddr_mode;
 780         u32 reg;
 781         int j;
 782
 783         ddr_mode = ddr3_get_static_ddr_mode();
 784
 785         j = 0;
 786         while (ddr_mode->vals[j].reg_addr != 0) {
 787                 udelay(10);     /* haim want to delay each write */
 788                 reg_write(ddr_mode->vals[j].reg_addr,
 789                           ddr_mode->vals[j].reg_value);
 790
 791                 if (ddr_mode->vals[j].reg_addr ==
 792                     REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
 793                         do {
 794                                 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
 795                                         REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
 796                         } while (reg);
 797                 j++;
 798         }
 799 }
 800 #endif
 801
 802 /*
 803  * Name:     ddr3_get_static_mc_value - Init Memory controller with static
 804  *           parameters
 805  * Desc:     Use this routine to init the controller without the HW training
 806  *           procedure
 807  *           User must provide compatible header file with registers data.
 808  * Args:     None.
 809  * Notes:
 810  * Returns:  None.
 811  */
 812 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
 813                              u32 mask2)
 814 {
 815         u32 reg, tmp;
 816
 817         reg = reg_read(reg_addr);
 818
 819         tmp = (reg >> offset1) & mask1;
 820         if (mask2)
 821                 tmp |= (reg >> offset2) & mask2;
 822
 823         return tmp;
 824 }
 825
 826 /*
 827  * Name:     ddr3_get_static_ddr_mode - Init Memory controller with static
 828  *           parameters
 829  * Desc:     Use this routine to init the controller without the HW training
 830  *           procedure
 831  *           User must provide compatible header file with registers data.
 832  * Args:     None.
 833  * Notes:
 834  * Returns:  None.
 835  */
 836 __weak MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 837 {
 838         u32 chip_board_rev, i;
 839         u32 size;
 840
 841         /* Do not modify this code. relevant only for marvell Boards */
 842 #if defined(DB_78X60_PCAC)
 843         chip_board_rev = Z1_PCAC;
 844 #elif defined(DB_78X60_AMC)
 845         chip_board_rev = A0_AMC;
 846 #elif defined(DB_88F6710_PCAC)
 847         chip_board_rev = A0_PCAC;
 848 #elif defined(RD_88F6710)
 849         chip_board_rev = A0_RD;
 850 #elif defined(MV88F672X)
 851         chip_board_rev = mv_board_id_get();
 852 #else
 853         chip_board_rev = A0;
 854 #endif
 855
 856         size = sizeof(ddr_modes) / sizeof(MV_DRAM_MODES);
 857         for (i = 0; i < size; i++) {
 858                 if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
 859                     (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
 860                     (chip_board_rev == ddr_modes[i].chip_board_rev))
 861                         return &ddr_modes[i];
 862         }
 863
 864         return &ddr_modes[0];
 865 }
 866
 867 #ifdef DUNIT_STATIC
 868 /*
 869  * Name:     ddr3_static_mc_init - Init Memory controller with static parameters
 870  * Desc:     Use this routine to init the controller without the HW training
 871  *           procedure
 872  *           User must provide compatible header file with registers data.
 873  * Args:     None.
 874  * Notes:
 875  * Returns:  None.
 876  */
 877 void ddr3_static_mc_init(void)
 878 {
 879         MV_DRAM_MODES *ddr_mode;
 880         u32 reg;
 881         int j;
 882
 883         ddr_mode = ddr3_get_static_ddr_mode();
 884         j = 0;
 885         while (ddr_mode->regs[j].reg_addr != 0) {
 886                 reg_write(ddr_mode->regs[j].reg_addr,
 887                           ddr_mode->regs[j].reg_value);
 888                 if (ddr_mode->regs[j].reg_addr ==
 889                     REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
 890                         do {
 891                                 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
 892                                         REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
 893                         } while (reg);
 894                 j++;
 895         }
 896 }
 897 #endif
 898
 899 /*
 900  * Name:     ddr3_check_config - Check user configurations: ECC/MultiCS
 901  * Desc:
 902  * Args:     twsi Address
 903  * Notes:    Only Available for ArmadaXP/Armada 370 DB boards
 904  * Returns:  None.
 905  */
 906 int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type)
 907 {
 908 #ifdef AUTO_DETECTION_SUPPORT
 909         u8 data = 0;
 910         int ret;
 911         int offset;
 912
 913         if ((config_type == CONFIG_ECC) || (config_type == CONFIG_BUS_WIDTH))
 914                 offset = 1;
 915         else
 916                 offset = 0;
 917
 918         ret = i2c_read(twsi_addr, offset, 1, (u8 *)&data, 1);
 919         if (!ret) {
 920                 switch (config_type) {
 921                 case CONFIG_ECC:
 922                         if (data & 0x2)
 923                                 return 1;
 924                         break;
 925                 case CONFIG_BUS_WIDTH:
 926                         if (data & 0x1)
 927                                 return 1;
 928                         break;
 929 #ifdef DB_88F6710
 930                 case CONFIG_MULTI_CS:
 931                         if (CFG_MULTI_CS_MODE(data))
 932                                 return 1;
 933                         break;
 934 #else
 935                 case CONFIG_MULTI_CS:
 936                         break;
 937 #endif
 938                 }
 939         }
 940 #endif
 941
 942         return 0;
 943 }
 944
 945 #if defined(DB_88F78X60_REV2)
 946 /*
 947  * Name:     ddr3_get_eprom_fabric - Get Fabric configuration from EPROM
 948  * Desc:
 949  * Args:     twsi Address
 950  * Notes:    Only Available for ArmadaXP DB Rev2 boards
 951  * Returns:  None.
 952  */
 953 u8 ddr3_get_eprom_fabric(void)
 954 {
 955 #ifdef AUTO_DETECTION_SUPPORT
 956         u8 data = 0;
 957         int ret;
 958
 959         ret = i2c_read(NEW_FABRIC_TWSI_ADDR, 1, 1, (u8 *)&data, 1);
 960         if (!ret)
 961                 return data & 0x1F;
 962 #endif
 963
 964         return 0;
 965 }
 966
 967 #endif
 968
 969 /*
 970  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
 971  * Desc:
 972  * Args:     clValue - the value
 973
 974  * Notes:
 975  * Returns:  required CL value
 976  */
 977 u32 ddr3_cl_to_valid_cl(u32 cl)
 978 {
 979         switch (cl) {
 980         case 5:
 981                 return 2;
 982                 break;
 983         case 6:
 984                 return 4;
 985                 break;
 986         case 7:
 987                 return 6;
 988                 break;
 989         case 8:
 990                 return 8;
 991                 break;
 992         case 9:
 993                 return 10;
 994                 break;
 995         case 10:
 996                 return 12;
 997                 break;
 998         case 11:
 999                 return 14;
1000                 break;
1001         case 12:
1002                 return 1;
1003                 break;
1004         case 13:
1005                 return 3;
1006                 break;
1007         case 14:
1008                 return 5;
1009                 break;
1010         default:
1011                 return 2;
1012         }
1013 }
1014
1015 /*
1016  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
1017  * Desc:
1018  * Args:     clValue - the value
1019  * Notes:
1020  * Returns:  required CL value
1021  */
1022 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl)
1023 {
1024         switch (ui_valid_cl) {
1025         case 1:
1026                 return 12;
1027                 break;
1028         case 2:
1029                 return 5;
1030                 break;
1031         case 3:
1032                 return 13;
1033                 break;
1034         case 4:
1035                 return 6;
1036                 break;
1037         case 5:
1038                 return 14;
1039                 break;
1040         case 6:
1041                 return 7;
1042                 break;
1043         case 8:
1044                 return 8;
1045                 break;
1046         case 10:
1047                 return 9;
1048                 break;
1049         case 12:
1050                 return 10;
1051                 break;
1052         case 14:
1053                 return 11;
1054                 break;
1055         default:
1056                 return 0;
1057         }
1058 }
1059
1060 /*
1061  * Name:     ddr3_get_cs_num_from_reg
1062  * Desc:
1063  * Args:
1064  * Notes:
1065  * Returns:
1066  */
1067 u32 ddr3_get_cs_num_from_reg(void)
1068 {
1069         u32 cs_ena = ddr3_get_cs_ena_from_reg();
1070         u32 cs_count = 0;
1071         u32 cs;
1072
1073         for (cs = 0; cs < MAX_CS; cs++) {
1074                 if (cs_ena & (1 << cs))
1075                         cs_count++;
1076         }
1077
1078         return cs_count;
1079 }
1080
1081 /*
1082  * Name:     ddr3_get_cs_ena_from_reg
1083  * Desc:
1084  * Args:
1085  * Notes:
1086  * Returns:
1087  */
1088 u32 ddr3_get_cs_ena_from_reg(void)
1089 {
1090         return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
1091                 REG_DDR3_RANK_CTRL_CS_ENA_MASK;
1092 }
1093
1094 /*
1095  * mv_ctrl_rev_get - Get Marvell controller device revision number
1096  *
1097  * DESCRIPTION:
1098  *       This function returns 8bit describing the device revision as defined
1099  *       in PCI Express Class Code and Revision ID Register.
1100  *
1101  * INPUT:
1102  *       None.
1103  *
1104  * OUTPUT:
1105  *       None.
1106  *
1107  * RETURN:
1108  *       8bit desscribing Marvell controller revision number
1109  *
1110  */
1111 #if !defined(MV88F672X)
1112 u8 mv_ctrl_rev_get(void)
1113 {
1114         u8 rev_num;
1115
1116 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1117         /* Check pex power state */
1118         u32 pex_power;
1119         pex_power = mv_ctrl_pwr_clck_get(PEX_UNIT_ID, 0);
1120         if (pex_power == 0)
1121                 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 1);
1122 #endif
1123         rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0,
1124                         PCI_CLASS_CODE_AND_REVISION_ID));
1125
1126 #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
1127         /* Return to power off state */
1128         if (pex_power == 0)
1129                 mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 0);
1130 #endif
1131
1132         return (rev_num & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
1133 }
1134
1135 #endif
1136
1137 #if defined(MV88F672X)
1138 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
1139 {
1140         u32 tmp, hclk;
1141
1142         switch (freq_mode) {
1143         case CPU_333MHz_DDR_167MHz_L2_167MHz:
1144                 hclk = 84;
1145                 tmp = DDR_100;
1146                 break;
1147         case CPU_266MHz_DDR_266MHz_L2_133MHz:
1148         case CPU_333MHz_DDR_222MHz_L2_167MHz:
1149         case CPU_400MHz_DDR_200MHz_L2_200MHz:
1150         case CPU_400MHz_DDR_267MHz_L2_200MHz:
1151         case CPU_533MHz_DDR_267MHz_L2_267MHz:
1152         case CPU_500MHz_DDR_250MHz_L2_250MHz:
1153         case CPU_600MHz_DDR_300MHz_L2_300MHz:
1154         case CPU_800MHz_DDR_267MHz_L2_400MHz:
1155         case CPU_900MHz_DDR_300MHz_L2_450MHz:
1156                 tmp = DDR_300;
1157                 hclk = 150;
1158                 break;
1159         case CPU_333MHz_DDR_333MHz_L2_167MHz:
1160         case CPU_500MHz_DDR_334MHz_L2_250MHz:
1161         case CPU_666MHz_DDR_333MHz_L2_333MHz:
1162                 tmp = DDR_333;
1163                 hclk = 165;
1164                 break;
1165         case CPU_533MHz_DDR_356MHz_L2_267MHz:
1166                 tmp = DDR_360;
1167                 hclk = 180;
1168                 break;
1169         case CPU_400MHz_DDR_400MHz_L2_200MHz:
1170         case CPU_600MHz_DDR_400MHz_L2_300MHz:
1171         case CPU_800MHz_DDR_400MHz_L2_400MHz:
1172         case CPU_400MHz_DDR_400MHz_L2_400MHz:
1173                 tmp = DDR_400;
1174                 hclk = 200;
1175                 break;
1176         case CPU_666MHz_DDR_444MHz_L2_333MHz:
1177         case CPU_900MHz_DDR_450MHz_L2_450MHz:
1178                 tmp = DDR_444;
1179                 hclk = 222;
1180                 break;
1181         case CPU_500MHz_DDR_500MHz_L2_250MHz:
1182         case CPU_1000MHz_DDR_500MHz_L2_500MHz:
1183         case CPU_1000MHz_DDR_500MHz_L2_333MHz:
1184                 tmp = DDR_500;
1185                 hclk = 250;
1186                 break;
1187         case CPU_533MHz_DDR_533MHz_L2_267MHz:
1188         case CPU_800MHz_DDR_534MHz_L2_400MHz:
1189         case CPU_1100MHz_DDR_550MHz_L2_550MHz:
1190                 tmp = DDR_533;
1191                 hclk = 267;
1192                 break;
1193         case CPU_600MHz_DDR_600MHz_L2_300MHz:
1194         case CPU_900MHz_DDR_600MHz_L2_450MHz:
1195         case CPU_1200MHz_DDR_600MHz_L2_600MHz:
1196                 tmp = DDR_600;
1197                 hclk = 300;
1198                 break;
1199         case CPU_666MHz_DDR_666MHz_L2_333MHz:
1200         case CPU_1000MHz_DDR_667MHz_L2_500MHz:
1201                 tmp = DDR_666;
1202                 hclk = 333;
1203                 break;
1204         default:
1205                 *ddr_freq = 0;
1206                 *hclk_ps = 0;
1207                 break;
1208         }
1209
1210         *ddr_freq = tmp;                /* DDR freq define */
1211         *hclk_ps = 1000000 / hclk;      /* values are 1/HCLK in ps */
1212
1213         return;
1214 }
1215 #endif