drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #include "ddr3_init.h"
   7 #include "mv_ddr_regs.h"
   8 #include "ddr_training_ip_db.h"
   9 #include <image.h>
  10
  11 #define PATTERN_1       0x55555555
  12 #define PATTERN_2       0xaaaaaaaa
  13
  14 #define VALIDATE_TRAINING_LIMIT(e1, e2)                 \
  15         ((((e2) - (e1) + 1) > 33) && ((e1) < 67))
  16
  17 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
  18
  19 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
  20                  HWS_SEARCH_DIR_LIMIT];
  21 u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; /* holds the bit status in the byte in wrapper function*/
  22
  23 u16 mask_results_dq_reg_map[] = {
  24         RESULT_CONTROL_PUP_0_BIT_0_REG, RESULT_CONTROL_PUP_0_BIT_1_REG,
  25         RESULT_CONTROL_PUP_0_BIT_2_REG, RESULT_CONTROL_PUP_0_BIT_3_REG,
  26         RESULT_CONTROL_PUP_0_BIT_4_REG, RESULT_CONTROL_PUP_0_BIT_5_REG,
  27         RESULT_CONTROL_PUP_0_BIT_6_REG, RESULT_CONTROL_PUP_0_BIT_7_REG,
  28         RESULT_CONTROL_PUP_1_BIT_0_REG, RESULT_CONTROL_PUP_1_BIT_1_REG,
  29         RESULT_CONTROL_PUP_1_BIT_2_REG, RESULT_CONTROL_PUP_1_BIT_3_REG,
  30         RESULT_CONTROL_PUP_1_BIT_4_REG, RESULT_CONTROL_PUP_1_BIT_5_REG,
  31         RESULT_CONTROL_PUP_1_BIT_6_REG, RESULT_CONTROL_PUP_1_BIT_7_REG,
  32         RESULT_CONTROL_PUP_2_BIT_0_REG, RESULT_CONTROL_PUP_2_BIT_1_REG,
  33         RESULT_CONTROL_PUP_2_BIT_2_REG, RESULT_CONTROL_PUP_2_BIT_3_REG,
  34         RESULT_CONTROL_PUP_2_BIT_4_REG, RESULT_CONTROL_PUP_2_BIT_5_REG,
  35         RESULT_CONTROL_PUP_2_BIT_6_REG, RESULT_CONTROL_PUP_2_BIT_7_REG,
  36         RESULT_CONTROL_PUP_3_BIT_0_REG, RESULT_CONTROL_PUP_3_BIT_1_REG,
  37         RESULT_CONTROL_PUP_3_BIT_2_REG, RESULT_CONTROL_PUP_3_BIT_3_REG,
  38         RESULT_CONTROL_PUP_3_BIT_4_REG, RESULT_CONTROL_PUP_3_BIT_5_REG,
  39         RESULT_CONTROL_PUP_3_BIT_6_REG, RESULT_CONTROL_PUP_3_BIT_7_REG,
  40         RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG,
  41         RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
  42         RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG,
  43         RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
  44 #if MAX_BUS_NUM == 9
  45         RESULT_CONTROL_PUP_5_BIT_0_REG, RESULT_CONTROL_PUP_5_BIT_1_REG,
  46         RESULT_CONTROL_PUP_5_BIT_2_REG, RESULT_CONTROL_PUP_5_BIT_3_REG,
  47         RESULT_CONTROL_PUP_5_BIT_4_REG, RESULT_CONTROL_PUP_5_BIT_5_REG,
  48         RESULT_CONTROL_PUP_5_BIT_6_REG, RESULT_CONTROL_PUP_5_BIT_7_REG,
  49         RESULT_CONTROL_PUP_6_BIT_0_REG, RESULT_CONTROL_PUP_6_BIT_1_REG,
  50         RESULT_CONTROL_PUP_6_BIT_2_REG, RESULT_CONTROL_PUP_6_BIT_3_REG,
  51         RESULT_CONTROL_PUP_6_BIT_4_REG, RESULT_CONTROL_PUP_6_BIT_5_REG,
  52         RESULT_CONTROL_PUP_6_BIT_6_REG, RESULT_CONTROL_PUP_6_BIT_7_REG,
  53         RESULT_CONTROL_PUP_7_BIT_0_REG, RESULT_CONTROL_PUP_7_BIT_1_REG,
  54         RESULT_CONTROL_PUP_7_BIT_2_REG, RESULT_CONTROL_PUP_7_BIT_3_REG,
  55         RESULT_CONTROL_PUP_7_BIT_4_REG, RESULT_CONTROL_PUP_7_BIT_5_REG,
  56         RESULT_CONTROL_PUP_7_BIT_6_REG, RESULT_CONTROL_PUP_7_BIT_7_REG,
  57         RESULT_CONTROL_PUP_8_BIT_0_REG, RESULT_CONTROL_PUP_8_BIT_1_REG,
  58         RESULT_CONTROL_PUP_8_BIT_2_REG, RESULT_CONTROL_PUP_8_BIT_3_REG,
  59         RESULT_CONTROL_PUP_8_BIT_4_REG, RESULT_CONTROL_PUP_8_BIT_5_REG,
  60         RESULT_CONTROL_PUP_8_BIT_6_REG, RESULT_CONTROL_PUP_8_BIT_7_REG,
  61 #endif
  62         0xffff
  63 };
  64
  65 u16 mask_results_pup_reg_map[] = {
  66         RESULT_CONTROL_BYTE_PUP_0_REG, RESULT_CONTROL_BYTE_PUP_1_REG,
  67         RESULT_CONTROL_BYTE_PUP_2_REG, RESULT_CONTROL_BYTE_PUP_3_REG,
  68         RESULT_CONTROL_BYTE_PUP_4_REG,
  69 #if MAX_BUS_NUM == 9
  70         RESULT_CONTROL_BYTE_PUP_5_REG, RESULT_CONTROL_BYTE_PUP_6_REG,
  71         RESULT_CONTROL_BYTE_PUP_7_REG, RESULT_CONTROL_BYTE_PUP_8_REG,
  72 #endif
  73         0xffff
  74 };
  75
  76 #if MAX_BUS_NUM == 5
  77 u16 mask_results_dq_reg_map_pup3_ecc[] = {
  78         RESULT_CONTROL_PUP_0_BIT_0_REG, RESULT_CONTROL_PUP_0_BIT_1_REG,
  79         RESULT_CONTROL_PUP_0_BIT_2_REG, RESULT_CONTROL_PUP_0_BIT_3_REG,
  80         RESULT_CONTROL_PUP_0_BIT_4_REG, RESULT_CONTROL_PUP_0_BIT_5_REG,
  81         RESULT_CONTROL_PUP_0_BIT_6_REG, RESULT_CONTROL_PUP_0_BIT_7_REG,
  82         RESULT_CONTROL_PUP_1_BIT_0_REG, RESULT_CONTROL_PUP_1_BIT_1_REG,
  83         RESULT_CONTROL_PUP_1_BIT_2_REG, RESULT_CONTROL_PUP_1_BIT_3_REG,
  84         RESULT_CONTROL_PUP_1_BIT_4_REG, RESULT_CONTROL_PUP_1_BIT_5_REG,
  85         RESULT_CONTROL_PUP_1_BIT_6_REG, RESULT_CONTROL_PUP_1_BIT_7_REG,
  86         RESULT_CONTROL_PUP_2_BIT_0_REG, RESULT_CONTROL_PUP_2_BIT_1_REG,
  87         RESULT_CONTROL_PUP_2_BIT_2_REG, RESULT_CONTROL_PUP_2_BIT_3_REG,
  88         RESULT_CONTROL_PUP_2_BIT_4_REG, RESULT_CONTROL_PUP_2_BIT_5_REG,
  89         RESULT_CONTROL_PUP_2_BIT_6_REG, RESULT_CONTROL_PUP_2_BIT_7_REG,
  90         RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG,
  91         RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
  92         RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG,
  93         RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
  94         RESULT_CONTROL_PUP_3_BIT_0_REG, RESULT_CONTROL_PUP_3_BIT_1_REG,
  95         RESULT_CONTROL_PUP_3_BIT_2_REG, RESULT_CONTROL_PUP_3_BIT_3_REG,
  96         RESULT_CONTROL_PUP_3_BIT_4_REG, RESULT_CONTROL_PUP_3_BIT_5_REG,
  97         RESULT_CONTROL_PUP_3_BIT_6_REG, RESULT_CONTROL_PUP_3_BIT_7_REG
  98 };
  99 #endif
 100
 101 #if MAX_BUS_NUM == 5
 102 u16 mask_results_pup_reg_map_pup3_ecc[] = {
 103         RESULT_CONTROL_BYTE_PUP_0_REG, RESULT_CONTROL_BYTE_PUP_1_REG,
 104         RESULT_CONTROL_BYTE_PUP_2_REG, RESULT_CONTROL_BYTE_PUP_4_REG,
 105         RESULT_CONTROL_BYTE_PUP_4_REG
 106 };
 107 #endif
 108
 109 struct pattern_info pattern_table_64[] = {
 110         /*
 111          * num_of_phases_tx, tx_burst_size;
 112          * delay_between_bursts, num_of_phases_rx,
 113          * start_addr, pattern_len
 114          */
 115         {0x7, 0x7, 2, 0x7, 0x00000, 8},         /* PATTERN_PBS1 */
 116         {0x7, 0x7, 2, 0x7, 0x00080, 8},         /* PATTERN_PBS2 */
 117         {0x7, 0x7, 2, 0x7, 0x00100, 8},         /* PATTERN_PBS3 */
 118         {0x7, 0x7, 2, 0x7, 0x00030, 8},         /* PATTERN_TEST */
 119         {0x7, 0x7, 2, 0x7, 0x00100, 8},         /* PATTERN_RL */
 120         {0x7, 0x7, 2, 0x7, 0x00100, 8},         /* PATTERN_RL2 */
 121         {0x1f, 0xf, 2, 0xf, 0x00680, 32},       /* PATTERN_STATIC_PBS */
 122         {0x1f, 0xf, 2, 0xf, 0x00a80, 32},       /* PATTERN_KILLER_DQ0 */
 123         {0x1f, 0xf, 2, 0xf, 0x01280, 32},       /* PATTERN_KILLER_DQ1 */
 124         {0x1f, 0xf, 2, 0xf, 0x01a80, 32},       /* PATTERN_KILLER_DQ2 */
 125         {0x1f, 0xf, 2, 0xf, 0x02280, 32},       /* PATTERN_KILLER_DQ3 */
 126         {0x1f, 0xf, 2, 0xf, 0x02a80, 32},       /* PATTERN_KILLER_DQ4 */
 127         {0x1f, 0xf, 2, 0xf, 0x03280, 32},       /* PATTERN_KILLER_DQ5 */
 128         {0x1f, 0xf, 2, 0xf, 0x03a80, 32},       /* PATTERN_KILLER_DQ6 */
 129         {0x1f, 0xf, 2, 0xf, 0x04280, 32},       /* PATTERN_KILLER_DQ7 */
 130         {0x1f, 0xf, 2, 0xf, 0x00e80, 32},       /* PATTERN_KILLER_DQ0_64 */
 131         {0x1f, 0xf, 2, 0xf, 0x01680, 32},       /* PATTERN_KILLER_DQ1_64 */
 132         {0x1f, 0xf, 2, 0xf, 0x01e80, 32},       /* PATTERN_KILLER_DQ2_64 */
 133         {0x1f, 0xf, 2, 0xf, 0x02680, 32},       /* PATTERN_KILLER_DQ3_64 */
 134         {0x1f, 0xf, 2, 0xf, 0x02e80, 32},       /* PATTERN_KILLER_DQ4_64 */
 135         {0x1f, 0xf, 2, 0xf, 0x03680, 32},       /* PATTERN_KILLER_DQ5_64 */
 136         {0x1f, 0xf, 2, 0xf, 0x03e80, 32},       /* PATTERN_KILLER_DQ6_64 */
 137         {0x1f, 0xf, 2, 0xf, 0x04680, 32},       /* PATTERN_KILLER_DQ7_64 */
 138         {0x1f, 0xf, 2, 0xf, 0x04a80, 32},       /* PATTERN_KILLER_DQ0_INV */
 139         {0x1f, 0xf, 2, 0xf, 0x05280, 32},       /* PATTERN_KILLER_DQ1_INV */
 140         {0x1f, 0xf, 2, 0xf, 0x05a80, 32},       /* PATTERN_KILLER_DQ2_INV */
 141         {0x1f, 0xf, 2, 0xf, 0x06280, 32},       /* PATTERN_KILLER_DQ3_INV */
 142         {0x1f, 0xf, 2, 0xf, 0x06a80, 32},       /* PATTERN_KILLER_DQ4_INV */
 143         {0x1f, 0xf, 2, 0xf, 0x07280, 32},       /* PATTERN_KILLER_DQ5_INV */
 144         {0x1f, 0xf, 2, 0xf, 0x07a80, 32},       /* PATTERN_KILLER_DQ6_INV */
 145         {0x1f, 0xf, 2, 0xf, 0x08280, 32},       /* PATTERN_KILLER_DQ7_INV */
 146         {0x1f, 0xf, 2, 0xf, 0x04e80, 32},       /* PATTERN_KILLER_DQ0_INV_64 */
 147         {0x1f, 0xf, 2, 0xf, 0x05680, 32},       /* PATTERN_KILLER_DQ1_INV_64 */
 148         {0x1f, 0xf, 2, 0xf, 0x05e80, 32},       /* PATTERN_KILLER_DQ2_INV_64 */
 149         {0x1f, 0xf, 2, 0xf, 0x06680, 32},       /* PATTERN_KILLER_DQ3_INV_64 */
 150         {0x1f, 0xf, 2, 0xf, 0x06e80, 32},       /* PATTERN_KILLER_DQ4_INV_64 */
 151         {0x1f, 0xf, 2, 0xf, 0x07680, 32},       /* PATTERN_KILLER_DQ5_INV_64 */
 152         {0x1f, 0xf, 2, 0xf, 0x07e80, 32},       /* PATTERN_KILLER_DQ6_INV_64 */
 153         {0x1f, 0xf, 2, 0xf, 0x08680, 32},       /* PATTERN_KILLER_DQ7_INV_64 */
 154         {0x1f, 0xf, 2, 0xf, 0x08a80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ0 */
 155         {0x1f, 0xf, 2, 0xf, 0x09280, 32},       /* PATTERN_SSO_FULL_XTALK_DQ1 */
 156         {0x1f, 0xf, 2, 0xf, 0x09a80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ2 */
 157         {0x1f, 0xf, 2, 0xf, 0x0a280, 32},       /* PATTERN_SSO_FULL_XTALK_DQ3 */
 158         {0x1f, 0xf, 2, 0xf, 0x0aa80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ4 */
 159         {0x1f, 0xf, 2, 0xf, 0x0b280, 32},       /* PATTERN_SSO_FULL_XTALK_DQ5 */
 160         {0x1f, 0xf, 2, 0xf, 0x0ba80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ6 */
 161         {0x1f, 0xf, 2, 0xf, 0x0c280, 32},       /* PATTERN_SSO_FULL_XTALK_DQ7 */
 162         {0x1f, 0xf, 2, 0xf, 0x08e80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ0_64 */
 163         {0x1f, 0xf, 2, 0xf, 0x09680, 32},       /* PATTERN_SSO_FULL_XTALK_DQ1_64 */
 164         {0x1f, 0xf, 2, 0xf, 0x09e80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ2_64 */
 165         {0x1f, 0xf, 2, 0xf, 0x0a680, 32},       /* PATTERN_SSO_FULL_XTALK_DQ3_64 */
 166         {0x1f, 0xf, 2, 0xf, 0x0ae80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ4_64 */
 167         {0x1f, 0xf, 2, 0xf, 0x0b680, 32},       /* PATTERN_SSO_FULL_XTALK_DQ5_64 */
 168         {0x1f, 0xf, 2, 0xf, 0x0be80, 32},       /* PATTERN_SSO_FULL_XTALK_DQ6_64 */
 169         {0x1f, 0xf, 2, 0xf, 0x0c680, 32},       /* PATTERN_SSO_FULL_XTALK_DQ7_64 */
 170         {0x1f, 0xf, 2, 0xf, 0x0ca80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ0 */
 171         {0x1f, 0xf, 2, 0xf, 0x0d280, 32},       /* PATTERN_SSO_XTALK_FREE_DQ1 */
 172         {0x1f, 0xf, 2, 0xf, 0x0da80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ2 */
 173         {0x1f, 0xf, 2, 0xf, 0x0e280, 32},       /* PATTERN_SSO_XTALK_FREE_DQ3 */
 174         {0x1f, 0xf, 2, 0xf, 0x0ea80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ4 */
 175         {0x1f, 0xf, 2, 0xf, 0x0f280, 32},       /* PATTERN_SSO_XTALK_FREE_DQ5 */
 176         {0x1f, 0xf, 2, 0xf, 0x0fa80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ6 */
 177         {0x1f, 0xf, 2, 0xf, 0x10280, 32},       /* PATTERN_SSO_XTALK_FREE_DQ7 */
 178         {0x1f, 0xf, 2, 0xf, 0x0ce80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ0_64 */
 179         {0x1f, 0xf, 2, 0xf, 0x0d680, 32},       /* PATTERN_SSO_XTALK_FREE_DQ1_64 */
 180         {0x1f, 0xf, 2, 0xf, 0x0de80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ2_64 */
 181         {0x1f, 0xf, 2, 0xf, 0x0e680, 32},       /* PATTERN_SSO_XTALK_FREE_DQ3_64 */
 182         {0x1f, 0xf, 2, 0xf, 0x0ee80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ4_64 */
 183         {0x1f, 0xf, 2, 0xf, 0x0f680, 32},       /* PATTERN_SSO_XTALK_FREE_DQ5_64 */
 184         {0x1f, 0xf, 2, 0xf, 0x0fe80, 32},       /* PATTERN_SSO_XTALK_FREE_DQ6_64 */
 185         {0x1f, 0xf, 2, 0xf, 0x10680, 32},       /* PATTERN_SSO_XTALK_FREE_DQ7_64 */
 186         {0x1f, 0xf, 2, 0xf, 0x10a80, 32},       /* PATTERN_ISI_XTALK_FREE */
 187         {0x1f, 0xf, 2, 0xf, 0x10e80, 32},       /* PATTERN_ISI_XTALK_FREE_64 */
 188         {0x1f, 0xf, 2, 0xf, 0x11280, 32},       /* PATTERN_VREF */
 189         {0x1f, 0xf, 2, 0xf, 0x11680, 32},       /* PATTERN_VREF_64 */
 190         {0x1f, 0xf, 2, 0xf, 0x11a80, 32},       /* PATTERN_VREF_INV */
 191         {0x1f, 0xf, 2, 0xf, 0x11e80, 32},       /* PATTERN_FULL_SSO_0T */
 192         {0x1f, 0xf, 2, 0xf, 0x12280, 32},       /* PATTERN_FULL_SSO_1T */
 193         {0x1f, 0xf, 2, 0xf, 0x12680, 32},       /* PATTERN_FULL_SSO_2T */
 194         {0x1f, 0xf, 2, 0xf, 0x12a80, 32},       /* PATTERN_FULL_SSO_3T */
 195         {0x1f, 0xf, 2, 0xf, 0x12e80, 32},       /* PATTERN_RESONANCE_1T */
 196         {0x1f, 0xf, 2, 0xf, 0x13280, 32},       /* PATTERN_RESONANCE_2T */
 197         {0x1f, 0xf, 2, 0xf, 0x13680, 32},       /* PATTERN_RESONANCE_3T */
 198         {0x1f, 0xf, 2, 0xf, 0x13a80, 32},       /* PATTERN_RESONANCE_4T */
 199         {0x1f, 0xf, 2, 0xf, 0x13e80, 32},       /* PATTERN_RESONANCE_5T */
 200         {0x1f, 0xf, 2, 0xf, 0x14280, 32},       /* PATTERN_RESONANCE_6T */
 201         {0x1f, 0xf, 2, 0xf, 0x14680, 32},       /* PATTERN_RESONANCE_7T */
 202         {0x1f, 0xf, 2, 0xf, 0x14a80, 32},       /* PATTERN_RESONANCE_8T */
 203         {0x1f, 0xf, 2, 0xf, 0x14e80, 32},       /* PATTERN_RESONANCE_9T */
 204         {0x1f, 0xf, 2, 0xf, 0x15280, 32},       /* PATTERN_ZERO */
 205         {0x1f, 0xf, 2, 0xf, 0x15680, 32}        /* PATTERN_ONE */
 206         /* Note: actual start_address is "<< 3" of defined address */
 207 };
 208
 209 struct pattern_info pattern_table_16[] = {
 210         /*
 211          * num tx phases, tx burst, delay between, rx pattern,
 212          * start_address, pattern_len
 213          */
 214         {1, 1, 2, 1, 0x0080, 2},        /* PATTERN_PBS1 */
 215         {1, 1, 2, 1, 0x00c0, 2},        /* PATTERN_PBS2 */
 216         {1, 1, 2, 1, 0x0380, 2},        /* PATTERN_PBS3 */
 217         {1, 1, 2, 1, 0x0040, 2},        /* PATTERN_TEST */
 218         {1, 1, 2, 1, 0x0100, 2},        /* PATTERN_RL */
 219         {1, 1, 2, 1, 0x0000, 2},        /* PATTERN_RL2 */
 220         {0xf, 0x7, 2, 0x7, 0x0140, 16}, /* PATTERN_STATIC_PBS */
 221         {0xf, 0x7, 2, 0x7, 0x0190, 16}, /* PATTERN_KILLER_DQ0 */
 222         {0xf, 0x7, 2, 0x7, 0x01d0, 16}, /* PATTERN_KILLER_DQ1 */
 223         {0xf, 0x7, 2, 0x7, 0x0210, 16}, /* PATTERN_KILLER_DQ2 */
 224         {0xf, 0x7, 2, 0x7, 0x0250, 16}, /* PATTERN_KILLER_DQ3 */
 225         {0xf, 0x7, 2, 0x7, 0x0290, 16}, /* PATTERN_KILLER_DQ4 */
 226         {0xf, 0x7, 2, 0x7, 0x02d0, 16}, /* PATTERN_KILLER_DQ5 */
 227         {0xf, 0x7, 2, 0x7, 0x0310, 16}, /* PATTERN_KILLER_DQ6 */
 228         {0xf, 0x7, 2, 0x7, 0x0350, 16}, /* PATTERN_KILLER_DQ7 */
 229         {0xf, 0x7, 2, 0x7, 0x04c0, 16}, /* PATTERN_VREF */
 230         {0xf, 0x7, 2, 0x7, 0x03c0, 16}, /* PATTERN_FULL_SSO_1T */
 231         {0xf, 0x7, 2, 0x7, 0x0400, 16}, /* PATTERN_FULL_SSO_2T */
 232         {0xf, 0x7, 2, 0x7, 0x0440, 16}, /* PATTERN_FULL_SSO_3T */
 233         {0xf, 0x7, 2, 0x7, 0x0480, 16}, /* PATTERN_FULL_SSO_4T */
 234         {0xf, 7, 2, 7, 0x6280, 16},     /* PATTERN_SSO_FULL_XTALK_DQ1 */
 235         {0xf, 7, 2, 7, 0x6680, 16},     /* PATTERN_SSO_FULL_XTALK_DQ1 */
 236         {0xf, 7, 2, 7, 0x6A80, 16},     /* PATTERN_SSO_FULL_XTALK_DQ2 */
 237         {0xf, 7, 2, 7, 0x6E80, 16},     /* PATTERN_SSO_FULL_XTALK_DQ3 */
 238         {0xf, 7, 2, 7, 0x7280, 16},     /* PATTERN_SSO_FULL_XTALK_DQ4 */
 239         {0xf, 7, 2, 7, 0x7680, 16},     /* PATTERN_SSO_FULL_XTALK_DQ5 */
 240         {0xf, 7, 2, 7, 0x7A80, 16},     /* PATTERN_SSO_FULL_XTALK_DQ6 */
 241         {0xf, 7, 2, 7, 0x7E80, 16},     /* PATTERN_SSO_FULL_XTALK_DQ7 */
 242         {0xf, 7, 2, 7, 0x8280, 16},     /* PATTERN_SSO_XTALK_FREE_DQ0 */
 243         {0xf, 7, 2, 7, 0x8680, 16},     /* PATTERN_SSO_XTALK_FREE_DQ1 */
 244         {0xf, 7, 2, 7, 0x8A80, 16},     /* PATTERN_SSO_XTALK_FREE_DQ2 */
 245         {0xf, 7, 2, 7, 0x8E80, 16},     /* PATTERN_SSO_XTALK_FREE_DQ3 */
 246         {0xf, 7, 2, 7, 0x9280, 16},     /* PATTERN_SSO_XTALK_FREE_DQ4 */
 247         {0xf, 7, 2, 7, 0x9680, 16},     /* PATTERN_SSO_XTALK_FREE_DQ5 */
 248         {0xf, 7, 2, 7, 0x9A80, 16},     /* PATTERN_SSO_XTALK_FREE_DQ6 */
 249         {0xf, 7, 2, 7, 0x9E80, 16},     /* PATTERN_SSO_XTALK_FREE_DQ7 */
 250         {0xf, 7, 2, 7, 0xA280, 16}      /* PATTERN_ISI_XTALK_FREE */
 251         /* Note: actual start_address is "<< 3" of defined address */
 252 };
 253
 254 struct pattern_info pattern_table_32[] = {
 255         /*
 256          * num tx phases, tx burst, delay between, rx pattern,
 257          * start_address, pattern_len
 258          */
 259         {3, 3, 2, 3, 0x0080, 4},        /* PATTERN_PBS1 */
 260         {3, 3, 2, 3, 0x00c0, 4},        /* PATTERN_PBS2 */
 261         {3, 3, 2, 3, 0x0380, 4},        /* PATTERN_PBS3 */
 262         {3, 3, 2, 3, 0x0040, 4},        /* PATTERN_TEST */
 263         {3, 3, 2, 3, 0x0100, 4},        /* PATTERN_RL */
 264         {3, 3, 2, 3, 0x0000, 4},        /* PATTERN_RL2 */
 265         {0x1f, 0xf, 2, 0xf, 0x0140, 32},        /* PATTERN_STATIC_PBS */
 266         {0x1f, 0xf, 2, 0xf, 0x0190, 32},        /* PATTERN_KILLER_DQ0 */
 267         {0x1f, 0xf, 2, 0xf, 0x01d0, 32},        /* PATTERN_KILLER_DQ1 */
 268         {0x1f, 0xf, 2, 0xf, 0x0210, 32},        /* PATTERN_KILLER_DQ2 */
 269         {0x1f, 0xf, 2, 0xf, 0x0250, 32},        /* PATTERN_KILLER_DQ3 */
 270         {0x1f, 0xf, 2, 0xf, 0x0290, 32},        /* PATTERN_KILLER_DQ4 */
 271         {0x1f, 0xf, 2, 0xf, 0x02d0, 32},        /* PATTERN_KILLER_DQ5 */
 272         {0x1f, 0xf, 2, 0xf, 0x0310, 32},        /* PATTERN_KILLER_DQ6 */
 273         {0x1f, 0xf, 2, 0xf, 0x0350, 32},        /* PATTERN_KILLER_DQ7 */
 274         {0x1f, 0xf, 2, 0xf, 0x04c0, 32},        /* PATTERN_VREF */
 275         {0x1f, 0xf, 2, 0xf, 0x03c0, 32},        /* PATTERN_FULL_SSO_1T */
 276         {0x1f, 0xf, 2, 0xf, 0x0400, 32},        /* PATTERN_FULL_SSO_2T */
 277         {0x1f, 0xf, 2, 0xf, 0x0440, 32},        /* PATTERN_FULL_SSO_3T */
 278         {0x1f, 0xf, 2, 0xf, 0x0480, 32},        /* PATTERN_FULL_SSO_4T */
 279         {0x1f, 0xF, 2, 0xf, 0x6280, 32},        /* PATTERN_SSO_FULL_XTALK_DQ0 */
 280         {0x1f, 0xF, 2, 0xf, 0x6680, 32},        /* PATTERN_SSO_FULL_XTALK_DQ1 */
 281         {0x1f, 0xF, 2, 0xf, 0x6A80, 32},        /* PATTERN_SSO_FULL_XTALK_DQ2 */
 282         {0x1f, 0xF, 2, 0xf, 0x6E80, 32},        /* PATTERN_SSO_FULL_XTALK_DQ3 */
 283         {0x1f, 0xF, 2, 0xf, 0x7280, 32},        /* PATTERN_SSO_FULL_XTALK_DQ4 */
 284         {0x1f, 0xF, 2, 0xf, 0x7680, 32},        /* PATTERN_SSO_FULL_XTALK_DQ5 */
 285         {0x1f, 0xF, 2, 0xf, 0x7A80, 32},        /* PATTERN_SSO_FULL_XTALK_DQ6 */
 286         {0x1f, 0xF, 2, 0xf, 0x7E80, 32},        /* PATTERN_SSO_FULL_XTALK_DQ7 */
 287         {0x1f, 0xF, 2, 0xf, 0x8280, 32},        /* PATTERN_SSO_XTALK_FREE_DQ0 */
 288         {0x1f, 0xF, 2, 0xf, 0x8680, 32},        /* PATTERN_SSO_XTALK_FREE_DQ1 */
 289         {0x1f, 0xF, 2, 0xf, 0x8A80, 32},        /* PATTERN_SSO_XTALK_FREE_DQ2 */
 290         {0x1f, 0xF, 2, 0xf, 0x8E80, 32},        /* PATTERN_SSO_XTALK_FREE_DQ3 */
 291         {0x1f, 0xF, 2, 0xf, 0x9280, 32},        /* PATTERN_SSO_XTALK_FREE_DQ4 */
 292         {0x1f, 0xF, 2, 0xf, 0x9680, 32},        /* PATTERN_SSO_XTALK_FREE_DQ5 */
 293         {0x1f, 0xF, 2, 0xf, 0x9A80, 32},        /* PATTERN_SSO_XTALK_FREE_DQ6 */
 294         {0x1f, 0xF, 2, 0xf, 0x9E80, 32},        /* PATTERN_SSO_XTALK_FREE_DQ7 */
 295         {0x1f, 0xF, 2, 0xf, 0xA280, 32}         /* PATTERN_ISI_XTALK_FREE */
 296         /* Note: actual start_address is "<< 3" of defined address */
 297 };
 298
 299 u32 train_dev_num;
 300 enum hws_ddr_cs traintrain_cs_type;
 301 u32 train_pup_num;
 302 enum hws_training_result train_result_type;
 303 enum hws_control_element train_control_element;
 304 enum hws_search_dir traine_search_dir;
 305 enum hws_dir train_direction;
 306 u32 train_if_select;
 307 u32 train_init_value;
 308 u32 train_number_iterations;
 309 enum hws_pattern train_pattern;
 310 enum hws_edge_compare train_edge_compare;
 311 u32 train_cs_num;
 312 u32 train_if_acess, train_if_id, train_pup_access;
 313 u32 max_polling_for_done = 1000000;
 314
 315 u32 *ddr3_tip_get_buf_ptr(u32 dev_num, enum hws_search_dir search,
 316                           enum hws_training_result result_type,
 317                           u32 interface_num)
 318 {
 319         u32 *buf_ptr = NULL;
 320
 321         buf_ptr = &training_res
 322                 [MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search +
 323                  interface_num * MAX_BUS_NUM * BUS_WIDTH_IN_BITS];
 324
 325         return buf_ptr;
 326 }
 327
 328 enum {
 329         PASS,
 330         FAIL
 331 };
 332 /*
 333  * IP Training search
 334  * Note: for one edge search only from fail to pass, else jitter can
 335  * be be entered into solution.
 336  */
 337 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
 338                          u32 interface_num,
 339                          enum hws_access_type pup_access_type,
 340                          u32 pup_num, enum hws_training_result result_type,
 341                          enum hws_control_element control_element,
 342                          enum hws_search_dir search_dir, enum hws_dir direction,
 343                          u32 interface_mask, u32 init_value, u32 num_iter,
 344                          enum hws_pattern pattern,
 345                          enum hws_edge_compare edge_comp,
 346                          enum hws_ddr_cs cs_type, u32 cs_num,
 347                          enum hws_training_ip_stat *train_status)
 348 {
 349         u32 mask_dq_num_of_regs, mask_pup_num_of_regs, index_cnt,
 350                 reg_data, pup_id;
 351         u32 tx_burst_size;
 352         u32 delay_between_burst;
 353         u32 rd_mode;
 354         u32 data;
 355         struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
 356         u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
 357         u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
 358         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 359         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 360
 361         if (pup_num >= octets_per_if_num) {
 362                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 363                                          ("pup_num %d not valid\n", pup_num));
 364         }
 365         if (interface_num >= MAX_INTERFACE_NUM) {
 366                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 367                                          ("if_id %d not valid\n",
 368                                           interface_num));
 369         }
 370         if (train_status == NULL) {
 371                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 372                                          ("error param 4\n"));
 373                 return MV_BAD_PARAM;
 374         }
 375
 376         /* load pattern */
 377         if (cs_type == CS_SINGLE) {
 378                 /* All CSs to CS0     */
 379                 CHECK_STATUS(ddr3_tip_if_write
 380                              (dev_num, access_type, interface_num,
 381                               DUAL_DUNIT_CFG_REG, 1 << 3, 1 << 3));
 382                 /* All CSs to CS0     */
 383                 CHECK_STATUS(ddr3_tip_if_write
 384                              (dev_num, access_type, interface_num,
 385                               ODPG_DATA_CTRL_REG,
 386                               (0x3 | (effective_cs << 26)), 0xc000003));
 387         } else {
 388                 CHECK_STATUS(ddr3_tip_if_write
 389                              (dev_num, access_type, interface_num,
 390                               DUAL_DUNIT_CFG_REG, 0, 1 << 3));
 391                 /*  CS select */
 392                 CHECK_STATUS(ddr3_tip_if_write
 393                              (dev_num, access_type, interface_num,
 394                               ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26,
 395                               0x3 | 3 << 26));
 396         }
 397
 398         /* load pattern to ODPG */
 399         ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num,
 400                                       pattern,
 401                                       pattern_table[pattern].start_addr);
 402         tx_burst_size = (direction == OPER_WRITE) ?
 403                 pattern_table[pattern].tx_burst_size : 0;
 404         delay_between_burst = (direction == OPER_WRITE) ? 2 : 0;
 405         rd_mode = (direction == OPER_WRITE) ? 1 : 0;
 406         CHECK_STATUS(ddr3_tip_configure_odpg
 407                      (dev_num, access_type, interface_num, direction,
 408                       pattern_table[pattern].num_of_phases_tx, tx_burst_size,
 409                       pattern_table[pattern].num_of_phases_rx,
 410                       delay_between_burst, rd_mode, effective_cs, STRESS_NONE,
 411                       DURATION_SINGLE));
 412         reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30);
 413         reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa;
 414         CHECK_STATUS(ddr3_tip_if_write
 415                      (dev_num, access_type, interface_num,
 416                       ODPG_WR_RD_MODE_ENA_REG, reg_data,
 417                       MASK_ALL_BITS));
 418         reg_data = (edge_comp == EDGE_PF || edge_comp == EDGE_FP) ? 0 : 1 << 6;
 419         reg_data |= (edge_comp == EDGE_PF || edge_comp == EDGE_PFP) ?
 420                 (1 << 7) : 0;
 421
 422         /* change from Pass to Fail will lock the result */
 423         if (pup_access_type == ACCESS_TYPE_MULTICAST)
 424                 reg_data |= 0xe << 14;
 425         else
 426                 reg_data |= pup_num << 14;
 427
 428         if (edge_comp == EDGE_FP) {
 429                 /* don't search for readl edge change, only the state */
 430                 reg_data |= (0 << 20);
 431         } else if (edge_comp == EDGE_FPF) {
 432                 reg_data |= (0 << 20);
 433         } else {
 434                 reg_data |= (3 << 20);
 435         }
 436
 437         CHECK_STATUS(ddr3_tip_if_write
 438                      (dev_num, access_type, interface_num,
 439                       GENERAL_TRAINING_OPCODE_REG,
 440                       reg_data | (0x7 << 8) | (0x7 << 11),
 441                       (0x3 | (0x3 << 2) | (0x3 << 6) | (1 << 5) | (0x7 << 8) |
 442                        (0x7 << 11) | (0xf << 14) | (0x3 << 18) | (3 << 20))));
 443         reg_data = (search_dir == HWS_LOW2HIGH) ? 0 : (1 << 8);
 444         CHECK_STATUS(ddr3_tip_if_write
 445                      (dev_num, access_type, interface_num, OPCODE_REG0_REG(1),
 446                       1 | reg_data | init_value << 9 | (1 << 25) | (1 << 26),
 447                       0xff | (1 << 8) | (0xffff << 9) | (1 << 25) | (1 << 26)));
 448
 449         /*
 450          * Write2_dunit(0x10b4, Number_iteration , [15:0])
 451          * Max number of iterations
 452          */
 453         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, interface_num,
 454                                        OPCODE_REG1_REG(1), num_iter,
 455                                        0xffff));
 456         if (control_element == HWS_CONTROL_ELEMENT_DQ_SKEW &&
 457             direction == OPER_READ) {
 458                 /*
 459                  * Write2_dunit(0x10c0, 0x5f , [7:0])
 460                  * MC PBS Reg Address at DDR PHY
 461                  */
 462                 reg_data = PBS_RX_BCAST_PHY_REG(effective_cs);
 463         } else if (control_element == HWS_CONTROL_ELEMENT_DQ_SKEW &&
 464                    direction == OPER_WRITE) {
 465                 reg_data = PBS_TX_BCAST_PHY_REG(effective_cs);
 466         } else if (control_element == HWS_CONTROL_ELEMENT_ADLL &&
 467                    direction == OPER_WRITE) {
 468                 /*
 469                  * LOOP         0x00000001 + 4*n:
 470                  * where n (0-3) represents M_CS number
 471                  */
 472                 /*
 473                  * Write2_dunit(0x10c0, 0x1 , [7:0])
 474                  * ADLL WR Reg Address at DDR PHY
 475                  */
 476                 reg_data = CTX_PHY_REG(effective_cs);
 477         } else if (control_element == HWS_CONTROL_ELEMENT_ADLL &&
 478                    direction == OPER_READ) {
 479                 /* ADLL RD Reg Address at DDR PHY */
 480                 reg_data = CRX_PHY_REG(effective_cs);
 481         } else if (control_element == HWS_CONTROL_ELEMENT_DQS_SKEW &&
 482                    direction == OPER_WRITE) {
 483                 /* TBD not defined in 0.5.0 requirement  */
 484         } else if (control_element == HWS_CONTROL_ELEMENT_DQS_SKEW &&
 485                    direction == OPER_READ) {
 486                 /* TBD not defined in 0.5.0 requirement */
 487         }
 488
 489         reg_data |= (0x6 << 28);
 490         CHECK_STATUS(ddr3_tip_if_write
 491                      (dev_num, access_type, interface_num, CAL_PHY_REG(1),
 492                       reg_data | (init_value << 8),
 493                       0xff | (0xffff << 8) | (0xf << 24) | (u32) (0xf << 28)));
 494
 495         mask_dq_num_of_regs = octets_per_if_num * BUS_WIDTH_IN_BITS;
 496         mask_pup_num_of_regs = octets_per_if_num;
 497
 498         if (result_type == RESULT_PER_BIT) {
 499                 for (index_cnt = 0; index_cnt < mask_dq_num_of_regs;
 500                      index_cnt++) {
 501                         CHECK_STATUS(ddr3_tip_if_write
 502                                      (dev_num, access_type, interface_num,
 503                                       mask_results_dq_reg_map[index_cnt], 0,
 504                                       1 << 24));
 505                 }
 506
 507                 /* Mask disabled buses */
 508                 for (pup_id = 0; pup_id < octets_per_if_num;
 509                      pup_id++) {
 510                         if (IS_BUS_ACTIVE(tm->bus_act_mask, pup_id) == 1)
 511                                 continue;
 512
 513                         for (index_cnt = (pup_id * 8); index_cnt < (pup_id + 1) * 8; index_cnt++) {
 514                                 CHECK_STATUS(ddr3_tip_if_write
 515                                              (dev_num, access_type,
 516                                               interface_num,
 517                                               mask_results_dq_reg_map
 518                                               [index_cnt], (1 << 24), 1 << 24));
 519                         }
 520                 }
 521
 522                 for (index_cnt = 0; index_cnt < mask_pup_num_of_regs;
 523                      index_cnt++) {
 524                         CHECK_STATUS(ddr3_tip_if_write
 525                                      (dev_num, access_type, interface_num,
 526                                       mask_results_pup_reg_map[index_cnt],
 527                                       (1 << 24), 1 << 24));
 528                 }
 529         } else if (result_type == RESULT_PER_BYTE) {
 530                 /* write to adll */
 531                 for (index_cnt = 0; index_cnt < mask_pup_num_of_regs;
 532                      index_cnt++) {
 533                         CHECK_STATUS(ddr3_tip_if_write
 534                                      (dev_num, access_type, interface_num,
 535                                       mask_results_pup_reg_map[index_cnt], 0,
 536                                       1 << 24));
 537                 }
 538                 for (index_cnt = 0; index_cnt < mask_dq_num_of_regs;
 539                      index_cnt++) {
 540                         CHECK_STATUS(ddr3_tip_if_write
 541                                      (dev_num, access_type, interface_num,
 542                                       mask_results_dq_reg_map[index_cnt],
 543                                       (1 << 24), (1 << 24)));
 544                 }
 545         }
 546
 547         /* trigger training */
 548         mv_ddr_training_enable();
 549
 550         /* wa for 16-bit mode: wait for all rfu tests to finish or timeout */
 551         mdelay(1);
 552
 553         /* check for training done */
 554         if (mv_ddr_is_training_done(MAX_POLLING_ITERATIONS, &data) != MV_OK) {
 555                 train_status[0] = HWS_TRAINING_IP_STATUS_TIMEOUT;
 556         } else { /* training done; check for pass */
 557                 if (data == PASS)
 558                         train_status[0] = HWS_TRAINING_IP_STATUS_SUCCESS;
 559                 else
 560                         train_status[0] = HWS_TRAINING_IP_STATUS_FAIL;
 561         }
 562
 563         ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 564                           ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
 565
 566         return MV_OK;
 567 }
 568
 569 /*
 570  * Load expected Pattern to ODPG
 571  */
 572 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
 573                                   u32 if_id, enum hws_pattern pattern,
 574                                   u32 load_addr)
 575 {
 576         u32 pattern_length_cnt = 0;
 577         struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
 578         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 579
 580         for (pattern_length_cnt = 0;
 581              pattern_length_cnt < pattern_table[pattern].pattern_len;
 582              pattern_length_cnt++) {    /* FIXME: the ecc patch below is only for a7040 A0 */
 583                 if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)/* || tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK*/) {
 584                         CHECK_STATUS(ddr3_tip_if_write
 585                                      (dev_num, access_type, if_id,
 586                                       ODPG_DATA_WR_DATA_LOW_REG,
 587                                       pattern_table_get_word(dev_num, pattern,
 588                                                              (u8) (pattern_length_cnt)),
 589                                       MASK_ALL_BITS));
 590                         CHECK_STATUS(ddr3_tip_if_write
 591                                      (dev_num, access_type, if_id,
 592                                       ODPG_DATA_WR_DATA_HIGH_REG,
 593                                       pattern_table_get_word(dev_num, pattern,
 594                                                              (u8) (pattern_length_cnt)),
 595                                       MASK_ALL_BITS));
 596                 } else {
 597                         CHECK_STATUS(ddr3_tip_if_write
 598                                      (dev_num, access_type, if_id,
 599                                               ODPG_DATA_WR_DATA_LOW_REG,
 600                                       pattern_table_get_word(dev_num, pattern,
 601                                                              (u8) (pattern_length_cnt * 2)),
 602                                       MASK_ALL_BITS));
 603                         CHECK_STATUS(ddr3_tip_if_write
 604                                      (dev_num, access_type, if_id,
 605                                       ODPG_DATA_WR_DATA_HIGH_REG,
 606                                       pattern_table_get_word(dev_num, pattern,
 607                                                              (u8) (pattern_length_cnt * 2 + 1)),
 608                                       MASK_ALL_BITS));
 609                 }
 610                 CHECK_STATUS(ddr3_tip_if_write
 611                              (dev_num, access_type, if_id,
 612                               ODPG_DATA_WR_ADDR_REG, pattern_length_cnt,
 613                               MASK_ALL_BITS));
 614         }
 615
 616         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
 617                                        ODPG_DATA_BUFFER_OFFS_REG,
 618                                        load_addr, MASK_ALL_BITS));
 619
 620         return MV_OK;
 621 }
 622
 623 /*
 624  * Configure ODPG
 625  */
 626 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
 627                             u32 if_id, enum hws_dir direction, u32 tx_phases,
 628                             u32 tx_burst_size, u32 rx_phases,
 629                             u32 delay_between_burst, u32 rd_mode, u32 cs_num,
 630                             u32 addr_stress_jump, u32 single_pattern)
 631 {
 632         u32 data_value = 0;
 633         int ret;
 634
 635         data_value = ((single_pattern << 2) | (tx_phases << 5) |
 636                       (tx_burst_size << 11) | (delay_between_burst << 15) |
 637                       (rx_phases << 21) | (rd_mode << 25) | (cs_num << 26) |
 638                       (addr_stress_jump << 29));
 639         ret = ddr3_tip_if_write(dev_num, access_type, if_id,
 640                                 ODPG_DATA_CTRL_REG, data_value, 0xaffffffc);
 641         if (ret != MV_OK)
 642                 return ret;
 643
 644         return MV_OK;
 645 }
 646
 647 int ddr3_tip_process_result(u32 *ar_result, enum hws_edge e_edge,
 648                             enum hws_edge_search e_edge_search,
 649                             u32 *edge_result)
 650 {
 651         u32 i, res;
 652         int tap_val, max_val = -10000, min_val = 10000;
 653         int lock_success = 1;
 654
 655         for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {
 656                 res = GET_LOCK_RESULT(ar_result[i]);
 657                 if (res == 0) {
 658                         lock_success = 0;
 659                         break;
 660                 }
 661                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 662                                          ("lock failed for bit %d\n", i));
 663         }
 664
 665         if (lock_success == 1) {
 666                 for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {
 667                         tap_val = GET_TAP_RESULT(ar_result[i], e_edge);
 668                         if (tap_val > max_val)
 669                                 max_val = tap_val;
 670                         if (tap_val < min_val)
 671                                 min_val = tap_val;
 672                         if (e_edge_search == TRAINING_EDGE_MAX)
 673                                 *edge_result = (u32) max_val;
 674                         else
 675                                 *edge_result = (u32) min_val;
 676
 677                         DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 678                                                  ("i %d ar_result[i] 0x%x tap_val %d max_val %d min_val %d Edge_result %d\n",
 679                                                   i, ar_result[i], tap_val,
 680                                                   max_val, min_val,
 681                                                   *edge_result));
 682                 }
 683         } else {
 684                 return MV_FAIL;
 685         }
 686
 687         return MV_OK;
 688 }
 689
 690 /*
 691  * Read training search result
 692  */
 693 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
 694                                   enum hws_access_type pup_access_type,
 695                                   u32 pup_num, u32 bit_num,
 696                                   enum hws_search_dir search,
 697                                   enum hws_dir direction,
 698                                   enum hws_training_result result_type,
 699                                   enum hws_training_load_op operation,
 700                                   u32 cs_num_type, u32 **load_res,
 701                                   int is_read_from_db, u8 cons_tap,
 702                                   int is_check_result_validity)
 703 {
 704         u32 reg_offset, pup_cnt, start_pup, end_pup, start_reg, end_reg;
 705         u32 *interface_train_res = NULL;
 706         u16 *reg_addr = NULL;
 707         u32 read_data[MAX_INTERFACE_NUM];
 708         u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map();
 709         u16 *mask_results_dq_reg_map = ddr3_tip_get_mask_results_dq_reg();
 710         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 711         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 712
 713         /*
 714          * Agreed assumption: all CS mask contain same number of bits,
 715          * i.e. in multi CS, the number of CS per memory is the same for
 716          * all pups
 717          */
 718         CHECK_STATUS(ddr3_tip_if_write
 719                      (dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG,
 720                       (cs_num_type == 0) ? 1 << 3 : 0, (1 << 3)));
 721         CHECK_STATUS(ddr3_tip_if_write
 722                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
 723                       ODPG_DATA_CTRL_REG, (cs_num_type << 26), (3 << 26)));
 724         DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_TRACE,
 725                                  ("Read_from_d_b %d cs_type %d oper %d result_type %d direction %d search %d pup_num %d if_id %d pup_access_type %d\n",
 726                                   is_read_from_db, cs_num_type, operation,
 727                                   result_type, direction, search, pup_num,
 728                                   if_id, pup_access_type));
 729
 730         if ((load_res == NULL) && (is_read_from_db == 1)) {
 731                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 732                                          ("ddr3_tip_read_training_result load_res = NULL"));
 733                 return MV_FAIL;
 734         }
 735         if (pup_num >= octets_per_if_num) {
 736                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 737                                          ("pup_num %d not valid\n", pup_num));
 738         }
 739         if (if_id >= MAX_INTERFACE_NUM) {
 740                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 741                                          ("if_id %d not valid\n", if_id));
 742         }
 743         if (result_type == RESULT_PER_BIT)
 744                 reg_addr = mask_results_dq_reg_map;
 745         else
 746                 reg_addr = mask_results_pup_reg_map;
 747         if (pup_access_type == ACCESS_TYPE_UNICAST) {
 748                 start_pup = pup_num;
 749                 end_pup = pup_num;
 750         } else {                /*pup_access_type == ACCESS_TYPE_MULTICAST) */
 751
 752                 start_pup = 0;
 753                 end_pup = octets_per_if_num - 1;
 754         }
 755
 756         for (pup_cnt = start_pup; pup_cnt <= end_pup; pup_cnt++) {
 757                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup_cnt);
 758                 DEBUG_TRAINING_IP_ENGINE(
 759                         DEBUG_LEVEL_TRACE,
 760                         ("if_id %d start_pup %d end_pup %d pup_cnt %d\n",
 761                          if_id, start_pup, end_pup, pup_cnt));
 762                 if (result_type == RESULT_PER_BIT) {
 763                         if (bit_num == ALL_BITS_PER_PUP) {
 764                                 start_reg = pup_cnt * BUS_WIDTH_IN_BITS;
 765                                 end_reg = (pup_cnt + 1) * BUS_WIDTH_IN_BITS - 1;
 766                         } else {
 767                                 start_reg =
 768                                         pup_cnt * BUS_WIDTH_IN_BITS + bit_num;
 769                                 end_reg = pup_cnt * BUS_WIDTH_IN_BITS + bit_num;
 770                         }
 771                 } else {
 772                         start_reg = pup_cnt;
 773                         end_reg = pup_cnt;
 774                 }
 775
 776                 interface_train_res =
 777                         ddr3_tip_get_buf_ptr(dev_num, search, result_type,
 778                                              if_id);
 779                 DEBUG_TRAINING_IP_ENGINE(
 780                         DEBUG_LEVEL_TRACE,
 781                         ("start_reg %d end_reg %d interface %p\n",
 782                          start_reg, end_reg, interface_train_res));
 783                 if (interface_train_res == NULL) {
 784                         DEBUG_TRAINING_IP_ENGINE(
 785                                 DEBUG_LEVEL_ERROR,
 786                                 ("interface_train_res is NULL\n"));
 787                         return MV_FAIL;
 788                 }
 789
 790                 for (reg_offset = start_reg; reg_offset <= end_reg;
 791                      reg_offset++) {
 792                         if (operation == TRAINING_LOAD_OPERATION_UNLOAD) {
 793                                 if (is_read_from_db == 0) {
 794                                         CHECK_STATUS(ddr3_tip_if_read
 795                                                      (dev_num,
 796                                                       ACCESS_TYPE_UNICAST,
 797                                                       if_id,
 798                                                       reg_addr[reg_offset],
 799                                                       read_data,
 800                                                       MASK_ALL_BITS));
 801                                         if (is_check_result_validity == 1) {
 802                                                 if ((read_data[if_id] &
 803                                                      TIP_ENG_LOCK) == 0) {
 804                                                         interface_train_res
 805                                                                 [reg_offset] =
 806                                                                 TIP_ENG_LOCK +
 807                                                                 TIP_TX_DLL_RANGE_MAX;
 808                                                 } else {
 809                                                         interface_train_res
 810                                                                 [reg_offset] =
 811                                                                 read_data
 812                                                                 [if_id] +
 813                                                                 cons_tap;
 814                                                 }
 815                                         } else {
 816                                                 interface_train_res[reg_offset]
 817                                                         = read_data[if_id] +
 818                                                         cons_tap;
 819                                         }
 820                                         DEBUG_TRAINING_IP_ENGINE
 821                                                 (DEBUG_LEVEL_TRACE,
 822                                                  ("reg_offset %d value 0x%x addr %p\n",
 823                                                   reg_offset,
 824                                                   interface_train_res
 825                                                   [reg_offset],
 826                                                   &interface_train_res
 827                                                   [reg_offset]));
 828                                 } else {
 829                                         *load_res =
 830                                                 &interface_train_res[start_reg];
 831                                         DEBUG_TRAINING_IP_ENGINE
 832                                                 (DEBUG_LEVEL_TRACE,
 833                                                  ("*load_res %p\n", *load_res));
 834                                 }
 835                         } else {
 836                                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_TRACE,
 837                                                          ("not supported\n"));
 838                         }
 839                 }
 840         }
 841
 842         return MV_OK;
 843 }
 844
 845 /*
 846  * Load all pattern to memory using ODPG
 847  */
 848 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
 849 {
 850         u32 pattern = 0, if_id;
 851         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 852
 853         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
 854                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 855                 training_result[training_stage][if_id] = TEST_SUCCESS;
 856         }
 857
 858         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
 859                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 860                 /* enable single cs */
 861                 CHECK_STATUS(ddr3_tip_if_write
 862                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
 863                               DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
 864         }
 865
 866         for (pattern = 0; pattern < PATTERN_LAST; pattern++)
 867                 ddr3_tip_load_pattern_to_mem(dev_num, pattern);
 868
 869         return MV_OK;
 870 }
 871
 872 /*
 873  * Load specific pattern to memory using ODPG
 874  */
 875 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern)
 876 {
 877         u32 reg_data, if_id;
 878         struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
 879         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 880
 881         /* load pattern to memory */
 882         /*
 883          * Write Tx mode, CS0, phases, Tx burst size, delay between burst,
 884          * rx pattern phases
 885          */
 886         reg_data =
 887                 0x1 | (pattern_table[pattern].num_of_phases_tx << 5) |
 888                 (pattern_table[pattern].tx_burst_size << 11) |
 889                 (pattern_table[pattern].delay_between_bursts << 15) |
 890                 (pattern_table[pattern].num_of_phases_rx << 21) | (0x1 << 25) |
 891                 (effective_cs << 26);
 892         CHECK_STATUS(ddr3_tip_if_write
 893                      (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 894                       ODPG_DATA_CTRL_REG, reg_data, MASK_ALL_BITS));
 895         /* ODPG Write enable from BIST */
 896         CHECK_STATUS(ddr3_tip_if_write
 897                      (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 898                       ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)),
 899                       0xc000003));
 900         /* disable error injection */
 901         CHECK_STATUS(ddr3_tip_if_write
 902                      (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 903                       ODPG_DATA_WR_DATA_ERR_REG, 0, 0x1));
 904         /* load pattern to ODPG */
 905         ddr3_tip_load_pattern_to_odpg(dev_num, ACCESS_TYPE_MULTICAST,
 906                                       PARAM_NOT_CARE, pattern,
 907                                       pattern_table[pattern].start_addr);
 908
 909         if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) >= MV_TIP_REV_3) {
 910                 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
 911                         VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 912
 913                         CHECK_STATUS(ddr3_tip_if_write
 914                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
 915                                       SDRAM_ODT_CTRL_HIGH_REG,
 916                                       0x3, 0xf));
 917                 }
 918
 919                 mv_ddr_odpg_enable();
 920         } else {
 921                 CHECK_STATUS(ddr3_tip_if_write
 922                              (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 923                               ODPG_DATA_CTRL_REG, (u32)(0x1 << 31),
 924                               (u32)(0x1 << 31)));
 925         }
 926         mdelay(1);
 927
 928         if (mv_ddr_is_odpg_done(MAX_POLLING_ITERATIONS) != MV_OK)
 929                 return MV_FAIL;
 930
 931         /* Disable ODPG and stop write to memory */
 932         CHECK_STATUS(ddr3_tip_if_write
 933                      (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 934                       ODPG_DATA_CTRL_REG, (0x1 << 30), (u32) (0x3 << 30)));
 935
 936         /* return to default */
 937         CHECK_STATUS(ddr3_tip_if_write
 938                      (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 939                       ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS));
 940
 941         if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) >= MV_TIP_REV_3) {
 942                 /* Disable odt0 for CS0 training - need to adjust for multy CS */
 943                 CHECK_STATUS(ddr3_tip_if_write
 944                              (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
 945                               SDRAM_ODT_CTRL_HIGH_REG, 0x0, 0xf));
 946         }
 947         /* temporary added */
 948         mdelay(1);
 949
 950         return MV_OK;
 951 }
 952
 953 /*
 954  * Training search routine
 955  */
 956 int ddr3_tip_ip_training_wrapper_int(u32 dev_num,
 957                                      enum hws_access_type access_type,
 958                                      u32 if_id,
 959                                      enum hws_access_type pup_access_type,
 960                                      u32 pup_num, u32 bit_num,
 961                                      enum hws_training_result result_type,
 962                                      enum hws_control_element control_element,
 963                                      enum hws_search_dir search_dir,
 964                                      enum hws_dir direction,
 965                                      u32 interface_mask, u32 init_value_l2h,
 966                                      u32 init_value_h2l, u32 num_iter,
 967                                      enum hws_pattern pattern,
 968                                      enum hws_edge_compare edge_comp,
 969                                      enum hws_ddr_cs train_cs_type, u32 cs_num,
 970                                      enum hws_training_ip_stat *train_status)
 971 {
 972         u32 interface_num = 0, start_if, end_if, init_value_used;
 973         enum hws_search_dir search_dir_id, start_search, end_search;
 974         enum hws_edge_compare edge_comp_used;
 975         u8 cons_tap = 0;
 976         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 977         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 978
 979         if (train_status == NULL) {
 980                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
 981                                          ("train_status is NULL\n"));
 982                 return MV_FAIL;
 983         }
 984
 985         if ((train_cs_type > CS_NON_SINGLE) ||
 986             (edge_comp >= EDGE_PFP) ||
 987             (pattern >= PATTERN_LAST) ||
 988             (direction > OPER_WRITE_AND_READ) ||
 989             (search_dir > HWS_HIGH2LOW) ||
 990             (control_element > HWS_CONTROL_ELEMENT_DQS_SKEW) ||
 991             (result_type > RESULT_PER_BYTE) ||
 992             (pup_num >= octets_per_if_num) ||
 993             (pup_access_type > ACCESS_TYPE_MULTICAST) ||
 994             (if_id > 11) || (access_type > ACCESS_TYPE_MULTICAST)) {
 995                 DEBUG_TRAINING_IP_ENGINE(
 996                         DEBUG_LEVEL_ERROR,
 997                         ("wrong parameter train_cs_type %d edge_comp %d pattern %d direction %d search_dir %d control_element %d result_type %d pup_num %d pup_access_type %d if_id %d access_type %d\n",
 998                          train_cs_type, edge_comp, pattern, direction,
 999                          search_dir, control_element, result_type, pup_num,
1000                          pup_access_type, if_id, access_type));
1001                 return MV_FAIL;
1002         }
1003
1004         if (edge_comp == EDGE_FPF) {
1005                 start_search = HWS_LOW2HIGH;
1006                 end_search = HWS_HIGH2LOW;
1007                 edge_comp_used = EDGE_FP;
1008         } else {
1009                 start_search = search_dir;
1010                 end_search = search_dir;
1011                 edge_comp_used = edge_comp;
1012         }
1013
1014         for (search_dir_id = start_search; search_dir_id <= end_search;
1015              search_dir_id++) {
1016                 init_value_used = (search_dir_id == HWS_LOW2HIGH) ?
1017                         init_value_l2h : init_value_h2l;
1018                 DEBUG_TRAINING_IP_ENGINE(
1019                         DEBUG_LEVEL_TRACE,
1020                         ("dev_num %d, access_type %d, if_id %d, pup_access_type %d,pup_num %d, result_type %d, control_element %d search_dir_id %d, direction %d, interface_mask %d,init_value_used %d, num_iter %d, pattern %d, edge_comp_used %d, train_cs_type %d, cs_num %d\n",
1021                          dev_num, access_type, if_id, pup_access_type, pup_num,
1022                          result_type, control_element, search_dir_id,
1023                          direction, interface_mask, init_value_used, num_iter,
1024                          pattern, edge_comp_used, train_cs_type, cs_num));
1025
1026                 ddr3_tip_ip_training(dev_num, access_type, if_id,
1027                                      pup_access_type, pup_num, result_type,
1028                                      control_element, search_dir_id, direction,
1029                                      interface_mask, init_value_used, num_iter,
1030                                      pattern, edge_comp_used, train_cs_type,
1031                                      cs_num, train_status);
1032                 if (access_type == ACCESS_TYPE_MULTICAST) {
1033                         start_if = 0;
1034                         end_if = MAX_INTERFACE_NUM - 1;
1035                 } else {
1036                         start_if = if_id;
1037                         end_if = if_id;
1038                 }
1039
1040                 for (interface_num = start_if; interface_num <= end_if;
1041                      interface_num++) {
1042                         VALIDATE_IF_ACTIVE(tm->if_act_mask, interface_num);
1043                         cs_num = 0;
1044                         CHECK_STATUS(ddr3_tip_read_training_result
1045                                      (dev_num, interface_num, pup_access_type,
1046                                       pup_num, bit_num, search_dir_id,
1047                                       direction, result_type,
1048                                       TRAINING_LOAD_OPERATION_UNLOAD,
1049                                       train_cs_type, NULL, 0, cons_tap,
1050                                       0));
1051                 }
1052         }
1053
1054         return MV_OK;
1055 }
1056 /*
1057  * Training search & read result routine
1058  * This function implements the search algorithm
1059  * first it calls the function ddr3_tip_ip_training_wrapper_int which triggers the search from l2h and h2l
1060  * this function handles rx and tx search cases
1061  * in case of rx it only triggers the search (l2h and h2l)
1062  * in case of tx there are 3 optional algorithm phases:
1063  * phase 1:
1064  * it first triggers the search and handles the results as following (phase 1):
1065  * each bit, which defined by the search two edges (e1 or VW_L and e2 or VW_H), match on of cases:
1066  *  1.  BIT_LOW_UI      0 =< VW =< 31 in case of jitter use: VW_L <= 31, VW_H <= 31
1067  *  2.  BIT_HIGH_UI     32 =< VW =< 63 in case of jitter use: VW_L >= 32, VW_H >= 32
1068  *  3.  BIT_SPLIT_IN    VW_L <= 31 & VW_H >= 32
1069  *  4.  BIT_SPLIT_OUT*  VW_H < 32 &  VW_L > 32
1070  * note: the VW units is adll taps
1071  * phase 2:
1072  * only bit case BIT_SPLIT_OUT requires another search (phase 2) from the middle range in two directions h2l and l2h
1073  * because only this case is not locked by the search engine in the first search trigger (phase 1).
1074  * phase 3:
1075  * each subphy is categorized according to its bits definition.
1076  * the sub-phy cases are as follows:
1077  *  1.BYTE_NOT_DEFINED                  the byte has not yet been categorized
1078  *  2.BYTE_HOMOGENEOUS_LOW              0 =< VW =< 31
1079  *  3.BYTE_HOMOGENEOUS_HIGH             32 =< VW =< 63
1080  *  4.BYTE_HOMOGENEOUS_SPLIT_IN         VW_L <= 31 & VW_H >= 32
1081  *                                      or the center of all bits in the byte  =< 31
1082  *  5.BYTE_HOMOGENEOUS_SPLIT_OUT        VW_H < 32 &  VW_L > 32
1083  *  6.BYTE_SPLIT_OUT_MIX                at least one bits is in split out state and one bit is in other
1084  *                                      or the center of all bits in the byte => 32
1085  * after the two phases above a center valid window for each subphy is calculated accordingly:
1086  * center valid window = maximum center of all bits in the subphy - minimum center of all bits in the subphy.
1087  * now decisions are made in each subphy as following:
1088  * all subphys which are homogeneous remains as is
1089  * all subphys which are homogeneous low | homogeneous high and the subphy center valid window is less than 32
1090  *      mark this subphy as homogeneous split in.
1091  * now the bits in the bytes which are BYTE_SPLIT_OUT_MIX needed to be reorganized and handles as following
1092  * all bits which are BIT_LOW_UI will be added with 64 adll,
1093  * this will hopefully ensures that all the bits in the sub phy can be sampled by the dqs
1094  */
1095 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
1096         u32 if_id,
1097         enum hws_access_type pup_access_type,
1098         u32 pup_num,
1099         enum hws_training_result result_type,
1100         enum hws_control_element control_element,
1101         enum hws_search_dir search_dir,
1102         enum hws_dir direction, u32 interface_mask,
1103         u32 init_value_l2h, u32 init_value_h2l,
1104         u32 num_iter, enum hws_pattern pattern,
1105         enum hws_edge_compare edge_comp,
1106         enum hws_ddr_cs train_cs_type, u32 cs_num,
1107         enum hws_training_ip_stat *train_status)
1108 {
1109         u8 e1, e2;
1110         u32 bit_id, start_if, end_if, bit_end = 0;
1111         u32 *result[HWS_SEARCH_DIR_LIMIT] = { 0 };
1112         u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0);
1113         u8 bit_bit_mask[MAX_BUS_NUM] = { 0 }, bit_bit_mask_active = 0;
1114         u8 bit_state[MAX_BUS_NUM * BUS_WIDTH_IN_BITS] = {0};
1115         u8 h2l_adll_value[MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
1116         u8 l2h_adll_value[MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
1117         u8 center_subphy_adll_window[MAX_BUS_NUM];
1118         u8 min_center_subphy_adll[MAX_BUS_NUM];
1119         u8 max_center_subphy_adll[MAX_BUS_NUM];
1120         u32 *l2h_if_train_res = NULL;
1121         u32 *h2l_if_train_res = NULL;
1122         enum hws_search_dir search_dir_id;
1123         int status;
1124         u32 bit_lock_result;
1125
1126         u8 sybphy_id;
1127         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1128         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1129
1130         if (pup_num >= octets_per_if_num) {
1131                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
1132                         ("pup_num %d not valid\n", pup_num));
1133         }
1134
1135         if (if_id >= MAX_INTERFACE_NUM) {
1136                 DEBUG_TRAINING_IP_ENGINE(DEBUG_LEVEL_ERROR,
1137                         ("if_id %d not valid\n", if_id));
1138         }
1139
1140         status = ddr3_tip_ip_training_wrapper_int
1141                 (dev_num, access_type, if_id, pup_access_type, pup_num,
1142                 ALL_BITS_PER_PUP, result_type, control_element,
1143                 search_dir, direction, interface_mask, init_value_l2h,
1144                 init_value_h2l, num_iter, pattern, edge_comp,
1145                 train_cs_type, cs_num, train_status);
1146
1147         if (MV_OK != status)
1148                 return status;
1149
1150         if (access_type == ACCESS_TYPE_MULTICAST) {
1151                 start_if = 0;
1152                 end_if = MAX_INTERFACE_NUM - 1;
1153         } else {
1154                 start_if = if_id;
1155                 end_if = if_id;
1156         }
1157
1158         for (if_id = start_if; if_id <= end_if; if_id++) {
1159                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1160                 /* zero the database */
1161                 bit_bit_mask_active = 0;        /* clean the flag for level2 search */
1162                 memset(bit_state, 0, sizeof(bit_state));
1163                 /* phase 1 */
1164                 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) {
1165                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id);
1166                         if (result_type == RESULT_PER_BIT)
1167                                 bit_end = BUS_WIDTH_IN_BITS;
1168                         else
1169                                 bit_end = 0;
1170
1171                         /* zero the data base */
1172                         bit_bit_mask[sybphy_id] = 0;
1173                         byte_status[if_id][sybphy_id] = BYTE_NOT_DEFINED;
1174                         for (bit_id = 0; bit_id < bit_end; bit_id++) {
1175                                 h2l_adll_value[sybphy_id][bit_id] = 64;
1176                                 l2h_adll_value[sybphy_id][bit_id] = 0;
1177                                 for (search_dir_id = HWS_LOW2HIGH; search_dir_id <= HWS_HIGH2LOW;
1178                                         search_dir_id++) {
1179                                         status = ddr3_tip_read_training_result
1180                                                 (dev_num, if_id,
1181                                                         ACCESS_TYPE_UNICAST, sybphy_id, bit_id,
1182                                                         search_dir_id, direction, result_type,
1183                                                         TRAINING_LOAD_OPERATION_UNLOAD, CS_SINGLE,
1184                                                         &result[search_dir_id], 1, 0, 0);
1185
1186                                         if (MV_OK != status)
1187                                                 return status;
1188                                 }
1189
1190                                 e1 = GET_TAP_RESULT(result[HWS_LOW2HIGH][0], EDGE_1);
1191                                 e2 = GET_TAP_RESULT(result[HWS_HIGH2LOW][0], EDGE_1);
1192                                 DEBUG_TRAINING_IP_ENGINE
1193                                         (DEBUG_LEVEL_INFO,
1194                                          ("if_id %d sybphy_id %d bit %d l2h 0x%x (e1 0x%x) h2l 0x%x (e2 0x%x)\n",
1195                                          if_id, sybphy_id, bit_id, result[HWS_LOW2HIGH][0], e1,
1196                                          result[HWS_HIGH2LOW][0], e2));
1197                                 bit_lock_result =
1198                                         (GET_LOCK_RESULT(result[HWS_LOW2HIGH][0]) &&
1199                                                 GET_LOCK_RESULT(result[HWS_HIGH2LOW][0]));
1200
1201                                 if (bit_lock_result) {
1202                                         /* in case of read operation set the byte status as homogeneous low */
1203                                         if (direction == OPER_READ) {
1204                                                 byte_status[if_id][sybphy_id] |= BYTE_HOMOGENEOUS_LOW;
1205                                         } else if ((e2 - e1) > 32) { /* oper_write */
1206                                                 /* split out */
1207                                                 bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =
1208                                                         BIT_SPLIT_OUT;
1209                                                 byte_status[if_id][sybphy_id] |= BYTE_HOMOGENEOUS_SPLIT_OUT;
1210                                                 /* mark problem bits */
1211                                                 bit_bit_mask[sybphy_id] |= (1 << bit_id);
1212                                                 bit_bit_mask_active = 1;
1213                                                 DEBUG_TRAINING_IP_ENGINE
1214                                                         (DEBUG_LEVEL_TRACE,
1215                                                          ("if_id %d sybphy_id %d bit %d BIT_SPLIT_OUT\n",
1216                                                          if_id, sybphy_id, bit_id));
1217                                         } else {
1218                                                 /* low ui */
1219                                                 if (e1 <= 31 && e2 <= 31) {
1220                                                         bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =
1221                                                                 BIT_LOW_UI;
1222                                                         byte_status[if_id][sybphy_id] |= BYTE_HOMOGENEOUS_LOW;
1223                                                         l2h_adll_value[sybphy_id][bit_id] = e1;
1224                                                         h2l_adll_value[sybphy_id][bit_id] = e2;
1225                                                         DEBUG_TRAINING_IP_ENGINE
1226                                                                 (DEBUG_LEVEL_TRACE,
1227                                                                  ("if_id %d sybphy_id %d bit %d BIT_LOW_UI\n",
1228                                                                  if_id, sybphy_id, bit_id));
1229                                                 }
1230                                                         /* high ui */
1231                                                 if (e1 >= 32 && e2 >= 32) {
1232                                                         bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =
1233                                                                 BIT_HIGH_UI;
1234                                                         byte_status[if_id][sybphy_id] |= BYTE_HOMOGENEOUS_HIGH;
1235                                                         l2h_adll_value[sybphy_id][bit_id] = e1;
1236                                                         h2l_adll_value[sybphy_id][bit_id] = e2;
1237                                                         DEBUG_TRAINING_IP_ENGINE
1238                                                                 (DEBUG_LEVEL_TRACE,
1239                                                                  ("if_id %d sybphy_id %d bit %d BIT_HIGH_UI\n",
1240                                                                  if_id, sybphy_id, bit_id));
1241                                                 }
1242                                                 /* split in */
1243                                                 if (e1 <= 31 && e2 >= 32) {
1244                                                         bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =
1245                                                                 BIT_SPLIT_IN;
1246                                                         byte_status[if_id][sybphy_id] |=
1247                                                                 BYTE_HOMOGENEOUS_SPLIT_IN;
1248                                                         l2h_adll_value[sybphy_id][bit_id] = e1;
1249                                                         h2l_adll_value[sybphy_id][bit_id] = e2;
1250                                                         DEBUG_TRAINING_IP_ENGINE
1251                                                                 (DEBUG_LEVEL_TRACE,
1252                                                                  ("if_id %d sybphy_id %d bit %d BIT_SPLIT_IN\n",
1253                                                                  if_id, sybphy_id, bit_id));
1254                                                 }
1255                                         }
1256                                 } else {
1257                                         DEBUG_TRAINING_IP_ENGINE
1258                                                 (DEBUG_LEVEL_INFO,
1259                                                  ("if_id %d sybphy_id %d bit %d l2h 0x%x (e1 0x%x)"
1260                                                  "h2l 0x%x (e2 0x%x): bit cannot be categorized\n",
1261                                                  if_id, sybphy_id, bit_id, result[HWS_LOW2HIGH][0], e1,
1262                                                  result[HWS_HIGH2LOW][0], e2));
1263                                         /* mark the byte as not defined */
1264                                         byte_status[if_id][sybphy_id] = BYTE_NOT_DEFINED;
1265                                         break; /* continue to next pup - no reason to analyze this byte */
1266                                 }
1267                         } /* for all bits */
1268                 } /* for all PUPs */
1269
1270                 /* phase 2 will occur only in write operation */
1271                 if (bit_bit_mask_active != 0) {
1272                         l2h_if_train_res = ddr3_tip_get_buf_ptr(dev_num, HWS_LOW2HIGH, result_type, if_id);
1273                         h2l_if_train_res = ddr3_tip_get_buf_ptr(dev_num, HWS_HIGH2LOW, result_type, if_id);
1274                         /* search from middle to end */
1275                         ddr3_tip_ip_training
1276                                 (dev_num, ACCESS_TYPE_UNICAST,
1277                                  if_id, ACCESS_TYPE_MULTICAST,
1278                                  PARAM_NOT_CARE, result_type,
1279                                  control_element, HWS_LOW2HIGH,
1280                                  direction, interface_mask,
1281                                  num_iter / 2, num_iter / 2,
1282                                  pattern, EDGE_FP, train_cs_type,
1283                                  cs_num, train_status);
1284
1285                         for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) {
1286                                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id);
1287                                 if (byte_status[if_id][sybphy_id] != BYTE_NOT_DEFINED) {
1288                                         if (bit_bit_mask[sybphy_id] == 0)
1289                                                 continue; /* this byte bits have no split out state */
1290
1291                                         for (bit_id = 0; bit_id < bit_end; bit_id++) {
1292                                                 if ((bit_bit_mask[sybphy_id] & (1 << bit_id)) == 0)
1293                                                         continue; /* this bit is non split goto next bit */
1294
1295                                                 /* enter the result to the data base */
1296                                                 status = ddr3_tip_read_training_result
1297                                                         (dev_num, if_id, ACCESS_TYPE_UNICAST, sybphy_id,
1298                                                          bit_id, HWS_LOW2HIGH, direction, result_type,
1299                                                          TRAINING_LOAD_OPERATION_UNLOAD, CS_SINGLE,
1300                                                          &l2h_if_train_res, 0, 0, 1);
1301
1302                                                 if (MV_OK != status)
1303                                                         return status;
1304
1305                                                 l2h_adll_value[sybphy_id][bit_id] =
1306                                                         l2h_if_train_res[sybphy_id *
1307                                                         BUS_WIDTH_IN_BITS + bit_id] & PUP_RESULT_EDGE_1_MASK;
1308                                         }
1309                                 }
1310                         }
1311                         /* Search from middle to start */
1312                         ddr3_tip_ip_training
1313                                 (dev_num, ACCESS_TYPE_UNICAST,
1314                                  if_id, ACCESS_TYPE_MULTICAST,
1315                                  PARAM_NOT_CARE, result_type,
1316                                  control_element, HWS_HIGH2LOW,
1317                                  direction, interface_mask,
1318                                  num_iter / 2, num_iter / 2,
1319                                  pattern, EDGE_FP, train_cs_type,
1320                                  cs_num, train_status);
1321
1322                         for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) {
1323                                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id);
1324                                 if (byte_status[if_id][sybphy_id] != BYTE_NOT_DEFINED) {
1325                                         if (bit_bit_mask[sybphy_id] == 0)
1326                                                 continue;
1327
1328                                         for (bit_id = 0; bit_id < bit_end; bit_id++) {
1329                                                 if ((bit_bit_mask[sybphy_id] & (1 << bit_id)) == 0)
1330                                                         continue;
1331
1332                                                 status = ddr3_tip_read_training_result
1333                                                         (dev_num, if_id, ACCESS_TYPE_UNICAST, sybphy_id,
1334                                                          bit_id, HWS_HIGH2LOW, direction, result_type,
1335                                                          TRAINING_LOAD_OPERATION_UNLOAD, CS_SINGLE,
1336                                                          &h2l_if_train_res, 0, cons_tap, 1);
1337
1338                                                 if (MV_OK != status)
1339                                                         return status;
1340
1341                                                 h2l_adll_value[sybphy_id][bit_id] =
1342                                                         h2l_if_train_res[sybphy_id *
1343                                                         BUS_WIDTH_IN_BITS + bit_id] & PUP_RESULT_EDGE_1_MASK;
1344                                         }
1345                                 }
1346                         }
1347                 } /* end if bit_bit_mask_active */
1348                 /*
1349                         * phase 3 will occur only in write operation
1350                         * find the maximum and the minimum center of each subphy
1351                         */
1352                 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) {
1353                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id);
1354
1355                         if ((byte_status[if_id][sybphy_id] != BYTE_NOT_DEFINED) && (direction == OPER_WRITE)) {
1356                                 /* clear the arrays and parameters */
1357                                 center_subphy_adll_window[sybphy_id] = 0;
1358                                 max_center_subphy_adll[sybphy_id] = 0;
1359                                 min_center_subphy_adll[sybphy_id] = 64;
1360                                 /* find the max and min center adll value in the current subphy */
1361                                 for (bit_id = 0; bit_id < bit_end; bit_id++) {
1362                                         /* debug print all the bit edges after alignment */
1363                                         DEBUG_TRAINING_IP_ENGINE
1364                                                 (DEBUG_LEVEL_TRACE,
1365                                                  ("if_id %d sybphy_id %d bit %d l2h %d h2l %d\n",
1366                                                  if_id, sybphy_id, bit_id, l2h_adll_value[sybphy_id][bit_id],
1367                                                  h2l_adll_value[sybphy_id][bit_id]));
1368
1369                                         if (((l2h_adll_value[sybphy_id][bit_id] +
1370                                               h2l_adll_value[sybphy_id][bit_id]) / 2) >
1371                                               max_center_subphy_adll[sybphy_id])
1372                                                 max_center_subphy_adll[sybphy_id] =
1373                                                 (l2h_adll_value[sybphy_id][bit_id] +
1374                                                  h2l_adll_value[sybphy_id][bit_id]) / 2;
1375                                         if (((l2h_adll_value[sybphy_id][bit_id] +
1376                                               h2l_adll_value[sybphy_id][bit_id]) / 2) <
1377                                               min_center_subphy_adll[sybphy_id])
1378                                                 min_center_subphy_adll[sybphy_id] =
1379                                                 (l2h_adll_value[sybphy_id][bit_id] +
1380                                                  h2l_adll_value[sybphy_id][bit_id]) / 2;
1381                                 }
1382
1383                                 /* calculate the center of the current subphy */
1384                                 center_subphy_adll_window[sybphy_id] =
1385                                         max_center_subphy_adll[sybphy_id] -
1386                                         min_center_subphy_adll[sybphy_id];
1387                                 DEBUG_TRAINING_IP_ENGINE
1388                                         (DEBUG_LEVEL_TRACE,
1389                                          ("if_id %d sybphy_id %d min center %d max center %d center %d\n",
1390                                          if_id, sybphy_id, min_center_subphy_adll[sybphy_id],
1391                                          max_center_subphy_adll[sybphy_id],
1392                                          center_subphy_adll_window[sybphy_id]));
1393                         }
1394                 }
1395                 /*
1396                         * check byte state and fix bits state if needed
1397                         * in case the level 1 and 2 above subphy results are
1398                         * homogeneous continue to the next subphy
1399                         */
1400                 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) {
1401                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id);
1402                         if ((byte_status[if_id][sybphy_id] == BYTE_HOMOGENEOUS_LOW) ||
1403                             (byte_status[if_id][sybphy_id] == BYTE_HOMOGENEOUS_HIGH) ||
1404                             (byte_status[if_id][sybphy_id] == BYTE_HOMOGENEOUS_SPLIT_IN) ||
1405                             (byte_status[if_id][sybphy_id] == BYTE_HOMOGENEOUS_SPLIT_OUT) ||
1406                             (byte_status[if_id][sybphy_id] == BYTE_NOT_DEFINED))
1407                         continue;
1408
1409                         /*
1410                          * in case all of the bits in the current subphy are
1411                          * less than 32 which will find alignment in the subphy bits
1412                          * mark this subphy as homogeneous split in
1413                         */
1414                         if (center_subphy_adll_window[sybphy_id] <= 31)
1415                                 byte_status[if_id][sybphy_id] = BYTE_HOMOGENEOUS_SPLIT_IN;
1416
1417                         /*
1418                                 * in case the current byte is split_out and the center is bigger than 31
1419                                 * the byte can be aligned. in this case add 64 to the the low ui bits aligning it
1420                                 * to the other ui bits
1421                                 */
1422                         if (center_subphy_adll_window[sybphy_id] >= 32) {
1423                                 byte_status[if_id][sybphy_id] = BYTE_SPLIT_OUT_MIX;
1424
1425                                 DEBUG_TRAINING_IP_ENGINE
1426                                         (DEBUG_LEVEL_TRACE,
1427                                          ("if_id %d sybphy_id %d byte state 0x%x\n",
1428                                          if_id, sybphy_id, byte_status[if_id][sybphy_id]));
1429                                 for (bit_id = 0; bit_id < bit_end; bit_id++) {
1430                                         if (bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] == BIT_LOW_UI) {
1431                                                 l2h_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] += 64;
1432                                                 h2l_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] += 64;
1433                                         }
1434                                         DEBUG_TRAINING_IP_ENGINE
1435                                                 (DEBUG_LEVEL_TRACE,
1436                                                  ("if_id %d sybphy_id %d bit_id %d added 64 adlls\n",
1437                                                  if_id, sybphy_id, bit_id));
1438                                 }
1439                         }
1440                 }
1441         } /* for all interfaces */
1442
1443         return MV_OK;
1444 }
1445
1446 u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id)
1447 {
1448         return byte_status[if_id][subphy_id];
1449 }
1450
1451 void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data)
1452 {
1453         byte_status[if_id][subphy_id] = byte_status_data;
1454 }
1455
1456 /*
1457  * Load phy values
1458  */
1459 int ddr3_tip_load_phy_values(int b_load)
1460 {
1461         u32 bus_cnt = 0, if_id, dev_num = 0;
1462         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1463         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1464
1465         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1466                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1467                 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
1468                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
1469                         if (b_load == 1) {
1470                                 CHECK_STATUS(ddr3_tip_bus_read
1471                                              (dev_num, if_id,
1472                                               ACCESS_TYPE_UNICAST, bus_cnt,
1473                                               DDR_PHY_DATA,
1474                                               CTX_PHY_REG(effective_cs),
1475                                               &phy_reg_bk[if_id][bus_cnt]
1476                                               [0]));
1477                                 CHECK_STATUS(ddr3_tip_bus_read
1478                                              (dev_num, if_id,
1479                                               ACCESS_TYPE_UNICAST, bus_cnt,
1480                                               DDR_PHY_DATA,
1481                                               RL_PHY_REG(effective_cs),
1482                                               &phy_reg_bk[if_id][bus_cnt]
1483                                               [1]));
1484                                 CHECK_STATUS(ddr3_tip_bus_read
1485                                              (dev_num, if_id,
1486                                               ACCESS_TYPE_UNICAST, bus_cnt,
1487                                               DDR_PHY_DATA,
1488                                               CRX_PHY_REG(effective_cs),
1489                                               &phy_reg_bk[if_id][bus_cnt]
1490                                               [2]));
1491                         } else {
1492                                 CHECK_STATUS(ddr3_tip_bus_write
1493                                              (dev_num, ACCESS_TYPE_UNICAST,
1494                                               if_id, ACCESS_TYPE_UNICAST,
1495                                               bus_cnt, DDR_PHY_DATA,
1496                                               CTX_PHY_REG(effective_cs),
1497                                               phy_reg_bk[if_id][bus_cnt]
1498                                               [0]));
1499                                 CHECK_STATUS(ddr3_tip_bus_write
1500                                              (dev_num, ACCESS_TYPE_UNICAST,
1501                                               if_id, ACCESS_TYPE_UNICAST,
1502                                               bus_cnt, DDR_PHY_DATA,
1503                                               RL_PHY_REG(effective_cs),
1504                                               phy_reg_bk[if_id][bus_cnt]
1505                                               [1]));
1506                                 CHECK_STATUS(ddr3_tip_bus_write
1507                                              (dev_num, ACCESS_TYPE_UNICAST,
1508                                               if_id, ACCESS_TYPE_UNICAST,
1509                                               bus_cnt, DDR_PHY_DATA,
1510                                               CRX_PHY_REG(effective_cs),
1511                                               phy_reg_bk[if_id][bus_cnt]
1512                                               [2]));
1513                         }
1514                 }
1515         }
1516
1517         return MV_OK;
1518 }
1519
1520 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
1521                               enum hws_search_dir search_dir,
1522                               enum hws_dir direction,
1523                               enum hws_edge_compare edge,
1524                               u32 init_val1, u32 init_val2,
1525                               u32 num_of_iterations,
1526                               u32 start_pattern, u32 end_pattern)
1527 {
1528         u32 pattern, if_id, pup_id;
1529         enum hws_training_ip_stat train_status[MAX_INTERFACE_NUM];
1530         u32 *res = NULL;
1531         u32 search_state = 0;
1532         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1533         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1534
1535         ddr3_tip_load_phy_values(1);
1536
1537         for (pattern = start_pattern; pattern <= end_pattern; pattern++) {
1538                 for (search_state = 0; search_state < HWS_SEARCH_DIR_LIMIT;
1539                      search_state++) {
1540                         ddr3_tip_ip_training_wrapper(dev_num,
1541                                                      ACCESS_TYPE_MULTICAST, 0,
1542                                                      ACCESS_TYPE_MULTICAST, 0,
1543                                                      result_type,
1544                                                      HWS_CONTROL_ELEMENT_ADLL,
1545                                                      search_dir, direction,
1546                                                      0xfff, init_val1,
1547                                                      init_val2,
1548                                                      num_of_iterations, pattern,
1549                                                      edge, CS_SINGLE,
1550                                                      PARAM_NOT_CARE,
1551                                                      train_status);
1552
1553                         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1;
1554                              if_id++) {
1555                                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1556                                 for (pup_id = 0; pup_id <
1557                                              octets_per_if_num;
1558                                      pup_id++) {
1559                                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask,
1560                                                         pup_id);
1561                                         CHECK_STATUS
1562                                                 (ddr3_tip_read_training_result
1563                                                  (dev_num, if_id,
1564                                                   ACCESS_TYPE_UNICAST, pup_id,
1565                                                   ALL_BITS_PER_PUP,
1566                                                   search_state,
1567                                                   direction, result_type,
1568                                                   TRAINING_LOAD_OPERATION_UNLOAD,
1569                                                   CS_SINGLE, &res, 1, 0,
1570                                                   0));
1571                                         if (result_type == RESULT_PER_BYTE) {
1572                                                 DEBUG_TRAINING_IP_ENGINE
1573                                                         (DEBUG_LEVEL_INFO,
1574                                                          ("search_state %d if_id %d pup_id %d 0x%x\n",
1575                                                           search_state, if_id,
1576                                                           pup_id, res[0]));
1577                                         } else {
1578                                                 DEBUG_TRAINING_IP_ENGINE
1579                                                         (DEBUG_LEVEL_INFO,
1580                                                          ("search_state %d if_id %d pup_id %d 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1581                                                           search_state, if_id,
1582                                                           pup_id, res[0],
1583                                                           res[1], res[2],
1584                                                           res[3], res[4],
1585                                                           res[5], res[6],
1586                                                           res[7]));
1587                                         }
1588                                 }
1589                         }       /* interface */
1590                 }               /* search */
1591         }                       /* pattern */
1592
1593         ddr3_tip_load_phy_values(0);
1594
1595         return MV_OK;
1596 }
1597
1598 int mv_ddr_pattern_start_addr_set(struct pattern_info *pattern_tbl, enum hws_pattern pattern, u32 addr)
1599 {
1600         pattern_tbl[pattern].start_addr = addr;
1601
1602         return 0;
1603 }
1604
1605 struct pattern_info *ddr3_tip_get_pattern_table()
1606 {
1607         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1608
1609         if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask))
1610                 return pattern_table_64;
1611         else if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0)
1612                 return pattern_table_32;
1613         else
1614                 return pattern_table_16;
1615 }
1616
1617 u16 *ddr3_tip_get_mask_results_dq_reg()
1618 {
1619 #if MAX_BUS_NUM == 5
1620         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1621
1622         if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
1623                 return mask_results_dq_reg_map_pup3_ecc;
1624         else
1625 #endif
1626                 return mask_results_dq_reg_map;
1627 }
1628
1629 u16 *ddr3_tip_get_mask_results_pup_reg_map()
1630 {
1631 #if MAX_BUS_NUM == 5
1632         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1633
1634         if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
1635                 return mask_results_pup_reg_map_pup3_ecc;
1636         else
1637 #endif
1638                 return mask_results_pup_reg_map;
1639 }
1640
1641 /* load expected dm pattern to odpg */
1642 #define LOW_NIBBLE_BYTE_MASK    0xf
1643 #define HIGH_NIBBLE_BYTE_MASK   0xf0
1644 int mv_ddr_load_dm_pattern_to_odpg(enum hws_access_type access_type, enum hws_pattern pattern,
1645                                    enum dm_direction dm_dir)
1646 {
1647         struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
1648         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1649         u32 pattern_len = 0;
1650         u32 data_low, data_high;
1651         u8 dm_data;
1652
1653         for (pattern_len = 0;
1654              pattern_len < pattern_table[pattern].pattern_len;
1655              pattern_len++) {
1656                 if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)) {
1657                         data_low = pattern_table_get_word(0, pattern, (u8)pattern_len);
1658                         data_high = data_low;
1659                 } else {
1660                         data_low = pattern_table_get_word(0, pattern, (u8)(pattern_len * 2));
1661                         data_high = pattern_table_get_word(0, pattern, (u8)(pattern_len * 2 + 1));
1662                 }
1663
1664                 /* odpg mbus dm definition is opposite to ddr4 protocol */
1665                 if (dm_dir == DM_DIR_INVERSE)
1666                         dm_data = ~((data_low & LOW_NIBBLE_BYTE_MASK) | (data_high & HIGH_NIBBLE_BYTE_MASK));
1667                 else
1668                         dm_data = (data_low & LOW_NIBBLE_BYTE_MASK) | (data_high & HIGH_NIBBLE_BYTE_MASK);
1669
1670                 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_DATA_LOW_REG, data_low, MASK_ALL_BITS);
1671                 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_DATA_HIGH_REG, data_high, MASK_ALL_BITS);
1672                 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_ADDR_REG,
1673                                   pattern_len | ((dm_data & ODPG_DATA_WR_DATA_MASK) << ODPG_DATA_WR_DATA_OFFS),
1674                                   MASK_ALL_BITS);
1675         }
1676
1677         return MV_OK;
1678 }