drivers/ddr/fsl/util.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #ifdef CONFIG_PPC
   8 #include <asm/fsl_law.h>
   9 #endif
  10 #include <div64.h>
  11 #include <linux/delay.h>
  12
  13 #include <fsl_ddr.h>
  14 #include <fsl_immap.h>
  15 #include <log.h>
  16 #include <asm/io.h>
  17 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  18         defined(CONFIG_ARM)
  19 #include <asm/arch/clock.h>
  20 #endif
  21
  22 /* To avoid 64-bit full-divides, we factor this here */
  23 #define ULL_2E12 2000000000000ULL
  24 #define UL_5POW12 244140625UL
  25 #define UL_2POW13 (1UL << 13)
  26
  27 #define ULL_8FS 0xFFFFFFFFULL
  28
  29 u32 fsl_ddr_get_version(unsigned int ctrl_num)
  30 {
  31         struct ccsr_ddr __iomem *ddr;
  32         u32 ver_major_minor_errata;
  33
  34         switch (ctrl_num) {
  35         case 0:
  36                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  37                 break;
  38 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  39         case 1:
  40                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  41                 break;
  42 #endif
  43 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  44         case 2:
  45                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  46                 break;
  47 #endif
  48 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  49         case 3:
  50                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  51                 break;
  52 #endif
  53         default:
  54                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  55                 return 0;
  56         }
  57         ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
  58         ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
  59
  60         return ver_major_minor_errata;
  61 }
  62
  63 /*
  64  * Round up mclk_ps to nearest 1 ps in memory controller code
  65  * if the error is 0.5ps or more.
  66  *
  67  * If an imprecise data rate is too high due to rounding error
  68  * propagation, compute a suitably rounded mclk_ps to compute
  69  * a working memory controller configuration.
  70  */
  71 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
  72 {
  73         unsigned int data_rate = get_ddr_freq(ctrl_num);
  74         unsigned int result;
  75
  76         /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
  77         unsigned long long rem, mclk_ps = ULL_2E12;
  78
  79         /* Now perform the big divide, the result fits in 32-bits */
  80         rem = do_div(mclk_ps, data_rate);
  81         result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
  82
  83         return result;
  84 }
  85
  86 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  87 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
  88 {
  89         unsigned long long clks, clks_rem;
  90         unsigned long data_rate = get_ddr_freq(ctrl_num);
  91
  92         /* Short circuit for zero picos */
  93         if (!picos)
  94                 return 0;
  95
  96         /* First multiply the time by the data rate (32x32 => 64) */
  97         clks = picos * (unsigned long long)data_rate;
  98         /*
  99          * Now divide by 5^12 and track the 32-bit remainder, then divide
 100          * by 2*(2^12) using shifts (and updating the remainder).
 101          */
 102         clks_rem = do_div(clks, UL_5POW12);
 103         clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
 104         clks >>= 13;
 105
 106         /* If we had a remainder greater than the 1ps error, then round up */
 107         if (clks_rem > data_rate)
 108                 clks++;
 109
 110         /* Clamp to the maximum representable value */
 111         if (clks > ULL_8FS)
 112                 clks = ULL_8FS;
 113         return (unsigned int) clks;
 114 }
 115
 116 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
 117 {
 118         return get_memory_clk_period_ps(ctrl_num) * mclk;
 119 }
 120
 121 #ifdef CONFIG_PPC
 122 void
 123 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 124                            unsigned int law_memctl,
 125                            unsigned int ctrl_num)
 126 {
 127         unsigned long long base = memctl_common_params->base_address;
 128         unsigned long long size = memctl_common_params->total_mem;
 129
 130         /*
 131          * If no DIMMs on this controller, do not proceed any further.
 132          */
 133         if (!memctl_common_params->ndimms_present) {
 134                 return;
 135         }
 136
 137 #if !defined(CONFIG_PHYS_64BIT)
 138         if (base >= CONFIG_MAX_MEM_MAPPED)
 139                 return;
 140         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
 141                 size = CONFIG_MAX_MEM_MAPPED - base;
 142 #endif
 143         if (set_ddr_laws(base, size, law_memctl) < 0) {
 144                 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
 145                         law_memctl);
 146                 return ;
 147         }
 148         debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
 149                 base, size, law_memctl);
 150 }
 151
 152 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 153 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 154                          unsigned int memctl_interleaved,
 155                          unsigned int ctrl_num);
 156 #endif
 157
 158 void fsl_ddr_set_intl3r(const unsigned int granule_size)
 159 {
 160 #ifdef CONFIG_E6500
 161         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 162         *mcintl3r = 0x80000000 | (granule_size & 0x1f);
 163         debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
 164 #endif
 165 }
 166
 167 u32 fsl_ddr_get_intl3r(void)
 168 {
 169         u32 val = 0;
 170 #ifdef CONFIG_E6500
 171         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 172         val = *mcintl3r;
 173 #endif
 174         return val;
 175 }
 176
 177 void print_ddr_info(unsigned int start_ctrl)
 178 {
 179         struct ccsr_ddr __iomem *ddr =
 180                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 181
 182 #if     defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
 183         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 184 #endif
 185 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 186         uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
 187 #endif
 188         uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 189         int cas_lat;
 190
 191 #if CONFIG_SYS_NUM_DDR_CTLRS >= 2
 192         if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 193             (start_ctrl == 1)) {
 194                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
 195                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 196         }
 197 #endif
 198 #if CONFIG_SYS_NUM_DDR_CTLRS >= 3
 199         if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 200             (start_ctrl == 2)) {
 201                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
 202                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 203         }
 204 #endif
 205
 206         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
 207                 puts(" (DDR not enabled)\n");
 208                 return;
 209         }
 210
 211         puts(" (DDR");
 212         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 213                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 214         case SDRAM_TYPE_DDR1:
 215                 puts("1");
 216                 break;
 217         case SDRAM_TYPE_DDR2:
 218                 puts("2");
 219                 break;
 220         case SDRAM_TYPE_DDR3:
 221                 puts("3");
 222                 break;
 223         case SDRAM_TYPE_DDR4:
 224                 puts("4");
 225                 break;
 226         default:
 227                 puts("?");
 228                 break;
 229         }
 230
 231         if (sdram_cfg & SDRAM_CFG_32_BE)
 232                 puts(", 32-bit");
 233         else if (sdram_cfg & SDRAM_CFG_16_BE)
 234                 puts(", 16-bit");
 235         else
 236                 puts(", 64-bit");
 237
 238         /* Calculate CAS latency based on timing cfg values */
 239         cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
 240         if (fsl_ddr_get_version(0) <= 0x40400)
 241                 cas_lat += 1;
 242         else
 243                 cas_lat += 2;
 244         cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
 245         printf(", CL=%d", cas_lat >> 1);
 246         if (cas_lat & 0x1)
 247                 puts(".5");
 248
 249         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 250                 puts(", ECC on)");
 251         else
 252                 puts(", ECC off)");
 253
 254 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
 255 #ifdef CONFIG_E6500
 256         if (*mcintl3r & 0x80000000) {
 257                 puts("\n");
 258                 puts("       DDR Controller Interleaving Mode: ");
 259                 switch (*mcintl3r & 0x1f) {
 260                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 261                         puts("3-way 1KB");
 262                         break;
 263                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 264                         puts("3-way 4KB");
 265                         break;
 266                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 267                         puts("3-way 8KB");
 268                         break;
 269                 default:
 270                         puts("3-way UNKNOWN");
 271                         break;
 272                 }
 273         }
 274 #endif
 275 #endif
 276 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 277         if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
 278                 puts("\n");
 279                 puts("       DDR Controller Interleaving Mode: ");
 280
 281                 switch ((cs0_config >> 24) & 0xf) {
 282                 case FSL_DDR_256B_INTERLEAVING:
 283                         puts("256B");
 284                         break;
 285                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 286                         puts("cache line");
 287                         break;
 288                 case FSL_DDR_PAGE_INTERLEAVING:
 289                         puts("page");
 290                         break;
 291                 case FSL_DDR_BANK_INTERLEAVING:
 292                         puts("bank");
 293                         break;
 294                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 295                         puts("super-bank");
 296                         break;
 297                 default:
 298                         puts("invalid");
 299                         break;
 300                 }
 301         }
 302 #endif
 303
 304         if ((sdram_cfg >> 8) & 0x7f) {
 305                 puts("\n");
 306                 puts("       DDR Chip-Select Interleaving Mode: ");
 307                 switch(sdram_cfg >> 8 & 0x7f) {
 308                 case FSL_DDR_CS0_CS1_CS2_CS3:
 309                         puts("CS0+CS1+CS2+CS3");
 310                         break;
 311                 case FSL_DDR_CS0_CS1:
 312                         puts("CS0+CS1");
 313                         break;
 314                 case FSL_DDR_CS2_CS3:
 315                         puts("CS2+CS3");
 316                         break;
 317                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 318                         puts("CS0+CS1 and CS2+CS3");
 319                         break;
 320                 default:
 321                         puts("invalid");
 322                         break;
 323                 }
 324         }
 325 }
 326
 327 void __weak detail_board_ddr_info(void)
 328 {
 329         print_ddr_info(0);
 330 }
 331
 332 void board_add_ram_info(int use_default)
 333 {
 334         detail_board_ddr_info();
 335 }
 336
 337 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 338 #define DDRC_DEBUG20_INIT_DONE  0x80000000
 339 #define DDRC_DEBUG2_RF          0x00000040
 340 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 341                                  unsigned int last_ctrl)
 342 {
 343         unsigned int i;
 344         u32 ddrc_debug20;
 345         u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
 346         u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
 347         struct ccsr_ddr __iomem *ddr;
 348
 349         for (i = first_ctrl; i <= last_ctrl; i++) {
 350                 switch (i) {
 351                 case 0:
 352                         ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 353                         break;
 354 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 355                 case 1:
 356                         ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
 357                         break;
 358 #endif
 359 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
 360                 case 2:
 361                         ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
 362                         break;
 363 #endif
 364 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
 365                 case 3:
 366                         ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 367                         break;
 368 #endif
 369                 default:
 370                         printf("%s unexpected ctrl = %u\n", __func__, i);
 371                         return;
 372                 }
 373                 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
 374                 ddrc_debug2_p[i] = &ddr->debug[1];
 375                 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
 376                         /* keep polling until DDRC init is done */
 377                         udelay(100);
 378                         ddrc_debug20 = ddr_in32(&ddr->debug[19]);
 379                 }
 380                 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
 381         }
 382         /*
 383          * Sync refresh
 384          * This is put together to make sure the refresh reqeusts are sent
 385          * closely to each other.
 386          */
 387         for (i = first_ctrl; i <= last_ctrl; i++)
 388                 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
 389 }
 390 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
 391
 392 void remove_unused_controllers(fsl_ddr_info_t *info)
 393 {
 394 #ifdef CONFIG_SYS_FSL_HAS_CCN504
 395         int i;
 396         u64 nodeid;
 397         void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
 398         bool ddr0_used = false;
 399         bool ddr1_used = false;
 400
 401         for (i = 0; i < 8; i++) {
 402                 nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
 403                 if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
 404                         ddr0_used = true;
 405                 } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
 406                         ddr1_used = true;
 407                 } else {
 408                         printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
 409                                nodeid);
 410                 }
 411                 hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
 412         }
 413         if (!ddr0_used && !ddr1_used) {
 414                 printf("Invalid configuration in HN-F SAM control\n");
 415                 return;
 416         }
 417
 418         if (!ddr0_used && info->first_ctrl == 0) {
 419                 info->first_ctrl = 1;
 420                 info->num_ctrls = 1;
 421                 debug("First DDR controller disabled\n");
 422                 return;
 423         }
 424
 425         if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
 426                 info->num_ctrls = 1;
 427                 debug("Second DDR controller disabled\n");
 428         }
 429 #endif
 430 }