drivers/ddr/fsl/util.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #ifdef CONFIG_PPC
  11 #include <asm/fsl_law.h>
  12 #endif
  13 #include <div64.h>
  14
  15 #include <fsl_ddr.h>
  16 #include <fsl_immap.h>
  17 #include <asm/io.h>
  18
  19 /* To avoid 64-bit full-divides, we factor this here */
  20 #define ULL_2E12 2000000000000ULL
  21 #define UL_5POW12 244140625UL
  22 #define UL_2POW13 (1UL << 13)
  23
  24 #define ULL_8FS 0xFFFFFFFFULL
  25
  26 u32 fsl_ddr_get_version(unsigned int ctrl_num)
  27 {
  28         struct ccsr_ddr __iomem *ddr;
  29         u32 ver_major_minor_errata;
  30
  31         switch (ctrl_num) {
  32         case 0:
  33                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  34                 break;
  35 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  36         case 1:
  37                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  38                 break;
  39 #endif
  40 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  41         case 2:
  42                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  43                 break;
  44 #endif
  45 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  46         case 3:
  47                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  48                 break;
  49 #endif
  50         default:
  51                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  52                 return 0;
  53         }
  54         ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
  55         ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
  56
  57         return ver_major_minor_errata;
  58 }
  59
  60 /*
  61  * Round up mclk_ps to nearest 1 ps in memory controller code
  62  * if the error is 0.5ps or more.
  63  *
  64  * If an imprecise data rate is too high due to rounding error
  65  * propagation, compute a suitably rounded mclk_ps to compute
  66  * a working memory controller configuration.
  67  */
  68 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
  69 {
  70         unsigned int data_rate = get_ddr_freq(ctrl_num);
  71         unsigned int result;
  72
  73         /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
  74         unsigned long long rem, mclk_ps = ULL_2E12;
  75
  76         /* Now perform the big divide, the result fits in 32-bits */
  77         rem = do_div(mclk_ps, data_rate);
  78         result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
  79
  80         return result;
  81 }
  82
  83 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  84 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
  85 {
  86         unsigned long long clks, clks_rem;
  87         unsigned long data_rate = get_ddr_freq(ctrl_num);
  88
  89         /* Short circuit for zero picos */
  90         if (!picos)
  91                 return 0;
  92
  93         /* First multiply the time by the data rate (32x32 => 64) */
  94         clks = picos * (unsigned long long)data_rate;
  95         /*
  96          * Now divide by 5^12 and track the 32-bit remainder, then divide
  97          * by 2*(2^12) using shifts (and updating the remainder).
  98          */
  99         clks_rem = do_div(clks, UL_5POW12);
 100         clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
 101         clks >>= 13;
 102
 103         /* If we had a remainder greater than the 1ps error, then round up */
 104         if (clks_rem > data_rate)
 105                 clks++;
 106
 107         /* Clamp to the maximum representable value */
 108         if (clks > ULL_8FS)
 109                 clks = ULL_8FS;
 110         return (unsigned int) clks;
 111 }
 112
 113 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
 114 {
 115         return get_memory_clk_period_ps(ctrl_num) * mclk;
 116 }
 117
 118 #ifdef CONFIG_PPC
 119 void
 120 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 121                            unsigned int law_memctl,
 122                            unsigned int ctrl_num)
 123 {
 124         unsigned long long base = memctl_common_params->base_address;
 125         unsigned long long size = memctl_common_params->total_mem;
 126
 127         /*
 128          * If no DIMMs on this controller, do not proceed any further.
 129          */
 130         if (!memctl_common_params->ndimms_present) {
 131                 return;
 132         }
 133
 134 #if !defined(CONFIG_PHYS_64BIT)
 135         if (base >= CONFIG_MAX_MEM_MAPPED)
 136                 return;
 137         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
 138                 size = CONFIG_MAX_MEM_MAPPED - base;
 139 #endif
 140         if (set_ddr_laws(base, size, law_memctl) < 0) {
 141                 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
 142                         law_memctl);
 143                 return ;
 144         }
 145         debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
 146                 base, size, law_memctl);
 147 }
 148
 149 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 150 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 151                          unsigned int memctl_interleaved,
 152                          unsigned int ctrl_num);
 153 #endif
 154
 155 void fsl_ddr_set_intl3r(const unsigned int granule_size)
 156 {
 157 #ifdef CONFIG_E6500
 158         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 159         *mcintl3r = 0x80000000 | (granule_size & 0x1f);
 160         debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
 161 #endif
 162 }
 163
 164 u32 fsl_ddr_get_intl3r(void)
 165 {
 166         u32 val = 0;
 167 #ifdef CONFIG_E6500
 168         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 169         val = *mcintl3r;
 170 #endif
 171         return val;
 172 }
 173
 174 void print_ddr_info(unsigned int start_ctrl)
 175 {
 176         struct ccsr_ddr __iomem *ddr =
 177                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 178
 179 #if     defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
 180         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 181 #endif
 182 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 183         uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
 184 #endif
 185         uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 186         int cas_lat;
 187
 188 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
 189         if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 190             (start_ctrl == 1)) {
 191                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
 192                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 193         }
 194 #endif
 195 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
 196         if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 197             (start_ctrl == 2)) {
 198                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
 199                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 200         }
 201 #endif
 202
 203         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
 204                 puts(" (DDR not enabled)\n");
 205                 return;
 206         }
 207
 208         puts(" (DDR");
 209         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 210                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 211         case SDRAM_TYPE_DDR1:
 212                 puts("1");
 213                 break;
 214         case SDRAM_TYPE_DDR2:
 215                 puts("2");
 216                 break;
 217         case SDRAM_TYPE_DDR3:
 218                 puts("3");
 219                 break;
 220         case SDRAM_TYPE_DDR4:
 221                 puts("4");
 222                 break;
 223         default:
 224                 puts("?");
 225                 break;
 226         }
 227
 228         if (sdram_cfg & SDRAM_CFG_32_BE)
 229                 puts(", 32-bit");
 230         else if (sdram_cfg & SDRAM_CFG_16_BE)
 231                 puts(", 16-bit");
 232         else
 233                 puts(", 64-bit");
 234
 235         /* Calculate CAS latency based on timing cfg values */
 236         cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
 237         if (fsl_ddr_get_version(0) <= 0x40400)
 238                 cas_lat += 1;
 239         else
 240                 cas_lat += 2;
 241         cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
 242         printf(", CL=%d", cas_lat >> 1);
 243         if (cas_lat & 0x1)
 244                 puts(".5");
 245
 246         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 247                 puts(", ECC on)");
 248         else
 249                 puts(", ECC off)");
 250
 251 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
 252 #ifdef CONFIG_E6500
 253         if (*mcintl3r & 0x80000000) {
 254                 puts("\n");
 255                 puts("       DDR Controller Interleaving Mode: ");
 256                 switch (*mcintl3r & 0x1f) {
 257                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 258                         puts("3-way 1KB");
 259                         break;
 260                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 261                         puts("3-way 4KB");
 262                         break;
 263                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 264                         puts("3-way 8KB");
 265                         break;
 266                 default:
 267                         puts("3-way UNKNOWN");
 268                         break;
 269                 }
 270         }
 271 #endif
 272 #endif
 273 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 274         if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
 275                 puts("\n");
 276                 puts("       DDR Controller Interleaving Mode: ");
 277
 278                 switch ((cs0_config >> 24) & 0xf) {
 279                 case FSL_DDR_256B_INTERLEAVING:
 280                         puts("256B");
 281                         break;
 282                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 283                         puts("cache line");
 284                         break;
 285                 case FSL_DDR_PAGE_INTERLEAVING:
 286                         puts("page");
 287                         break;
 288                 case FSL_DDR_BANK_INTERLEAVING:
 289                         puts("bank");
 290                         break;
 291                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 292                         puts("super-bank");
 293                         break;
 294                 default:
 295                         puts("invalid");
 296                         break;
 297                 }
 298         }
 299 #endif
 300
 301         if ((sdram_cfg >> 8) & 0x7f) {
 302                 puts("\n");
 303                 puts("       DDR Chip-Select Interleaving Mode: ");
 304                 switch(sdram_cfg >> 8 & 0x7f) {
 305                 case FSL_DDR_CS0_CS1_CS2_CS3:
 306                         puts("CS0+CS1+CS2+CS3");
 307                         break;
 308                 case FSL_DDR_CS0_CS1:
 309                         puts("CS0+CS1");
 310                         break;
 311                 case FSL_DDR_CS2_CS3:
 312                         puts("CS2+CS3");
 313                         break;
 314                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 315                         puts("CS0+CS1 and CS2+CS3");
 316                         break;
 317                 default:
 318                         puts("invalid");
 319                         break;
 320                 }
 321         }
 322 }
 323
 324 void __weak detail_board_ddr_info(void)
 325 {
 326         print_ddr_info(0);
 327 }
 328
 329 void board_add_ram_info(int use_default)
 330 {
 331         detail_board_ddr_info();
 332 }
 333
 334 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 335 #define DDRC_DEBUG20_INIT_DONE  0x80000000
 336 #define DDRC_DEBUG2_RF          0x00000040
 337 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 338                                  unsigned int last_ctrl)
 339 {
 340         unsigned int i;
 341         u32 ddrc_debug20;
 342         u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
 343         u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
 344         struct ccsr_ddr __iomem *ddr;
 345
 346         for (i = first_ctrl; i <= last_ctrl; i++) {
 347                 switch (i) {
 348                 case 0:
 349                         ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 350                         break;
 351 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 352                 case 1:
 353                         ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
 354                         break;
 355 #endif
 356 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
 357                 case 2:
 358                         ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
 359                         break;
 360 #endif
 361 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
 362                 case 3:
 363                         ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 364                         break;
 365 #endif
 366                 default:
 367                         printf("%s unexpected ctrl = %u\n", __func__, i);
 368                         return;
 369                 }
 370                 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
 371                 ddrc_debug2_p[i] = &ddr->debug[1];
 372                 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
 373                         /* keep polling until DDRC init is done */
 374                         udelay(100);
 375                         ddrc_debug20 = ddr_in32(&ddr->debug[19]);
 376                 }
 377                 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
 378         }
 379         /*
 380          * Sync refresh
 381          * This is put together to make sure the refresh reqeusts are sent
 382          * closely to each other.
 383          */
 384         for (i = first_ctrl; i <= last_ctrl; i++)
 385                 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
 386 }
 387 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
 388
 389 void remove_unused_controllers(fsl_ddr_info_t *info)
 390 {
 391 #ifdef CONFIG_FSL_LSCH3
 392         int i;
 393         u64 nodeid;
 394         void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
 395         bool ddr0_used = false;
 396         bool ddr1_used = false;
 397
 398         for (i = 0; i < 8; i++) {
 399                 nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
 400                 if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
 401                         ddr0_used = true;
 402                 } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
 403                         ddr1_used = true;
 404                 } else {
 405                         printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
 406                                nodeid);
 407                 }
 408                 hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
 409         }
 410         if (!ddr0_used && !ddr1_used) {
 411                 printf("Invalid configuration in HN-F SAM control\n");
 412                 return;
 413         }
 414
 415         if (!ddr0_used && info->first_ctrl == 0) {
 416                 info->first_ctrl = 1;
 417                 info->num_ctrls = 1;
 418                 debug("First DDR controller disabled\n");
 419                 return;
 420         }
 421
 422         if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
 423                 info->num_ctrls = 1;
 424                 debug("Second DDR controller disabled\n");
 425         }
 426 #endif
 427 }