drivers/ddr/fsl/options.c

   1 /*
   2  * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <hwconfig.h>
   9 #include <fsl_ddr_sdram.h>
  10
  11 #include <fsl_ddr.h>
  12
  13 /*
  14  * Use our own stack based buffer before relocation to allow accessing longer
  15  * hwconfig strings that might be in the environment before we've relocated.
  16  * This is pretty fragile on both the use of stack and if the buffer is big
  17  * enough. However we will get a warning from getenv_f for the later.
  18  */
  19
  20 /* Board-specific functions defined in each board's ddr.c */
  21 extern void fsl_ddr_board_options(memctl_options_t *popts,
  22                 dimm_params_t *pdimm,
  23                 unsigned int ctrl_num);
  24
  25 struct dynamic_odt {
  26         unsigned int odt_rd_cfg;
  27         unsigned int odt_wr_cfg;
  28         unsigned int odt_rtt_norm;
  29         unsigned int odt_rtt_wr;
  30 };
  31
  32 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  33 static const struct dynamic_odt single_Q[4] = {
  34         {       /* cs0 */
  35                 FSL_DDR_ODT_NEVER,
  36                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  37                 DDR3_RTT_20_OHM,
  38                 DDR3_RTT_120_OHM
  39         },
  40         {       /* cs1 */
  41                 FSL_DDR_ODT_NEVER,
  42                 FSL_DDR_ODT_NEVER,      /* tied high */
  43                 DDR3_RTT_OFF,
  44                 DDR3_RTT_120_OHM
  45         },
  46         {       /* cs2 */
  47                 FSL_DDR_ODT_NEVER,
  48                 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
  49                 DDR3_RTT_20_OHM,
  50                 DDR3_RTT_120_OHM
  51         },
  52         {       /* cs3 */
  53                 FSL_DDR_ODT_NEVER,
  54                 FSL_DDR_ODT_NEVER,      /* tied high */
  55                 DDR3_RTT_OFF,
  56                 DDR3_RTT_120_OHM
  57         }
  58 };
  59
  60 static const struct dynamic_odt single_D[4] = {
  61         {       /* cs0 */
  62                 FSL_DDR_ODT_NEVER,
  63                 FSL_DDR_ODT_ALL,
  64                 DDR3_RTT_40_OHM,
  65                 DDR3_RTT_OFF
  66         },
  67         {       /* cs1 */
  68                 FSL_DDR_ODT_NEVER,
  69                 FSL_DDR_ODT_NEVER,
  70                 DDR3_RTT_OFF,
  71                 DDR3_RTT_OFF
  72         },
  73         {0, 0, 0, 0},
  74         {0, 0, 0, 0}
  75 };
  76
  77 static const struct dynamic_odt single_S[4] = {
  78         {       /* cs0 */
  79                 FSL_DDR_ODT_NEVER,
  80                 FSL_DDR_ODT_ALL,
  81                 DDR3_RTT_40_OHM,
  82                 DDR3_RTT_OFF
  83         },
  84         {0, 0, 0, 0},
  85         {0, 0, 0, 0},
  86         {0, 0, 0, 0},
  87 };
  88
  89 static const struct dynamic_odt dual_DD[4] = {
  90         {       /* cs0 */
  91                 FSL_DDR_ODT_NEVER,
  92                 FSL_DDR_ODT_SAME_DIMM,
  93                 DDR3_RTT_120_OHM,
  94                 DDR3_RTT_OFF
  95         },
  96         {       /* cs1 */
  97                 FSL_DDR_ODT_OTHER_DIMM,
  98                 FSL_DDR_ODT_OTHER_DIMM,
  99                 DDR3_RTT_30_OHM,
 100                 DDR3_RTT_OFF
 101         },
 102         {       /* cs2 */
 103                 FSL_DDR_ODT_NEVER,
 104                 FSL_DDR_ODT_SAME_DIMM,
 105                 DDR3_RTT_120_OHM,
 106                 DDR3_RTT_OFF
 107         },
 108         {       /* cs3 */
 109                 FSL_DDR_ODT_OTHER_DIMM,
 110                 FSL_DDR_ODT_OTHER_DIMM,
 111                 DDR3_RTT_30_OHM,
 112                 DDR3_RTT_OFF
 113         }
 114 };
 115
 116 static const struct dynamic_odt dual_DS[4] = {
 117         {       /* cs0 */
 118                 FSL_DDR_ODT_NEVER,
 119                 FSL_DDR_ODT_SAME_DIMM,
 120                 DDR3_RTT_120_OHM,
 121                 DDR3_RTT_OFF
 122         },
 123         {       /* cs1 */
 124                 FSL_DDR_ODT_OTHER_DIMM,
 125                 FSL_DDR_ODT_OTHER_DIMM,
 126                 DDR3_RTT_30_OHM,
 127                 DDR3_RTT_OFF
 128         },
 129         {       /* cs2 */
 130                 FSL_DDR_ODT_OTHER_DIMM,
 131                 FSL_DDR_ODT_ALL,
 132                 DDR3_RTT_20_OHM,
 133                 DDR3_RTT_120_OHM
 134         },
 135         {0, 0, 0, 0}
 136 };
 137 static const struct dynamic_odt dual_SD[4] = {
 138         {       /* cs0 */
 139                 FSL_DDR_ODT_OTHER_DIMM,
 140                 FSL_DDR_ODT_ALL,
 141                 DDR3_RTT_20_OHM,
 142                 DDR3_RTT_120_OHM
 143         },
 144         {0, 0, 0, 0},
 145         {       /* cs2 */
 146                 FSL_DDR_ODT_NEVER,
 147                 FSL_DDR_ODT_SAME_DIMM,
 148                 DDR3_RTT_120_OHM,
 149                 DDR3_RTT_OFF
 150         },
 151         {       /* cs3 */
 152                 FSL_DDR_ODT_OTHER_DIMM,
 153                 FSL_DDR_ODT_OTHER_DIMM,
 154                 DDR3_RTT_20_OHM,
 155                 DDR3_RTT_OFF
 156         }
 157 };
 158
 159 static const struct dynamic_odt dual_SS[4] = {
 160         {       /* cs0 */
 161                 FSL_DDR_ODT_OTHER_DIMM,
 162                 FSL_DDR_ODT_ALL,
 163                 DDR3_RTT_30_OHM,
 164                 DDR3_RTT_120_OHM
 165         },
 166         {0, 0, 0, 0},
 167         {       /* cs2 */
 168                 FSL_DDR_ODT_OTHER_DIMM,
 169                 FSL_DDR_ODT_ALL,
 170                 DDR3_RTT_30_OHM,
 171                 DDR3_RTT_120_OHM
 172         },
 173         {0, 0, 0, 0}
 174 };
 175
 176 static const struct dynamic_odt dual_D0[4] = {
 177         {       /* cs0 */
 178                 FSL_DDR_ODT_NEVER,
 179                 FSL_DDR_ODT_SAME_DIMM,
 180                 DDR3_RTT_40_OHM,
 181                 DDR3_RTT_OFF
 182         },
 183         {       /* cs1 */
 184                 FSL_DDR_ODT_NEVER,
 185                 FSL_DDR_ODT_NEVER,
 186                 DDR3_RTT_OFF,
 187                 DDR3_RTT_OFF
 188         },
 189         {0, 0, 0, 0},
 190         {0, 0, 0, 0}
 191 };
 192
 193 static const struct dynamic_odt dual_0D[4] = {
 194         {0, 0, 0, 0},
 195         {0, 0, 0, 0},
 196         {       /* cs2 */
 197                 FSL_DDR_ODT_NEVER,
 198                 FSL_DDR_ODT_SAME_DIMM,
 199                 DDR3_RTT_40_OHM,
 200                 DDR3_RTT_OFF
 201         },
 202         {       /* cs3 */
 203                 FSL_DDR_ODT_NEVER,
 204                 FSL_DDR_ODT_NEVER,
 205                 DDR3_RTT_OFF,
 206                 DDR3_RTT_OFF
 207         }
 208 };
 209
 210 static const struct dynamic_odt dual_S0[4] = {
 211         {       /* cs0 */
 212                 FSL_DDR_ODT_NEVER,
 213                 FSL_DDR_ODT_CS,
 214                 DDR3_RTT_40_OHM,
 215                 DDR3_RTT_OFF
 216         },
 217         {0, 0, 0, 0},
 218         {0, 0, 0, 0},
 219         {0, 0, 0, 0}
 220
 221 };
 222
 223 static const struct dynamic_odt dual_0S[4] = {
 224         {0, 0, 0, 0},
 225         {0, 0, 0, 0},
 226         {       /* cs2 */
 227                 FSL_DDR_ODT_NEVER,
 228                 FSL_DDR_ODT_CS,
 229                 DDR3_RTT_40_OHM,
 230                 DDR3_RTT_OFF
 231         },
 232         {0, 0, 0, 0}
 233
 234 };
 235
 236 static const struct dynamic_odt odt_unknown[4] = {
 237         {       /* cs0 */
 238                 FSL_DDR_ODT_NEVER,
 239                 FSL_DDR_ODT_CS,
 240                 DDR3_RTT_120_OHM,
 241                 DDR3_RTT_OFF
 242         },
 243         {       /* cs1 */
 244                 FSL_DDR_ODT_NEVER,
 245                 FSL_DDR_ODT_CS,
 246                 DDR3_RTT_120_OHM,
 247                 DDR3_RTT_OFF
 248         },
 249         {       /* cs2 */
 250                 FSL_DDR_ODT_NEVER,
 251                 FSL_DDR_ODT_CS,
 252                 DDR3_RTT_120_OHM,
 253                 DDR3_RTT_OFF
 254         },
 255         {       /* cs3 */
 256                 FSL_DDR_ODT_NEVER,
 257                 FSL_DDR_ODT_CS,
 258                 DDR3_RTT_120_OHM,
 259                 DDR3_RTT_OFF
 260         }
 261 };
 262 #else   /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
 263 static const struct dynamic_odt single_Q[4] = {
 264         {0, 0, 0, 0},
 265         {0, 0, 0, 0},
 266         {0, 0, 0, 0},
 267         {0, 0, 0, 0}
 268 };
 269
 270 static const struct dynamic_odt single_D[4] = {
 271         {       /* cs0 */
 272                 FSL_DDR_ODT_NEVER,
 273                 FSL_DDR_ODT_ALL,
 274                 DDR2_RTT_150_OHM,
 275                 DDR2_RTT_OFF
 276         },
 277         {       /* cs1 */
 278                 FSL_DDR_ODT_NEVER,
 279                 FSL_DDR_ODT_NEVER,
 280                 DDR2_RTT_OFF,
 281                 DDR2_RTT_OFF
 282         },
 283         {0, 0, 0, 0},
 284         {0, 0, 0, 0}
 285 };
 286
 287 static const struct dynamic_odt single_S[4] = {
 288         {       /* cs0 */
 289                 FSL_DDR_ODT_NEVER,
 290                 FSL_DDR_ODT_ALL,
 291                 DDR2_RTT_150_OHM,
 292                 DDR2_RTT_OFF
 293         },
 294         {0, 0, 0, 0},
 295         {0, 0, 0, 0},
 296         {0, 0, 0, 0},
 297 };
 298
 299 static const struct dynamic_odt dual_DD[4] = {
 300         {       /* cs0 */
 301                 FSL_DDR_ODT_OTHER_DIMM,
 302                 FSL_DDR_ODT_OTHER_DIMM,
 303                 DDR2_RTT_75_OHM,
 304                 DDR2_RTT_OFF
 305         },
 306         {       /* cs1 */
 307                 FSL_DDR_ODT_NEVER,
 308                 FSL_DDR_ODT_NEVER,
 309                 DDR2_RTT_OFF,
 310                 DDR2_RTT_OFF
 311         },
 312         {       /* cs2 */
 313                 FSL_DDR_ODT_OTHER_DIMM,
 314                 FSL_DDR_ODT_OTHER_DIMM,
 315                 DDR2_RTT_75_OHM,
 316                 DDR2_RTT_OFF
 317         },
 318         {       /* cs3 */
 319                 FSL_DDR_ODT_NEVER,
 320                 FSL_DDR_ODT_NEVER,
 321                 DDR2_RTT_OFF,
 322                 DDR2_RTT_OFF
 323         }
 324 };
 325
 326 static const struct dynamic_odt dual_DS[4] = {
 327         {       /* cs0 */
 328                 FSL_DDR_ODT_OTHER_DIMM,
 329                 FSL_DDR_ODT_OTHER_DIMM,
 330                 DDR2_RTT_75_OHM,
 331                 DDR2_RTT_OFF
 332         },
 333         {       /* cs1 */
 334                 FSL_DDR_ODT_NEVER,
 335                 FSL_DDR_ODT_NEVER,
 336                 DDR2_RTT_OFF,
 337                 DDR2_RTT_OFF
 338         },
 339         {       /* cs2 */
 340                 FSL_DDR_ODT_OTHER_DIMM,
 341                 FSL_DDR_ODT_OTHER_DIMM,
 342                 DDR2_RTT_75_OHM,
 343                 DDR2_RTT_OFF
 344         },
 345         {0, 0, 0, 0}
 346 };
 347
 348 static const struct dynamic_odt dual_SD[4] = {
 349         {       /* cs0 */
 350                 FSL_DDR_ODT_OTHER_DIMM,
 351                 FSL_DDR_ODT_OTHER_DIMM,
 352                 DDR2_RTT_75_OHM,
 353                 DDR2_RTT_OFF
 354         },
 355         {0, 0, 0, 0},
 356         {       /* cs2 */
 357                 FSL_DDR_ODT_OTHER_DIMM,
 358                 FSL_DDR_ODT_OTHER_DIMM,
 359                 DDR2_RTT_75_OHM,
 360                 DDR2_RTT_OFF
 361         },
 362         {       /* cs3 */
 363                 FSL_DDR_ODT_NEVER,
 364                 FSL_DDR_ODT_NEVER,
 365                 DDR2_RTT_OFF,
 366                 DDR2_RTT_OFF
 367         }
 368 };
 369
 370 static const struct dynamic_odt dual_SS[4] = {
 371         {       /* cs0 */
 372                 FSL_DDR_ODT_OTHER_DIMM,
 373                 FSL_DDR_ODT_OTHER_DIMM,
 374                 DDR2_RTT_75_OHM,
 375                 DDR2_RTT_OFF
 376         },
 377         {0, 0, 0, 0},
 378         {       /* cs2 */
 379                 FSL_DDR_ODT_OTHER_DIMM,
 380                 FSL_DDR_ODT_OTHER_DIMM,
 381                 DDR2_RTT_75_OHM,
 382                 DDR2_RTT_OFF
 383         },
 384         {0, 0, 0, 0}
 385 };
 386
 387 static const struct dynamic_odt dual_D0[4] = {
 388         {       /* cs0 */
 389                 FSL_DDR_ODT_NEVER,
 390                 FSL_DDR_ODT_ALL,
 391                 DDR2_RTT_150_OHM,
 392                 DDR2_RTT_OFF
 393         },
 394         {       /* cs1 */
 395                 FSL_DDR_ODT_NEVER,
 396                 FSL_DDR_ODT_NEVER,
 397                 DDR2_RTT_OFF,
 398                 DDR2_RTT_OFF
 399         },
 400         {0, 0, 0, 0},
 401         {0, 0, 0, 0}
 402 };
 403
 404 static const struct dynamic_odt dual_0D[4] = {
 405         {0, 0, 0, 0},
 406         {0, 0, 0, 0},
 407         {       /* cs2 */
 408                 FSL_DDR_ODT_NEVER,
 409                 FSL_DDR_ODT_ALL,
 410                 DDR2_RTT_150_OHM,
 411                 DDR2_RTT_OFF
 412         },
 413         {       /* cs3 */
 414                 FSL_DDR_ODT_NEVER,
 415                 FSL_DDR_ODT_NEVER,
 416                 DDR2_RTT_OFF,
 417                 DDR2_RTT_OFF
 418         }
 419 };
 420
 421 static const struct dynamic_odt dual_S0[4] = {
 422         {       /* cs0 */
 423                 FSL_DDR_ODT_NEVER,
 424                 FSL_DDR_ODT_CS,
 425                 DDR2_RTT_150_OHM,
 426                 DDR2_RTT_OFF
 427         },
 428         {0, 0, 0, 0},
 429         {0, 0, 0, 0},
 430         {0, 0, 0, 0}
 431
 432 };
 433
 434 static const struct dynamic_odt dual_0S[4] = {
 435         {0, 0, 0, 0},
 436         {0, 0, 0, 0},
 437         {       /* cs2 */
 438                 FSL_DDR_ODT_NEVER,
 439                 FSL_DDR_ODT_CS,
 440                 DDR2_RTT_150_OHM,
 441                 DDR2_RTT_OFF
 442         },
 443         {0, 0, 0, 0}
 444
 445 };
 446
 447 static const struct dynamic_odt odt_unknown[4] = {
 448         {       /* cs0 */
 449                 FSL_DDR_ODT_NEVER,
 450                 FSL_DDR_ODT_CS,
 451                 DDR2_RTT_75_OHM,
 452                 DDR2_RTT_OFF
 453         },
 454         {       /* cs1 */
 455                 FSL_DDR_ODT_NEVER,
 456                 FSL_DDR_ODT_NEVER,
 457                 DDR2_RTT_OFF,
 458                 DDR2_RTT_OFF
 459         },
 460         {       /* cs2 */
 461                 FSL_DDR_ODT_NEVER,
 462                 FSL_DDR_ODT_CS,
 463                 DDR2_RTT_75_OHM,
 464                 DDR2_RTT_OFF
 465         },
 466         {       /* cs3 */
 467                 FSL_DDR_ODT_NEVER,
 468                 FSL_DDR_ODT_NEVER,
 469                 DDR2_RTT_OFF,
 470                 DDR2_RTT_OFF
 471         }
 472 };
 473 #endif
 474
 475 /*
 476  * Automatically seleect bank interleaving mode based on DIMMs
 477  * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
 478  * This function only deal with one or two slots per controller.
 479  */
 480 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
 481 {
 482 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 483         if (pdimm[0].n_ranks == 4)
 484                 return FSL_DDR_CS0_CS1_CS2_CS3;
 485         else if (pdimm[0].n_ranks == 2)
 486                 return FSL_DDR_CS0_CS1;
 487 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 488 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 489         if (pdimm[0].n_ranks == 4)
 490                 return FSL_DDR_CS0_CS1_CS2_CS3;
 491 #endif
 492         if (pdimm[0].n_ranks == 2) {
 493                 if (pdimm[1].n_ranks == 2)
 494                         return FSL_DDR_CS0_CS1_CS2_CS3;
 495                 else
 496                         return FSL_DDR_CS0_CS1;
 497         }
 498 #endif
 499         return 0;
 500 }
 501
 502 unsigned int populate_memctl_options(int all_dimms_registered,
 503                         memctl_options_t *popts,
 504                         dimm_params_t *pdimm,
 505                         unsigned int ctrl_num)
 506 {
 507         unsigned int i;
 508         char buffer[HWCONFIG_BUFFER_SIZE];
 509         char *buf = NULL;
 510 #if defined(CONFIG_SYS_FSL_DDR3) || \
 511         defined(CONFIG_SYS_FSL_DDR2) || \
 512         defined(CONFIG_SYS_FSL_DDR4)
 513         const struct dynamic_odt *pdodt = odt_unknown;
 514 #endif
 515         ulong ddr_freq;
 516
 517         /*
 518          * Extract hwconfig from environment since we have not properly setup
 519          * the environment but need it for ddr config params
 520          */
 521         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 522                 buf = buffer;
 523
 524 #if defined(CONFIG_SYS_FSL_DDR3) || \
 525         defined(CONFIG_SYS_FSL_DDR2) || \
 526         defined(CONFIG_SYS_FSL_DDR4)
 527         /* Chip select options. */
 528 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 529         switch (pdimm[0].n_ranks) {
 530         case 1:
 531                 pdodt = single_S;
 532                 break;
 533         case 2:
 534                 pdodt = single_D;
 535                 break;
 536         case 4:
 537                 pdodt = single_Q;
 538                 break;
 539         }
 540 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 541         switch (pdimm[0].n_ranks) {
 542 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 543         case 4:
 544                 pdodt = single_Q;
 545                 if (pdimm[1].n_ranks)
 546                         printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
 547                 break;
 548 #endif
 549         case 2:
 550                 switch (pdimm[1].n_ranks) {
 551                 case 2:
 552                         pdodt = dual_DD;
 553                         break;
 554                 case 1:
 555                         pdodt = dual_DS;
 556                         break;
 557                 case 0:
 558                         pdodt = dual_D0;
 559                         break;
 560                 }
 561                 break;
 562         case 1:
 563                 switch (pdimm[1].n_ranks) {
 564                 case 2:
 565                         pdodt = dual_SD;
 566                         break;
 567                 case 1:
 568                         pdodt = dual_SS;
 569                         break;
 570                 case 0:
 571                         pdodt = dual_S0;
 572                         break;
 573                 }
 574                 break;
 575         case 0:
 576                 switch (pdimm[1].n_ranks) {
 577                 case 2:
 578                         pdodt = dual_0D;
 579                         break;
 580                 case 1:
 581                         pdodt = dual_0S;
 582                         break;
 583                 }
 584                 break;
 585         }
 586 #endif  /* CONFIG_DIMM_SLOTS_PER_CTLR */
 587 #endif  /* CONFIG_SYS_FSL_DDR2, 3, 4 */
 588
 589         /* Pick chip-select local options. */
 590         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 591 #if defined(CONFIG_SYS_FSL_DDR3) || \
 592         defined(CONFIG_SYS_FSL_DDR2) || \
 593         defined(CONFIG_SYS_FSL_DDR4)
 594                 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
 595                 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
 596                 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
 597                 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
 598 #else
 599                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 600                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 601 #endif
 602                 popts->cs_local_opts[i].auto_precharge = 0;
 603         }
 604
 605         /* Pick interleaving mode. */
 606
 607         /*
 608          * 0 = no interleaving
 609          * 1 = interleaving between 2 controllers
 610          */
 611         popts->memctl_interleaving = 0;
 612
 613         /*
 614          * 0 = cacheline
 615          * 1 = page
 616          * 2 = (logical) bank
 617          * 3 = superbank (only if CS interleaving is enabled)
 618          */
 619         popts->memctl_interleaving_mode = 0;
 620
 621         /*
 622          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
 623          * 1: page:      bit to the left of the column bits selects the memctl
 624          * 2: bank:      bit to the left of the bank bits selects the memctl
 625          * 3: superbank: bit to the left of the chip select selects the memctl
 626          *
 627          * NOTE: ba_intlv (rank interleaving) is independent of memory
 628          * controller interleaving; it is only within a memory controller.
 629          * Must use superbank interleaving if rank interleaving is used and
 630          * memory controller interleaving is enabled.
 631          */
 632
 633         /*
 634          * 0 = no
 635          * 0x40 = CS0,CS1
 636          * 0x20 = CS2,CS3
 637          * 0x60 = CS0,CS1 + CS2,CS3
 638          * 0x04 = CS0,CS1,CS2,CS3
 639          */
 640         popts->ba_intlv_ctl = 0;
 641
 642         /* Memory Organization Parameters */
 643         popts->registered_dimm_en = all_dimms_registered;
 644
 645         /* Operational Mode Paramters */
 646
 647         /* Pick ECC modes */
 648         popts->ecc_mode = 0;              /* 0 = disabled, 1 = enabled */
 649 #ifdef CONFIG_DDR_ECC
 650         if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 651                 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
 652                         popts->ecc_mode = 1;
 653         } else
 654                 popts->ecc_mode = 1;
 655 #endif
 656         popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 657
 658         /*
 659          * Choose DQS config
 660          * 0 for DDR1
 661          * 1 for DDR2
 662          */
 663 #if defined(CONFIG_SYS_FSL_DDR1)
 664         popts->dqs_config = 0;
 665 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
 666         popts->dqs_config = 1;
 667 #endif
 668
 669         /* Choose self-refresh during sleep. */
 670         popts->self_refresh_in_sleep = 1;
 671
 672         /* Choose dynamic power management mode. */
 673         popts->dynamic_power = 0;
 674
 675         /*
 676          * check first dimm for primary sdram width
 677          * presuming all dimms are similar
 678          * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 679          */
 680 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 681         if (pdimm[0].n_ranks != 0) {
 682                 if ((pdimm[0].data_width >= 64) && \
 683                         (pdimm[0].data_width <= 72))
 684                         popts->data_bus_width = 0;
 685                 else if ((pdimm[0].data_width >= 32) || \
 686                         (pdimm[0].data_width <= 40))
 687                         popts->data_bus_width = 1;
 688                 else {
 689                         panic("Error: data width %u is invalid!\n",
 690                                 pdimm[0].data_width);
 691                 }
 692         }
 693 #else
 694         if (pdimm[0].n_ranks != 0) {
 695                 if (pdimm[0].primary_sdram_width == 64)
 696                         popts->data_bus_width = 0;
 697                 else if (pdimm[0].primary_sdram_width == 32)
 698                         popts->data_bus_width = 1;
 699                 else if (pdimm[0].primary_sdram_width == 16)
 700                         popts->data_bus_width = 2;
 701                 else {
 702                         panic("Error: primary sdram width %u is invalid!\n",
 703                                 pdimm[0].primary_sdram_width);
 704                 }
 705         }
 706 #endif
 707
 708         popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
 709
 710         /* Choose burst length. */
 711 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 712 #if defined(CONFIG_E500MC)
 713         popts->otf_burst_chop_en = 0;   /* on-the-fly burst chop disable */
 714         popts->burst_length = DDR_BL8;  /* Fixed 8-beat burst len */
 715 #else
 716         if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 717                 /* 32-bit or 16-bit bus */
 718                 popts->otf_burst_chop_en = 0;
 719                 popts->burst_length = DDR_BL8;
 720         } else {
 721                 popts->otf_burst_chop_en = 1;   /* on-the-fly burst chop */
 722                 popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 723         }
 724 #endif
 725 #else
 726         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 727 #endif
 728
 729         /* Choose ddr controller address mirror mode */
 730 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 731         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 732                 if (pdimm[i].n_ranks) {
 733                         popts->mirrored_dimm = pdimm[i].mirrored_dimm;
 734                         break;
 735                 }
 736         }
 737 #endif
 738
 739         /* Global Timing Parameters. */
 740         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
 741
 742         /* Pick a caslat override. */
 743         popts->cas_latency_override = 0;
 744         popts->cas_latency_override_value = 3;
 745         if (popts->cas_latency_override) {
 746                 debug("using caslat override value = %u\n",
 747                        popts->cas_latency_override_value);
 748         }
 749
 750         /* Decide whether to use the computed derated latency */
 751         popts->use_derated_caslat = 0;
 752
 753         /* Choose an additive latency. */
 754         popts->additive_latency_override = 0;
 755         popts->additive_latency_override_value = 3;
 756         if (popts->additive_latency_override) {
 757                 debug("using additive latency override value = %u\n",
 758                        popts->additive_latency_override_value);
 759         }
 760
 761         /*
 762          * 2T_EN setting
 763          *
 764          * Factors to consider for 2T_EN:
 765          *      - number of DIMMs installed
 766          *      - number of components, number of active ranks
 767          *      - how much time you want to spend playing around
 768          */
 769         popts->twot_en = 0;
 770         popts->threet_en = 0;
 771
 772         /* for RDIMM, address parity enable */
 773         popts->ap_en = 1;
 774
 775         /*
 776          * BSTTOPRE precharge interval
 777          *
 778          * Set this to 0 for global auto precharge
 779          * The value of 0x100 has been used for DDR1, DDR2, DDR3.
 780          * It is not wrong. Any value should be OK. The performance depends on
 781          * applications. There is no one good value for all.
 782          */
 783         popts->bstopre = 0x100;
 784
 785         /*
 786          * Window for four activates -- tFAW
 787          *
 788          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 789          * FIXME: varies depending upon number of column addresses or data
 790          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 791          */
 792 #if defined(CONFIG_SYS_FSL_DDR1)
 793         popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
 794
 795 #elif defined(CONFIG_SYS_FSL_DDR2)
 796         /*
 797          * x4/x8;  some datasheets have 35000
 798          * x16 wide columns only?  Use 50000?
 799          */
 800         popts->tfaw_window_four_activates_ps = 37500;
 801
 802 #else
 803         popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
 804 #endif
 805         popts->zq_en = 0;
 806         popts->wrlvl_en = 0;
 807 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 808         /*
 809          * due to ddr3 dimm is fly-by topology
 810          * we suggest to enable write leveling to
 811          * meet the tQDSS under different loading.
 812          */
 813         popts->wrlvl_en = 1;
 814         popts->zq_en = 1;
 815         popts->wrlvl_override = 0;
 816 #endif
 817
 818         /*
 819          * Check interleaving configuration from environment.
 820          * Please refer to doc/README.fsl-ddr for the detail.
 821          *
 822          * If memory controller interleaving is enabled, then the data
 823          * bus widths must be programmed identically for all memory controllers.
 824          *
 825          * Attempt to set all controllers to the same chip select
 826          * interleaving mode. It will do a best effort to get the
 827          * requested ranks interleaved together such that the result
 828          * should be a subset of the requested configuration.
 829          *
 830          * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
 831          * with 256 Byte is enabled.
 832          */
 833 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 834         if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
 835 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
 836                 ;
 837 #else
 838                 goto done;
 839 #endif
 840         if (pdimm[0].n_ranks == 0) {
 841                 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
 842                 popts->memctl_interleaving = 0;
 843                 goto done;
 844         }
 845         popts->memctl_interleaving = 1;
 846 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
 847         popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
 848         popts->memctl_interleaving = 1;
 849         debug("256 Byte interleaving\n");
 850 #else
 851         /*
 852          * test null first. if CONFIG_HWCONFIG is not defined
 853          * hwconfig_arg_cmp returns non-zero
 854          */
 855         if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
 856                                     "null", buf)) {
 857                 popts->memctl_interleaving = 0;
 858                 debug("memory controller interleaving disabled.\n");
 859         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 860                                         "ctlr_intlv",
 861                                         "cacheline", buf)) {
 862                 popts->memctl_interleaving_mode =
 863                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 864                         0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
 865                 popts->memctl_interleaving =
 866                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 867                         0 : 1;
 868         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 869                                         "ctlr_intlv",
 870                                         "page", buf)) {
 871                 popts->memctl_interleaving_mode =
 872                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 873                         0 : FSL_DDR_PAGE_INTERLEAVING;
 874                 popts->memctl_interleaving =
 875                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 876                         0 : 1;
 877         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 878                                         "ctlr_intlv",
 879                                         "bank", buf)) {
 880                 popts->memctl_interleaving_mode =
 881                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 882                         0 : FSL_DDR_BANK_INTERLEAVING;
 883                 popts->memctl_interleaving =
 884                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 885                         0 : 1;
 886         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 887                                         "ctlr_intlv",
 888                                         "superbank", buf)) {
 889                 popts->memctl_interleaving_mode =
 890                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 891                         0 : FSL_DDR_SUPERBANK_INTERLEAVING;
 892                 popts->memctl_interleaving =
 893                         ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
 894                         0 : 1;
 895 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
 896         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 897                                         "ctlr_intlv",
 898                                         "3way_1KB", buf)) {
 899                 popts->memctl_interleaving_mode =
 900                         FSL_DDR_3WAY_1KB_INTERLEAVING;
 901         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 902                                         "ctlr_intlv",
 903                                         "3way_4KB", buf)) {
 904                 popts->memctl_interleaving_mode =
 905                         FSL_DDR_3WAY_4KB_INTERLEAVING;
 906         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 907                                         "ctlr_intlv",
 908                                         "3way_8KB", buf)) {
 909                 popts->memctl_interleaving_mode =
 910                         FSL_DDR_3WAY_8KB_INTERLEAVING;
 911 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
 912         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 913                                         "ctlr_intlv",
 914                                         "4way_1KB", buf)) {
 915                 popts->memctl_interleaving_mode =
 916                         FSL_DDR_4WAY_1KB_INTERLEAVING;
 917         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 918                                         "ctlr_intlv",
 919                                         "4way_4KB", buf)) {
 920                 popts->memctl_interleaving_mode =
 921                         FSL_DDR_4WAY_4KB_INTERLEAVING;
 922         } else if (hwconfig_subarg_cmp_f("fsl_ddr",
 923                                         "ctlr_intlv",
 924                                         "4way_8KB", buf)) {
 925                 popts->memctl_interleaving_mode =
 926                         FSL_DDR_4WAY_8KB_INTERLEAVING;
 927 #endif
 928         } else {
 929                 popts->memctl_interleaving = 0;
 930                 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
 931         }
 932 #endif  /* CONFIG_SYS_FSL_DDR_INTLV_256B */
 933 done:
 934 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
 935         if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
 936                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 937                 /* test null first. if CONFIG_HWCONFIG is not defined,
 938                  * hwconfig_subarg_cmp_f returns non-zero */
 939                 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 940                                             "null", buf))
 941                         debug("bank interleaving disabled.\n");
 942                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 943                                                  "cs0_cs1", buf))
 944                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 945                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 946                                                  "cs2_cs3", buf))
 947                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 948                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 949                                                  "cs0_cs1_and_cs2_cs3", buf))
 950                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 951                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 952                                                  "cs0_cs1_cs2_cs3", buf))
 953                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 954                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 955                                                 "auto", buf))
 956                         popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
 957                 else
 958                         printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 959                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 960                 case FSL_DDR_CS0_CS1_CS2_CS3:
 961 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 962                         if (pdimm[0].n_ranks < 4) {
 963                                 popts->ba_intlv_ctl = 0;
 964                                 printf("Not enough bank(chip-select) for "
 965                                         "CS0+CS1+CS2+CS3 on controller %d, "
 966                                         "interleaving disabled!\n", ctrl_num);
 967                         }
 968 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 969 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 970                         if (pdimm[0].n_ranks == 4)
 971                                 break;
 972 #endif
 973                         if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 974                                 popts->ba_intlv_ctl = 0;
 975                                 printf("Not enough bank(chip-select) for "
 976                                         "CS0+CS1+CS2+CS3 on controller %d, "
 977                                         "interleaving disabled!\n", ctrl_num);
 978                         }
 979                         if (pdimm[0].capacity != pdimm[1].capacity) {
 980                                 popts->ba_intlv_ctl = 0;
 981                                 printf("Not identical DIMM size for "
 982                                         "CS0+CS1+CS2+CS3 on controller %d, "
 983                                         "interleaving disabled!\n", ctrl_num);
 984                         }
 985 #endif
 986                         break;
 987                 case FSL_DDR_CS0_CS1:
 988                         if (pdimm[0].n_ranks < 2) {
 989                                 popts->ba_intlv_ctl = 0;
 990                                 printf("Not enough bank(chip-select) for "
 991                                         "CS0+CS1 on controller %d, "
 992                                         "interleaving disabled!\n", ctrl_num);
 993                         }
 994                         break;
 995                 case FSL_DDR_CS2_CS3:
 996 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 997                         if (pdimm[0].n_ranks < 4) {
 998                                 popts->ba_intlv_ctl = 0;
 999                                 printf("Not enough bank(chip-select) for CS2+CS3 "
1000                                         "on controller %d, interleaving disabled!\n", ctrl_num);
1001                         }
1002 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1003                         if (pdimm[1].n_ranks < 2) {
1004                                 popts->ba_intlv_ctl = 0;
1005                                 printf("Not enough bank(chip-select) for CS2+CS3 "
1006                                         "on controller %d, interleaving disabled!\n", ctrl_num);
1007                         }
1008 #endif
1009                         break;
1010                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1011 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1012                         if (pdimm[0].n_ranks < 4) {
1013                                 popts->ba_intlv_ctl = 0;
1014                                 printf("Not enough bank(CS) for CS0+CS1 and "
1015                                         "CS2+CS3 on controller %d, "
1016                                         "interleaving disabled!\n", ctrl_num);
1017                         }
1018 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1019                         if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1020                                 popts->ba_intlv_ctl = 0;
1021                                 printf("Not enough bank(CS) for CS0+CS1 and "
1022                                         "CS2+CS3 on controller %d, "
1023                                         "interleaving disabled!\n", ctrl_num);
1024                         }
1025 #endif
1026                         break;
1027                 default:
1028                         popts->ba_intlv_ctl = 0;
1029                         break;
1030                 }
1031         }
1032
1033         if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1034                 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1035                         popts->addr_hash = 0;
1036                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1037                                                "true", buf))
1038                         popts->addr_hash = 1;
1039         }
1040
1041         if (pdimm[0].n_ranks == 4)
1042                 popts->quad_rank_present = 1;
1043
1044         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1045         if (popts->registered_dimm_en) {
1046                 popts->rcw_override = 1;
1047                 popts->rcw_1 = 0x000a5a00;
1048                 if (ddr_freq <= 800)
1049                         popts->rcw_2 = 0x00000000;
1050                 else if (ddr_freq <= 1066)
1051                         popts->rcw_2 = 0x00100000;
1052                 else if (ddr_freq <= 1333)
1053                         popts->rcw_2 = 0x00200000;
1054                 else
1055                         popts->rcw_2 = 0x00300000;
1056         }
1057
1058         fsl_ddr_board_options(popts, pdimm, ctrl_num);
1059
1060         return 0;
1061 }
1062
1063 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1064 {
1065         int i, j, k, check_n_ranks, intlv_invalid = 0;
1066         unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1067         unsigned long long check_rank_density;
1068         struct dimm_params_s *dimm;
1069         int first_ctrl = pinfo->first_ctrl;
1070         int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1071
1072         /*
1073          * Check if all controllers are configured for memory
1074          * controller interleaving. Identical dimms are recommended. At least
1075          * the size, row and col address should be checked.
1076          */
1077         j = 0;
1078         check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1079         check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1080         check_n_row_addr =  pinfo->dimm_params[first_ctrl][0].n_row_addr;
1081         check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1082         check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1083         for (i = first_ctrl; i <= last_ctrl; i++) {
1084                 dimm = &pinfo->dimm_params[i][0];
1085                 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1086                         continue;
1087                 } else if (((check_rank_density != dimm->rank_density) ||
1088                      (check_n_ranks != dimm->n_ranks) ||
1089                      (check_n_row_addr != dimm->n_row_addr) ||
1090                      (check_n_col_addr != dimm->n_col_addr) ||
1091                      (check_intlv !=
1092                         pinfo->memctl_opts[i].memctl_interleaving_mode))){
1093                         intlv_invalid = 1;
1094                         break;
1095                 } else {
1096                         j++;
1097                 }
1098
1099         }
1100         if (intlv_invalid) {
1101                 for (i = first_ctrl; i <= last_ctrl; i++)
1102                         pinfo->memctl_opts[i].memctl_interleaving = 0;
1103                 printf("Not all DIMMs are identical. "
1104                         "Memory controller interleaving disabled.\n");
1105         } else {
1106                 switch (check_intlv) {
1107                 case FSL_DDR_256B_INTERLEAVING:
1108                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1109                 case FSL_DDR_PAGE_INTERLEAVING:
1110                 case FSL_DDR_BANK_INTERLEAVING:
1111                 case FSL_DDR_SUPERBANK_INTERLEAVING:
1112 #if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1113                                 k = 2;
1114 #else
1115                                 k = CONFIG_NUM_DDR_CONTROLLERS;
1116 #endif
1117                         break;
1118                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1119                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1120                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1121                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1122                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1123                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1124                 default:
1125                         k = CONFIG_NUM_DDR_CONTROLLERS;
1126                         break;
1127                 }
1128                 debug("%d of %d controllers are interleaving.\n", j, k);
1129                 if (j && (j != k)) {
1130                         for (i = first_ctrl; i <= last_ctrl; i++)
1131                                 pinfo->memctl_opts[i].memctl_interleaving = 0;
1132                         if ((last_ctrl - first_ctrl) > 1)
1133                                 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1134                 }
1135         }
1136         debug("Checking interleaving options completed\n");
1137 }
1138
1139 int fsl_use_spd(void)
1140 {
1141         int use_spd = 0;
1142
1143 #ifdef CONFIG_DDR_SPD
1144         char buffer[HWCONFIG_BUFFER_SIZE];
1145         char *buf = NULL;
1146
1147         /*
1148          * Extract hwconfig from environment since we have not properly setup
1149          * the environment but need it for ddr config params
1150          */
1151         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1152                 buf = buffer;
1153
1154         /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1155         if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1156                 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1157                         use_spd = 1;
1158                 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
1159                                                "fixed", buf))
1160                         use_spd = 0;
1161                 else
1162                         use_spd = 1;
1163         } else
1164                 use_spd = 1;
1165 #endif
1166
1167         return use_spd;
1168 }