1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008 Freescale Semiconductor, Inc.
9 #include <fsl_ddr_sdram.h>
10 #include <linux/delay.h>
12 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
13 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
16 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
17 unsigned int ctrl_num, int step)
20 struct ccsr_ddr __iomem *ddr;
24 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
27 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
30 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
34 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
36 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
37 out_be32(&ddr->cs0_config, regs->cs[i].config);
40 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
41 out_be32(&ddr->cs1_config, regs->cs[i].config);
44 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
45 out_be32(&ddr->cs2_config, regs->cs[i].config);
48 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
49 out_be32(&ddr->cs3_config, regs->cs[i].config);
53 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
54 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
55 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
56 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
57 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
58 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
59 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
60 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
61 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
62 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
63 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
64 out_be32(&ddr->init_addr, regs->ddr_init_addr);
65 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
70 * 200 painful micro-seconds must elapse between
71 * the DDR clock setup and the DDR config enable.
74 asm volatile("sync;isync");
76 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
79 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
81 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
82 udelay(10000); /* throttle polling rate */