1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
8 #include <asm/processor.h>
9 #include <fsl_ddr_sdram.h>
11 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
12 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
15 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
16 unsigned int ctrl_num, int step)
19 struct ccsr_ddr __iomem *ddr =
20 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
22 #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
23 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
28 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
32 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
34 * Set the DDR IO receiver to an acceptable bias point.
38 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
39 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
40 SDRAM_CFG_SDRAM_TYPE_DDR2)
41 out_be32(&gur->ddrioovcr, 0x90000000);
43 out_be32(&gur->ddrioovcr, 0xA8000000);
47 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
50 out_be32(&ddr->cs0_config, regs->cs[i].config);
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
54 out_be32(&ddr->cs1_config, regs->cs[i].config);
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
58 out_be32(&ddr->cs2_config, regs->cs[i].config);
61 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
62 out_be32(&ddr->cs3_config, regs->cs[i].config);
66 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
67 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
68 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
69 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
70 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
71 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
72 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
73 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
74 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
75 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
76 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
77 out_be32(&ddr->init_addr, regs->ddr_init_addr);
78 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
81 * 200 painful micro-seconds must elapse between
82 * the DDR clock setup and the DDR config enable.
85 asm volatile("sync;isync");
87 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
89 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
90 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
91 udelay(10000); /* throttle polling rate */