drivers/ddr/fsl/interactive.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2010-2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP Semiconductor
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  *         York Sun [at freescale.com]
  12  */
  13
  14 #include <common.h>
  15 #include <cli.h>
  16 #include <command.h>
  17 #include <env.h>
  18 #include <linux/ctype.h>
  19 #include <asm/types.h>
  20 #include <asm/io.h>
  21
  22 #include <fsl_ddr_sdram.h>
  23 #include <fsl_ddr.h>
  24
  25 /* Option parameter Structures */
  26 struct options_string {
  27         const char *option_name;
  28         size_t offset;
  29         unsigned int size;
  30         const char printhex;
  31 };
  32
  33 static unsigned int picos_to_mhz(unsigned int picos)
  34 {
  35         return 1000000 / picos;
  36 }
  37
  38 static void print_option_table(const struct options_string *table,
  39                          int table_size,
  40                          const void *base)
  41 {
  42         unsigned int i;
  43         unsigned int *ptr;
  44         unsigned long long *ptr_l;
  45
  46         for (i = 0; i < table_size; i++) {
  47                 switch (table[i].size) {
  48                 case 4:
  49                         ptr = (unsigned int *) (base + table[i].offset);
  50                         if (table[i].printhex) {
  51                                 printf("%s = 0x%08X\n",
  52                                         table[i].option_name, *ptr);
  53                         } else {
  54                                 printf("%s = %u\n",
  55                                         table[i].option_name, *ptr);
  56                         }
  57                         break;
  58                 case 8:
  59                         ptr_l = (unsigned long long *) (base + table[i].offset);
  60                         printf("%s = %llu\n",
  61                                 table[i].option_name, *ptr_l);
  62                         break;
  63                 default:
  64                         printf("Unrecognized size!\n");
  65                         break;
  66                 }
  67         }
  68 }
  69
  70 static int handle_option_table(const struct options_string *table,
  71                          int table_size,
  72                          void *base,
  73                          const char *opt,
  74                          const char *val)
  75 {
  76         unsigned int i;
  77         unsigned int value, *ptr;
  78         unsigned long long value_l, *ptr_l;
  79
  80         for (i = 0; i < table_size; i++) {
  81                 if (strcmp(table[i].option_name, opt) != 0)
  82                         continue;
  83                 switch (table[i].size) {
  84                 case 4:
  85                         value = simple_strtoul(val, NULL, 0);
  86                         ptr = base + table[i].offset;
  87                         *ptr = value;
  88                         break;
  89                 case 8:
  90                         value_l = simple_strtoull(val, NULL, 0);
  91                         ptr_l = base + table[i].offset;
  92                         *ptr_l = value_l;
  93                         break;
  94                 default:
  95                         printf("Unrecognized size!\n");
  96                         break;
  97                 }
  98                 return 1;
  99         }
 100
 101         return 0;
 102 }
 103
 104 static void fsl_ddr_generic_edit(void *pdata,
 105                            void *pend,
 106                            unsigned int element_size,
 107                            unsigned int element_num,
 108                            unsigned int value)
 109 {
 110         char *pcdata = (char *)pdata;           /* BIG ENDIAN ONLY */
 111
 112         pcdata += element_num * element_size;
 113         if ((pcdata + element_size) > (char *) pend) {
 114                 printf("trying to write past end of data\n");
 115                 return;
 116         }
 117
 118         switch (element_size) {
 119         case 1:
 120                 __raw_writeb(value, pcdata);
 121                 break;
 122         case 2:
 123                 __raw_writew(value, pcdata);
 124                 break;
 125         case 4:
 126                 __raw_writel(value, pcdata);
 127                 break;
 128         default:
 129                 printf("unexpected element size %u\n", element_size);
 130                 break;
 131         }
 132 }
 133
 134 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
 135                        unsigned int ctrl_num,
 136                        unsigned int dimm_num,
 137                        unsigned int element_num,
 138                        unsigned int value)
 139 {
 140         generic_spd_eeprom_t *pspd;
 141
 142         pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
 143         fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
 144 }
 145
 146 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
 147         sizeof((common_timing_params_t *)0)->x, 0}
 148
 149 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 150                                         unsigned int ctrl_num,
 151                                         const char *optname_str,
 152                                         const char *value_str)
 153 {
 154         common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 155
 156         static const struct options_string options[] = {
 157                 COMMON_TIMING(tckmin_x_ps),
 158                 COMMON_TIMING(tckmax_ps),
 159 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 160                 COMMON_TIMING(taamin_ps),
 161 #endif
 162                 COMMON_TIMING(trcd_ps),
 163                 COMMON_TIMING(trp_ps),
 164                 COMMON_TIMING(tras_ps),
 165
 166 #ifdef CONFIG_SYS_FSL_DDR4
 167                 COMMON_TIMING(trfc1_ps),
 168                 COMMON_TIMING(trfc2_ps),
 169                 COMMON_TIMING(trfc4_ps),
 170                 COMMON_TIMING(trrds_ps),
 171                 COMMON_TIMING(trrdl_ps),
 172                 COMMON_TIMING(tccdl_ps),
 173                 COMMON_TIMING(trfc_slr_ps),
 174 #else
 175                 COMMON_TIMING(twtr_ps),
 176                 COMMON_TIMING(trfc_ps),
 177                 COMMON_TIMING(trrd_ps),
 178                 COMMON_TIMING(trtp_ps),
 179 #endif
 180                 COMMON_TIMING(twr_ps),
 181                 COMMON_TIMING(trc_ps),
 182                 COMMON_TIMING(refresh_rate_ps),
 183                 COMMON_TIMING(extended_op_srt),
 184 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 185                 COMMON_TIMING(tis_ps),
 186                 COMMON_TIMING(tih_ps),
 187                 COMMON_TIMING(tds_ps),
 188                 COMMON_TIMING(tdh_ps),
 189                 COMMON_TIMING(tdqsq_max_ps),
 190                 COMMON_TIMING(tqhs_ps),
 191 #endif
 192                 COMMON_TIMING(ndimms_present),
 193                 COMMON_TIMING(lowest_common_spd_caslat),
 194                 COMMON_TIMING(highest_common_derated_caslat),
 195                 COMMON_TIMING(additive_latency),
 196                 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
 197                 COMMON_TIMING(all_dimms_registered),
 198                 COMMON_TIMING(all_dimms_unbuffered),
 199                 COMMON_TIMING(all_dimms_ecc_capable),
 200                 COMMON_TIMING(total_mem),
 201                 COMMON_TIMING(base_address),
 202         };
 203         static const unsigned int n_opts = ARRAY_SIZE(options);
 204
 205         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 206                 return;
 207
 208         printf("Error: couldn't find option string %s\n", optname_str);
 209 }
 210
 211 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
 212         sizeof((dimm_params_t *)0)->x, 0}
 213 #define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
 214         sizeof((dimm_params_t *)0)->x, 1}
 215
 216 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 217                                    unsigned int ctrl_num,
 218                                    unsigned int dimm_num,
 219                                    const char *optname_str,
 220                                    const char *value_str)
 221 {
 222         dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
 223
 224         static const struct options_string options[] = {
 225                 DIMM_PARM(n_ranks),
 226                 DIMM_PARM(data_width),
 227                 DIMM_PARM(primary_sdram_width),
 228                 DIMM_PARM(ec_sdram_width),
 229                 DIMM_PARM(package_3ds),
 230                 DIMM_PARM(registered_dimm),
 231                 DIMM_PARM(mirrored_dimm),
 232                 DIMM_PARM(device_width),
 233
 234                 DIMM_PARM(n_row_addr),
 235                 DIMM_PARM(n_col_addr),
 236                 DIMM_PARM(edc_config),
 237 #ifdef CONFIG_SYS_FSL_DDR4
 238                 DIMM_PARM(bank_addr_bits),
 239                 DIMM_PARM(bank_group_bits),
 240                 DIMM_PARM_HEX(die_density),
 241 #else
 242                 DIMM_PARM(n_banks_per_sdram_device),
 243 #endif
 244                 DIMM_PARM(burst_lengths_bitmask),
 245
 246                 DIMM_PARM(tckmin_x_ps),
 247                 DIMM_PARM(tckmin_x_minus_1_ps),
 248                 DIMM_PARM(tckmin_x_minus_2_ps),
 249                 DIMM_PARM(tckmax_ps),
 250
 251                 DIMM_PARM(caslat_x),
 252                 DIMM_PARM(caslat_x_minus_1),
 253                 DIMM_PARM(caslat_x_minus_2),
 254
 255                 DIMM_PARM(caslat_lowest_derated),
 256
 257                 DIMM_PARM(trcd_ps),
 258                 DIMM_PARM(trp_ps),
 259                 DIMM_PARM(tras_ps),
 260 #ifdef CONFIG_SYS_FSL_DDR4
 261                 DIMM_PARM(trfc1_ps),
 262                 DIMM_PARM(trfc2_ps),
 263                 DIMM_PARM(trfc4_ps),
 264                 DIMM_PARM(trrds_ps),
 265                 DIMM_PARM(trrdl_ps),
 266                 DIMM_PARM(tccdl_ps),
 267                 DIMM_PARM(trfc_slr_ps),
 268 #else
 269                 DIMM_PARM(twr_ps),
 270                 DIMM_PARM(twtr_ps),
 271                 DIMM_PARM(trfc_ps),
 272                 DIMM_PARM(trrd_ps),
 273                 DIMM_PARM(trtp_ps),
 274 #endif
 275                 DIMM_PARM(trc_ps),
 276                 DIMM_PARM(refresh_rate_ps),
 277                 DIMM_PARM(extended_op_srt),
 278
 279 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 280                 DIMM_PARM(tis_ps),
 281                 DIMM_PARM(tih_ps),
 282                 DIMM_PARM(tds_ps),
 283                 DIMM_PARM(tdh_ps),
 284                 DIMM_PARM(tdqsq_max_ps),
 285                 DIMM_PARM(tqhs_ps),
 286 #endif
 287 #ifdef CONFIG_SYS_FSL_DDR4
 288                 DIMM_PARM_HEX(dq_mapping[0]),
 289                 DIMM_PARM_HEX(dq_mapping[1]),
 290                 DIMM_PARM_HEX(dq_mapping[2]),
 291                 DIMM_PARM_HEX(dq_mapping[3]),
 292                 DIMM_PARM_HEX(dq_mapping[4]),
 293                 DIMM_PARM_HEX(dq_mapping[5]),
 294                 DIMM_PARM_HEX(dq_mapping[6]),
 295                 DIMM_PARM_HEX(dq_mapping[7]),
 296                 DIMM_PARM_HEX(dq_mapping[8]),
 297                 DIMM_PARM_HEX(dq_mapping[9]),
 298                 DIMM_PARM_HEX(dq_mapping[10]),
 299                 DIMM_PARM_HEX(dq_mapping[11]),
 300                 DIMM_PARM_HEX(dq_mapping[12]),
 301                 DIMM_PARM_HEX(dq_mapping[13]),
 302                 DIMM_PARM_HEX(dq_mapping[14]),
 303                 DIMM_PARM_HEX(dq_mapping[15]),
 304                 DIMM_PARM_HEX(dq_mapping[16]),
 305                 DIMM_PARM_HEX(dq_mapping[17]),
 306                 DIMM_PARM(dq_mapping_ors),
 307 #endif
 308                 DIMM_PARM(rank_density),
 309                 DIMM_PARM(capacity),
 310                 DIMM_PARM(base_address),
 311         };
 312
 313         static const unsigned int n_opts = ARRAY_SIZE(options);
 314
 315         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 316                 return;
 317
 318         printf("couldn't find option string %s\n", optname_str);
 319 }
 320
 321 static void print_dimm_parameters(const dimm_params_t *pdimm)
 322 {
 323         static const struct options_string options[] = {
 324                 DIMM_PARM(n_ranks),
 325                 DIMM_PARM(data_width),
 326                 DIMM_PARM(primary_sdram_width),
 327                 DIMM_PARM(ec_sdram_width),
 328                 DIMM_PARM(package_3ds),
 329                 DIMM_PARM(registered_dimm),
 330                 DIMM_PARM(mirrored_dimm),
 331                 DIMM_PARM(device_width),
 332
 333                 DIMM_PARM(n_row_addr),
 334                 DIMM_PARM(n_col_addr),
 335                 DIMM_PARM(edc_config),
 336 #ifdef CONFIG_SYS_FSL_DDR4
 337                 DIMM_PARM(bank_addr_bits),
 338                 DIMM_PARM(bank_group_bits),
 339                 DIMM_PARM_HEX(die_density),
 340 #else
 341                 DIMM_PARM(n_banks_per_sdram_device),
 342 #endif
 343
 344                 DIMM_PARM(tckmin_x_ps),
 345                 DIMM_PARM(tckmin_x_minus_1_ps),
 346                 DIMM_PARM(tckmin_x_minus_2_ps),
 347                 DIMM_PARM(tckmax_ps),
 348
 349                 DIMM_PARM(caslat_x),
 350                 DIMM_PARM_HEX(caslat_x),
 351                 DIMM_PARM(taa_ps),
 352                 DIMM_PARM(caslat_x_minus_1),
 353                 DIMM_PARM(caslat_x_minus_2),
 354                 DIMM_PARM(caslat_lowest_derated),
 355
 356                 DIMM_PARM(trcd_ps),
 357                 DIMM_PARM(trp_ps),
 358                 DIMM_PARM(tras_ps),
 359 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 360                 DIMM_PARM(tfaw_ps),
 361 #endif
 362 #ifdef CONFIG_SYS_FSL_DDR4
 363                 DIMM_PARM(trfc1_ps),
 364                 DIMM_PARM(trfc2_ps),
 365                 DIMM_PARM(trfc4_ps),
 366                 DIMM_PARM(trrds_ps),
 367                 DIMM_PARM(trrdl_ps),
 368                 DIMM_PARM(tccdl_ps),
 369                 DIMM_PARM(trfc_slr_ps),
 370 #else
 371                 DIMM_PARM(twr_ps),
 372                 DIMM_PARM(twtr_ps),
 373                 DIMM_PARM(trfc_ps),
 374                 DIMM_PARM(trrd_ps),
 375                 DIMM_PARM(trtp_ps),
 376 #endif
 377                 DIMM_PARM(trc_ps),
 378                 DIMM_PARM(refresh_rate_ps),
 379
 380 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 381                 DIMM_PARM(tis_ps),
 382                 DIMM_PARM(tih_ps),
 383                 DIMM_PARM(tds_ps),
 384                 DIMM_PARM(tdh_ps),
 385                 DIMM_PARM(tdqsq_max_ps),
 386                 DIMM_PARM(tqhs_ps),
 387 #endif
 388 #ifdef CONFIG_SYS_FSL_DDR4
 389                 DIMM_PARM_HEX(dq_mapping[0]),
 390                 DIMM_PARM_HEX(dq_mapping[1]),
 391                 DIMM_PARM_HEX(dq_mapping[2]),
 392                 DIMM_PARM_HEX(dq_mapping[3]),
 393                 DIMM_PARM_HEX(dq_mapping[4]),
 394                 DIMM_PARM_HEX(dq_mapping[5]),
 395                 DIMM_PARM_HEX(dq_mapping[6]),
 396                 DIMM_PARM_HEX(dq_mapping[7]),
 397                 DIMM_PARM_HEX(dq_mapping[8]),
 398                 DIMM_PARM_HEX(dq_mapping[9]),
 399                 DIMM_PARM_HEX(dq_mapping[10]),
 400                 DIMM_PARM_HEX(dq_mapping[11]),
 401                 DIMM_PARM_HEX(dq_mapping[12]),
 402                 DIMM_PARM_HEX(dq_mapping[13]),
 403                 DIMM_PARM_HEX(dq_mapping[14]),
 404                 DIMM_PARM_HEX(dq_mapping[15]),
 405                 DIMM_PARM_HEX(dq_mapping[16]),
 406                 DIMM_PARM_HEX(dq_mapping[17]),
 407                 DIMM_PARM(dq_mapping_ors),
 408 #endif
 409         };
 410         static const unsigned int n_opts = ARRAY_SIZE(options);
 411
 412         if (pdimm->n_ranks == 0) {
 413                 printf("DIMM not present\n");
 414                 return;
 415         }
 416         printf("DIMM organization parameters:\n");
 417         printf("module part name = %s\n", pdimm->mpart);
 418         printf("rank_density = %llu bytes (%llu megabytes)\n",
 419                pdimm->rank_density, pdimm->rank_density / 0x100000);
 420         printf("capacity = %llu bytes (%llu megabytes)\n",
 421                pdimm->capacity, pdimm->capacity / 0x100000);
 422         printf("burst_lengths_bitmask = %02X\n",
 423                pdimm->burst_lengths_bitmask);
 424         printf("base_addresss = %llu (%08llX %08llX)\n",
 425                pdimm->base_address,
 426                (pdimm->base_address >> 32),
 427                pdimm->base_address & 0xFFFFFFFF);
 428         print_option_table(options, n_opts, pdimm);
 429 }
 430
 431 static void print_lowest_common_dimm_parameters(
 432                 const common_timing_params_t *plcd_dimm_params)
 433 {
 434         static const struct options_string options[] = {
 435 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 436                 COMMON_TIMING(taamin_ps),
 437 #endif
 438                 COMMON_TIMING(trcd_ps),
 439                 COMMON_TIMING(trp_ps),
 440                 COMMON_TIMING(tras_ps),
 441 #ifdef CONFIG_SYS_FSL_DDR4
 442                 COMMON_TIMING(trfc1_ps),
 443                 COMMON_TIMING(trfc2_ps),
 444                 COMMON_TIMING(trfc4_ps),
 445                 COMMON_TIMING(trrds_ps),
 446                 COMMON_TIMING(trrdl_ps),
 447                 COMMON_TIMING(tccdl_ps),
 448                 COMMON_TIMING(trfc_slr_ps),
 449 #else
 450                 COMMON_TIMING(twtr_ps),
 451                 COMMON_TIMING(trfc_ps),
 452                 COMMON_TIMING(trrd_ps),
 453                 COMMON_TIMING(trtp_ps),
 454 #endif
 455                 COMMON_TIMING(twr_ps),
 456                 COMMON_TIMING(trc_ps),
 457                 COMMON_TIMING(refresh_rate_ps),
 458                 COMMON_TIMING(extended_op_srt),
 459 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 460                 COMMON_TIMING(tis_ps),
 461                 COMMON_TIMING(tih_ps),
 462                 COMMON_TIMING(tds_ps),
 463                 COMMON_TIMING(tdh_ps),
 464                 COMMON_TIMING(tdqsq_max_ps),
 465                 COMMON_TIMING(tqhs_ps),
 466 #endif
 467                 COMMON_TIMING(lowest_common_spd_caslat),
 468                 COMMON_TIMING(highest_common_derated_caslat),
 469                 COMMON_TIMING(additive_latency),
 470                 COMMON_TIMING(ndimms_present),
 471                 COMMON_TIMING(all_dimms_registered),
 472                 COMMON_TIMING(all_dimms_unbuffered),
 473                 COMMON_TIMING(all_dimms_ecc_capable),
 474         };
 475         static const unsigned int n_opts = ARRAY_SIZE(options);
 476
 477         /* Clock frequencies */
 478         printf("tckmin_x_ps = %u (%u MHz)\n",
 479                plcd_dimm_params->tckmin_x_ps,
 480                picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
 481         printf("tckmax_ps = %u (%u MHz)\n",
 482                plcd_dimm_params->tckmax_ps,
 483                picos_to_mhz(plcd_dimm_params->tckmax_ps));
 484         printf("all_dimms_burst_lengths_bitmask = %02X\n",
 485                plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 486
 487         print_option_table(options, n_opts, plcd_dimm_params);
 488
 489         printf("total_mem = %llu (%llu megabytes)\n",
 490                plcd_dimm_params->total_mem,
 491                plcd_dimm_params->total_mem / 0x100000);
 492         printf("base_address = %llu (%llu megabytes)\n",
 493                plcd_dimm_params->base_address,
 494                plcd_dimm_params->base_address / 0x100000);
 495 }
 496
 497 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
 498         sizeof((memctl_options_t *)0)->x, 0}
 499 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
 500         offsetof(memctl_options_t, cs_local_opts[x].y), \
 501         sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
 502
 503 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 504                            unsigned int ctl_num,
 505                            const char *optname_str,
 506                            const char *value_str)
 507 {
 508         memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
 509         /*
 510          * This array all on the stack and *computed* each time this
 511          * function is rung.
 512          */
 513         static const struct options_string options[] = {
 514                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 515                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 516 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 517                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 518                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 519 #endif
 520 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 521                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 522                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 523 #endif
 524 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 525                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 526                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 527 #endif
 528 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 529                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 530                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 531 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 532                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 533                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 534 #endif
 535 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 536                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 537                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 538 #endif
 539 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 540                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 541                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 542 #endif
 543 #endif
 544                 CTRL_OPTIONS(memctl_interleaving),
 545                 CTRL_OPTIONS(memctl_interleaving_mode),
 546                 CTRL_OPTIONS(ba_intlv_ctl),
 547                 CTRL_OPTIONS(ecc_mode),
 548                 CTRL_OPTIONS(ecc_init_using_memctl),
 549                 CTRL_OPTIONS(dqs_config),
 550                 CTRL_OPTIONS(self_refresh_in_sleep),
 551                 CTRL_OPTIONS(dynamic_power),
 552                 CTRL_OPTIONS(data_bus_width),
 553                 CTRL_OPTIONS(burst_length),
 554                 CTRL_OPTIONS(cas_latency_override),
 555                 CTRL_OPTIONS(cas_latency_override_value),
 556                 CTRL_OPTIONS(use_derated_caslat),
 557                 CTRL_OPTIONS(additive_latency_override),
 558                 CTRL_OPTIONS(additive_latency_override_value),
 559                 CTRL_OPTIONS(clk_adjust),
 560                 CTRL_OPTIONS(cpo_override),
 561                 CTRL_OPTIONS(write_data_delay),
 562                 CTRL_OPTIONS(half_strength_driver_enable),
 563
 564                 /*
 565                  * These can probably be changed to 2T_EN and 3T_EN
 566                  * (using a leading numerical character) without problem
 567                  */
 568                 CTRL_OPTIONS(twot_en),
 569                 CTRL_OPTIONS(threet_en),
 570                 CTRL_OPTIONS(mirrored_dimm),
 571                 CTRL_OPTIONS(ap_en),
 572                 CTRL_OPTIONS(x4_en),
 573                 CTRL_OPTIONS(package_3ds),
 574                 CTRL_OPTIONS(bstopre),
 575                 CTRL_OPTIONS(wrlvl_override),
 576                 CTRL_OPTIONS(wrlvl_sample),
 577                 CTRL_OPTIONS(wrlvl_start),
 578                 CTRL_OPTIONS(cswl_override),
 579                 CTRL_OPTIONS(rcw_override),
 580                 CTRL_OPTIONS(rcw_1),
 581                 CTRL_OPTIONS(rcw_2),
 582                 CTRL_OPTIONS(rcw_3),
 583                 CTRL_OPTIONS(ddr_cdr1),
 584                 CTRL_OPTIONS(ddr_cdr2),
 585                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 586                 CTRL_OPTIONS(trwt_override),
 587                 CTRL_OPTIONS(trwt),
 588                 CTRL_OPTIONS(rtt_override),
 589                 CTRL_OPTIONS(rtt_override_value),
 590                 CTRL_OPTIONS(rtt_wr_override_value),
 591         };
 592
 593         static const unsigned int n_opts = ARRAY_SIZE(options);
 594
 595         if (handle_option_table(options, n_opts, p,
 596                                         optname_str, value_str))
 597                 return;
 598
 599         printf("couldn't find option string %s\n", optname_str);
 600 }
 601
 602 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
 603         sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
 604 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
 605         offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
 606         sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
 607
 608 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 609 {
 610         unsigned int i;
 611         static const struct options_string options[] = {
 612                 CFG_REGS_CS(0, bnds),
 613                 CFG_REGS_CS(0, config),
 614                 CFG_REGS_CS(0, config_2),
 615 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 616                 CFG_REGS_CS(1, bnds),
 617                 CFG_REGS_CS(1, config),
 618                 CFG_REGS_CS(1, config_2),
 619 #endif
 620 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 621                 CFG_REGS_CS(2, bnds),
 622                 CFG_REGS_CS(2, config),
 623                 CFG_REGS_CS(2, config_2),
 624 #endif
 625 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 626                 CFG_REGS_CS(3, bnds),
 627                 CFG_REGS_CS(3, config),
 628                 CFG_REGS_CS(3, config_2),
 629 #endif
 630                 CFG_REGS(timing_cfg_3),
 631                 CFG_REGS(timing_cfg_0),
 632                 CFG_REGS(timing_cfg_1),
 633                 CFG_REGS(timing_cfg_2),
 634                 CFG_REGS(ddr_sdram_cfg),
 635                 CFG_REGS(ddr_sdram_cfg_2),
 636                 CFG_REGS(ddr_sdram_cfg_3),
 637                 CFG_REGS(ddr_sdram_mode),
 638                 CFG_REGS(ddr_sdram_mode_2),
 639                 CFG_REGS(ddr_sdram_mode_3),
 640                 CFG_REGS(ddr_sdram_mode_4),
 641                 CFG_REGS(ddr_sdram_mode_5),
 642                 CFG_REGS(ddr_sdram_mode_6),
 643                 CFG_REGS(ddr_sdram_mode_7),
 644                 CFG_REGS(ddr_sdram_mode_8),
 645 #ifdef CONFIG_SYS_FSL_DDR4
 646                 CFG_REGS(ddr_sdram_mode_9),
 647                 CFG_REGS(ddr_sdram_mode_10),
 648                 CFG_REGS(ddr_sdram_mode_11),
 649                 CFG_REGS(ddr_sdram_mode_12),
 650                 CFG_REGS(ddr_sdram_mode_13),
 651                 CFG_REGS(ddr_sdram_mode_14),
 652                 CFG_REGS(ddr_sdram_mode_15),
 653                 CFG_REGS(ddr_sdram_mode_16),
 654 #endif
 655                 CFG_REGS(ddr_sdram_interval),
 656                 CFG_REGS(ddr_data_init),
 657                 CFG_REGS(ddr_sdram_clk_cntl),
 658                 CFG_REGS(ddr_init_addr),
 659                 CFG_REGS(ddr_init_ext_addr),
 660                 CFG_REGS(timing_cfg_4),
 661                 CFG_REGS(timing_cfg_5),
 662 #ifdef CONFIG_SYS_FSL_DDR4
 663                 CFG_REGS(timing_cfg_6),
 664                 CFG_REGS(timing_cfg_7),
 665                 CFG_REGS(timing_cfg_8),
 666                 CFG_REGS(timing_cfg_9),
 667 #endif
 668                 CFG_REGS(ddr_zq_cntl),
 669                 CFG_REGS(ddr_wrlvl_cntl),
 670                 CFG_REGS(ddr_wrlvl_cntl_2),
 671                 CFG_REGS(ddr_wrlvl_cntl_3),
 672                 CFG_REGS(ddr_sr_cntr),
 673                 CFG_REGS(ddr_sdram_rcw_1),
 674                 CFG_REGS(ddr_sdram_rcw_2),
 675                 CFG_REGS(ddr_sdram_rcw_3),
 676                 CFG_REGS(ddr_cdr1),
 677                 CFG_REGS(ddr_cdr2),
 678                 CFG_REGS(dq_map_0),
 679                 CFG_REGS(dq_map_1),
 680                 CFG_REGS(dq_map_2),
 681                 CFG_REGS(dq_map_3),
 682                 CFG_REGS(err_disable),
 683                 CFG_REGS(err_int_en),
 684                 CFG_REGS(ddr_eor),
 685         };
 686         static const unsigned int n_opts = ARRAY_SIZE(options);
 687
 688         print_option_table(options, n_opts, ddr);
 689
 690         for (i = 0; i < 64; i++)
 691                 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 692 }
 693
 694 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 695                         unsigned int ctrl_num,
 696                         const char *regname,
 697                         const char *value_str)
 698 {
 699         unsigned int i;
 700         fsl_ddr_cfg_regs_t *ddr;
 701         char buf[20];
 702         static const struct options_string options[] = {
 703                 CFG_REGS_CS(0, bnds),
 704                 CFG_REGS_CS(0, config),
 705                 CFG_REGS_CS(0, config_2),
 706 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 707                 CFG_REGS_CS(1, bnds),
 708                 CFG_REGS_CS(1, config),
 709                 CFG_REGS_CS(1, config_2),
 710 #endif
 711 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 712                 CFG_REGS_CS(2, bnds),
 713                 CFG_REGS_CS(2, config),
 714                 CFG_REGS_CS(2, config_2),
 715 #endif
 716 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 717                 CFG_REGS_CS(3, bnds),
 718                 CFG_REGS_CS(3, config),
 719                 CFG_REGS_CS(3, config_2),
 720 #endif
 721                 CFG_REGS(timing_cfg_3),
 722                 CFG_REGS(timing_cfg_0),
 723                 CFG_REGS(timing_cfg_1),
 724                 CFG_REGS(timing_cfg_2),
 725                 CFG_REGS(ddr_sdram_cfg),
 726                 CFG_REGS(ddr_sdram_cfg_2),
 727                 CFG_REGS(ddr_sdram_cfg_3),
 728                 CFG_REGS(ddr_sdram_mode),
 729                 CFG_REGS(ddr_sdram_mode_2),
 730                 CFG_REGS(ddr_sdram_mode_3),
 731                 CFG_REGS(ddr_sdram_mode_4),
 732                 CFG_REGS(ddr_sdram_mode_5),
 733                 CFG_REGS(ddr_sdram_mode_6),
 734                 CFG_REGS(ddr_sdram_mode_7),
 735                 CFG_REGS(ddr_sdram_mode_8),
 736 #ifdef CONFIG_SYS_FSL_DDR4
 737                 CFG_REGS(ddr_sdram_mode_9),
 738                 CFG_REGS(ddr_sdram_mode_10),
 739                 CFG_REGS(ddr_sdram_mode_11),
 740                 CFG_REGS(ddr_sdram_mode_12),
 741                 CFG_REGS(ddr_sdram_mode_13),
 742                 CFG_REGS(ddr_sdram_mode_14),
 743                 CFG_REGS(ddr_sdram_mode_15),
 744                 CFG_REGS(ddr_sdram_mode_16),
 745 #endif
 746                 CFG_REGS(ddr_sdram_interval),
 747                 CFG_REGS(ddr_data_init),
 748                 CFG_REGS(ddr_sdram_clk_cntl),
 749                 CFG_REGS(ddr_init_addr),
 750                 CFG_REGS(ddr_init_ext_addr),
 751                 CFG_REGS(timing_cfg_4),
 752                 CFG_REGS(timing_cfg_5),
 753 #ifdef CONFIG_SYS_FSL_DDR4
 754                 CFG_REGS(timing_cfg_6),
 755                 CFG_REGS(timing_cfg_7),
 756                 CFG_REGS(timing_cfg_8),
 757                 CFG_REGS(timing_cfg_9),
 758 #endif
 759                 CFG_REGS(ddr_zq_cntl),
 760                 CFG_REGS(ddr_wrlvl_cntl),
 761                 CFG_REGS(ddr_wrlvl_cntl_2),
 762                 CFG_REGS(ddr_wrlvl_cntl_3),
 763                 CFG_REGS(ddr_sr_cntr),
 764                 CFG_REGS(ddr_sdram_rcw_1),
 765                 CFG_REGS(ddr_sdram_rcw_2),
 766                 CFG_REGS(ddr_sdram_rcw_3),
 767                 CFG_REGS(ddr_cdr1),
 768                 CFG_REGS(ddr_cdr2),
 769                 CFG_REGS(dq_map_0),
 770                 CFG_REGS(dq_map_1),
 771                 CFG_REGS(dq_map_2),
 772                 CFG_REGS(dq_map_3),
 773                 CFG_REGS(err_disable),
 774                 CFG_REGS(err_int_en),
 775                 CFG_REGS(ddr_sdram_rcw_2),
 776                 CFG_REGS(ddr_sdram_rcw_2),
 777                 CFG_REGS(ddr_eor),
 778         };
 779         static const unsigned int n_opts = ARRAY_SIZE(options);
 780
 781         debug("fsl_ddr_regs_edit: ctrl_num = %u, "
 782                 "regname = %s, value = %s\n",
 783                 ctrl_num, regname, value_str);
 784         if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
 785                 return;
 786
 787         ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
 788
 789         if (handle_option_table(options, n_opts, ddr, regname, value_str))
 790                 return;
 791
 792         for (i = 0; i < 64; i++) {
 793                 unsigned int value = simple_strtoul(value_str, NULL, 0);
 794                 sprintf(buf, "debug_%u", i + 1);
 795                 if (strcmp(buf, regname) == 0) {
 796                         ddr->debug[i] = value;
 797                         return;
 798                 }
 799         }
 800         printf("Error: couldn't find register string %s\n", regname);
 801 }
 802
 803 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
 804         sizeof((memctl_options_t *)0)->x, 1}
 805
 806 static void print_memctl_options(const memctl_options_t *popts)
 807 {
 808         static const struct options_string options[] = {
 809                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 810                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 811 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 812                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 813                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 814 #endif
 815 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 816                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 817                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 818 #endif
 819 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 820                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 821                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 822 #endif
 823 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 824                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 825                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 826 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 827                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 828                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 829 #endif
 830 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 831                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 832                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 833 #endif
 834 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 835                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 836                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 837 #endif
 838 #endif
 839                 CTRL_OPTIONS(memctl_interleaving),
 840                 CTRL_OPTIONS(memctl_interleaving_mode),
 841                 CTRL_OPTIONS_HEX(ba_intlv_ctl),
 842                 CTRL_OPTIONS(ecc_mode),
 843                 CTRL_OPTIONS(ecc_init_using_memctl),
 844                 CTRL_OPTIONS(dqs_config),
 845                 CTRL_OPTIONS(self_refresh_in_sleep),
 846                 CTRL_OPTIONS(dynamic_power),
 847                 CTRL_OPTIONS(data_bus_width),
 848                 CTRL_OPTIONS(burst_length),
 849                 CTRL_OPTIONS(cas_latency_override),
 850                 CTRL_OPTIONS(cas_latency_override_value),
 851                 CTRL_OPTIONS(use_derated_caslat),
 852                 CTRL_OPTIONS(additive_latency_override),
 853                 CTRL_OPTIONS(additive_latency_override_value),
 854                 CTRL_OPTIONS(clk_adjust),
 855                 CTRL_OPTIONS(cpo_override),
 856                 CTRL_OPTIONS(write_data_delay),
 857                 CTRL_OPTIONS(half_strength_driver_enable),
 858                 /*
 859                  * These can probably be changed to 2T_EN and 3T_EN
 860                  * (using a leading numerical character) without problem
 861                  */
 862                 CTRL_OPTIONS(twot_en),
 863                 CTRL_OPTIONS(threet_en),
 864                 CTRL_OPTIONS(registered_dimm_en),
 865                 CTRL_OPTIONS(mirrored_dimm),
 866                 CTRL_OPTIONS(ap_en),
 867                 CTRL_OPTIONS(x4_en),
 868                 CTRL_OPTIONS(package_3ds),
 869                 CTRL_OPTIONS(bstopre),
 870                 CTRL_OPTIONS(wrlvl_override),
 871                 CTRL_OPTIONS(wrlvl_sample),
 872                 CTRL_OPTIONS(wrlvl_start),
 873                 CTRL_OPTIONS_HEX(cswl_override),
 874                 CTRL_OPTIONS(rcw_override),
 875                 CTRL_OPTIONS_HEX(rcw_1),
 876                 CTRL_OPTIONS_HEX(rcw_2),
 877                 CTRL_OPTIONS_HEX(rcw_3),
 878                 CTRL_OPTIONS_HEX(ddr_cdr1),
 879                 CTRL_OPTIONS_HEX(ddr_cdr2),
 880                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 881                 CTRL_OPTIONS(trwt_override),
 882                 CTRL_OPTIONS(trwt),
 883                 CTRL_OPTIONS(rtt_override),
 884                 CTRL_OPTIONS(rtt_override_value),
 885                 CTRL_OPTIONS(rtt_wr_override_value),
 886         };
 887         static const unsigned int n_opts = ARRAY_SIZE(options);
 888
 889         print_option_table(options, n_opts, popts);
 890 }
 891
 892 #ifdef CONFIG_SYS_FSL_DDR1
 893 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
 894 {
 895         unsigned int i;
 896
 897         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 898                " spd->info_size,   *  0 # bytes written into serial memory *");
 899         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 900                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 901         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 902                " spd->mem_type,    *  2 Fundamental memory type *");
 903         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 904                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 905         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 906                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 907         printf("%-3d    : %02x %s\n", 5, spd->nrows,
 908                " spd->nrows        *  5 # of DIMM Banks *");
 909         printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
 910                " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
 911         printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
 912                " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
 913         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 914                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 915         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 916                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 917         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 918                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
 919         printf("%-3d    : %02x %s\n", 11, spd->config,
 920                " spd->config,      * 11 DIMM Configuration type *");
 921         printf("%-3d    : %02x %s\n", 12, spd->refresh,
 922                " spd->refresh,     * 12 Refresh Rate/Type *");
 923         printf("%-3d    : %02x %s\n", 13, spd->primw,
 924                " spd->primw,       * 13 Primary SDRAM Width *");
 925         printf("%-3d    : %02x %s\n", 14, spd->ecw,
 926                " spd->ecw,         * 14 Error Checking SDRAM width *");
 927         printf("%-3d    : %02x %s\n", 15, spd->min_delay,
 928                " spd->min_delay,   * 15 Back to Back Random Access *");
 929         printf("%-3d    : %02x %s\n", 16, spd->burstl,
 930                " spd->burstl,      * 16 Burst Lengths Supported *");
 931         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
 932                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
 933         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
 934                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
 935         printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
 936                " spd->cs_lat,      * 19 Chip Select Latency *");
 937         printf("%-3d    : %02x %s\n", 20, spd->write_lat,
 938                " spd->write_lat,   * 20 Write Latency/Recovery *");
 939         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
 940                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
 941         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
 942                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
 943         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
 944                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
 945         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
 946                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
 947         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
 948                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
 949         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
 950                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
 951         printf("%-3d    : %02x %s\n", 27, spd->trp,
 952                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
 953         printf("%-3d    : %02x %s\n", 28, spd->trrd,
 954                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
 955         printf("%-3d    : %02x %s\n", 29, spd->trcd,
 956                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
 957         printf("%-3d    : %02x %s\n", 30, spd->tras,
 958                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
 959         printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
 960                " spd->bank_dens,   * 31 Density of each bank on module *");
 961         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
 962                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
 963         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
 964                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
 965         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
 966                " spd->data_setup,  * 34 Data signal input setup time *");
 967         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
 968                " spd->data_hold,   * 35 Data signal input hold time *");
 969         printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
 970                " spd->res_36_40[0], * 36 Reserved / tWR *");
 971         printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
 972                " spd->res_36_40[1], * 37 Reserved / tWTR *");
 973         printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
 974                " spd->res_36_40[2], * 38 Reserved / tRTP *");
 975         printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
 976                " spd->res_36_40[3], * 39 Reserved / mem_probe *");
 977         printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
 978                " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
 979         printf("%-3d    : %02x %s\n", 41, spd->trc,
 980                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
 981         printf("%-3d    : %02x %s\n", 42, spd->trfc,
 982                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
 983         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
 984                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
 985         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
 986                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
 987         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
 988                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 989         printf("%-3d    : %02x %s\n", 46, spd->res_46,
 990                " spd->res_46,  * 46 Reserved/ PLL Relock time *");
 991         printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
 992                " spd->dimm_height  * 47 SDRAM DIMM Height *");
 993
 994         printf("%-3d-%3d: ",  48, 61);
 995
 996         for (i = 0; i < 14; i++)
 997                 printf("%02x", spd->res_48_61[i]);
 998
 999         printf(" * 48-61 IDD in SPD and Reserved space *\n");
1000
1001         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1002                " spd->spd_rev,     * 62 SPD Data Revision Code *");
1003         printf("%-3d    : %02x %s\n", 63, spd->cksum,
1004                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1005         printf("%-3d-%3d: ",  64, 71);
1006
1007         for (i = 0; i < 8; i++)
1008                 printf("%02x", spd->mid[i]);
1009
1010         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1011         printf("%-3d    : %02x %s\n", 72, spd->mloc,
1012                " spd->mloc,        * 72 Manufacturing Location *");
1013
1014         printf("%-3d-%3d: >>",  73, 90);
1015
1016         for (i = 0; i < 18; i++)
1017                 printf("%c", spd->mpart[i]);
1018
1019         printf("<<* 73 Manufacturer's Part Number *\n");
1020
1021         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1022                "* 91 Revision Code *");
1023         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1024                "* 93 Manufacturing Date *");
1025         printf("%-3d-%3d: ", 95, 98);
1026
1027         for (i = 0; i < 4; i++)
1028                 printf("%02x", spd->sernum[i]);
1029
1030         printf("* 95 Assembly Serial Number *\n");
1031
1032         printf("%-3d-%3d: ", 99, 127);
1033
1034         for (i = 0; i < 27; i++)
1035                 printf("%02x", spd->mspec[i]);
1036
1037         printf("* 99 Manufacturer Specific Data *\n");
1038 }
1039 #endif
1040
1041 #ifdef CONFIG_SYS_FSL_DDR2
1042 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
1043 {
1044         unsigned int i;
1045
1046         printf("%-3d    : %02x %s\n", 0, spd->info_size,
1047                " spd->info_size,   *  0 # bytes written into serial memory *");
1048         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
1049                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
1050         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
1051                " spd->mem_type,    *  2 Fundamental memory type *");
1052         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
1053                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
1054         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
1055                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
1056         printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
1057                " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
1058         printf("%-3d    : %02x %s\n", 6, spd->dataw,
1059                " spd->dataw,       *  6 Data Width of this assembly *");
1060         printf("%-3d    : %02x %s\n", 7, spd->res_7,
1061                " spd->res_7,       *  7 Reserved *");
1062         printf("%-3d    : %02x %s\n", 8, spd->voltage,
1063                " spd->voltage,     *  8 Voltage intf std of this assembly *");
1064         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
1065                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
1066         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
1067                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
1068         printf("%-3d    : %02x %s\n", 11, spd->config,
1069                " spd->config,      * 11 DIMM Configuration type *");
1070         printf("%-3d    : %02x %s\n", 12, spd->refresh,
1071                " spd->refresh,     * 12 Refresh Rate/Type *");
1072         printf("%-3d    : %02x %s\n", 13, spd->primw,
1073                " spd->primw,       * 13 Primary SDRAM Width *");
1074         printf("%-3d    : %02x %s\n", 14, spd->ecw,
1075                " spd->ecw,         * 14 Error Checking SDRAM width *");
1076         printf("%-3d    : %02x %s\n", 15, spd->res_15,
1077                " spd->res_15,      * 15 Reserved *");
1078         printf("%-3d    : %02x %s\n", 16, spd->burstl,
1079                " spd->burstl,      * 16 Burst Lengths Supported *");
1080         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
1081                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
1082         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
1083                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
1084         printf("%-3d    : %02x %s\n", 19, spd->mech_char,
1085                " spd->mech_char,   * 19 Mechanical Characteristics *");
1086         printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
1087                " spd->dimm_type,   * 20 DIMM type *");
1088         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
1089                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
1090         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
1091                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
1092         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
1093                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
1094         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
1095                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1096         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
1097                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
1098         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
1099                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1100         printf("%-3d    : %02x %s\n", 27, spd->trp,
1101                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
1102         printf("%-3d    : %02x %s\n", 28, spd->trrd,
1103                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
1104         printf("%-3d    : %02x %s\n", 29, spd->trcd,
1105                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
1106         printf("%-3d    : %02x %s\n", 30, spd->tras,
1107                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
1108         printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
1109                " spd->rank_dens,   * 31 Density of each rank on module *");
1110         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
1111                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
1112         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
1113                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
1114         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
1115                " spd->data_setup,  * 34 Data signal input setup time *");
1116         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
1117                " spd->data_hold,   * 35 Data signal input hold time *");
1118         printf("%-3d    : %02x %s\n", 36, spd->twr,
1119                " spd->twr,         * 36 Write Recovery time tWR *");
1120         printf("%-3d    : %02x %s\n", 37, spd->twtr,
1121                " spd->twtr,        * 37 Int write to read delay tWTR *");
1122         printf("%-3d    : %02x %s\n", 38, spd->trtp,
1123                " spd->trtp,        * 38 Int read to precharge delay tRTP *");
1124         printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
1125                " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
1126         printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
1127                " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1128         printf("%-3d    : %02x %s\n", 41, spd->trc,
1129                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
1130         printf("%-3d    : %02x %s\n", 42, spd->trfc,
1131                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
1132         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
1133                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
1134         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
1135                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
1136         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
1137                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
1138         printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
1139                " spd->pll_relock,  * 46 PLL Relock time *");
1140         printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
1141                " spd->t_casemax,    * 47 t_casemax *");
1142         printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
1143                " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
1144                "from Top (Case) to Ambient (Psi T-A DRAM) *");
1145         printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
1146                " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
1147                "Ambient due to Activate-Precharge/Mode Bits "
1148                "(DT0/Mode Bits) *)");
1149         printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
1150                " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
1151                "Ambient due to Precharge/Quiet Standby "
1152                "(DT2N/DT2Q) *");
1153         printf("%-3d    : %02x %s\n", 51, spd->dt2p,
1154                " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
1155                "Ambient due to Precharge Power-Down (DT2P) *");
1156         printf("%-3d    : %02x %s\n", 52, spd->dt3n,
1157                " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
1158                "Ambient due to Active Standby (DT3N) *");
1159         printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
1160                " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
1161                "Ambient due to Active Power-Down with Fast PDN Exit "
1162                "(DT3Pfast) *");
1163         printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
1164                " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
1165                "Ambient due to Active Power-Down with Slow PDN Exit "
1166                "(DT3Pslow) *");
1167         printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
1168                " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1169                "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1170                "(DT4R/DT4R4W Mode Bit) *");
1171         printf("%-3d    : %02x %s\n", 56, spd->dt5b,
1172                " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
1173                "Ambient due to Burst Refresh (DT5B) *");
1174         printf("%-3d    : %02x %s\n", 57, spd->dt7,
1175                " spd->dt7,         * 57 DRAM Case Temperature Rise from "
1176                "Ambient due to Bank Interleave Reads with "
1177                "Auto-Precharge (DT7) *");
1178         printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
1179                " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
1180                " Top (Case) to Ambient (Psi T-A PLL) *");
1181         printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
1182                " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
1183                " from Top (Case) to Ambient (Psi T-A Register) *");
1184         printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
1185                " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1186                "Ambient due to PLL Active (DT PLL Active) *");
1187         printf("%-3d    : %02x %s\n", 61, spd->dtregact,
1188                " spd->dtregact,    "
1189                "* 61 Register Case Temperature Rise from Ambient due to "
1190                "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1191         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1192                " spd->spd_rev,     * 62 SPD Data Revision Code *");
1193         printf("%-3d    : %02x %s\n", 63, spd->cksum,
1194                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1195
1196         printf("%-3d-%3d: ",  64, 71);
1197
1198         for (i = 0; i < 8; i++)
1199                 printf("%02x", spd->mid[i]);
1200
1201         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1202
1203         printf("%-3d    : %02x %s\n", 72, spd->mloc,
1204                " spd->mloc,        * 72 Manufacturing Location *");
1205
1206         printf("%-3d-%3d: >>",  73, 90);
1207         for (i = 0; i < 18; i++)
1208                 printf("%c", spd->mpart[i]);
1209
1210
1211         printf("<<* 73 Manufacturer's Part Number *\n");
1212
1213         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1214                "* 91 Revision Code *");
1215         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1216                "* 93 Manufacturing Date *");
1217         printf("%-3d-%3d: ", 95, 98);
1218
1219         for (i = 0; i < 4; i++)
1220                 printf("%02x", spd->sernum[i]);
1221
1222         printf("* 95 Assembly Serial Number *\n");
1223
1224         printf("%-3d-%3d: ", 99, 127);
1225         for (i = 0; i < 27; i++)
1226                 printf("%02x", spd->mspec[i]);
1227
1228
1229         printf("* 99 Manufacturer Specific Data *\n");
1230 }
1231 #endif
1232
1233 #ifdef CONFIG_SYS_FSL_DDR3
1234 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1235 {
1236         unsigned int i;
1237
1238         /* General Section: Bytes 0-59 */
1239
1240 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1241 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1242         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1243
1244         PRINT_NXS(0, spd->info_size_crc,
1245                 "info_size_crc  bytes written into serial memory, "
1246                 "CRC coverage");
1247         PRINT_NXS(1, spd->spd_rev,
1248                 "spd_rev        SPD Revision");
1249         PRINT_NXS(2, spd->mem_type,
1250                 "mem_type       Key Byte / DRAM Device Type");
1251         PRINT_NXS(3, spd->module_type,
1252                 "module_type    Key Byte / Module Type");
1253         PRINT_NXS(4, spd->density_banks,
1254                 "density_banks  SDRAM Density and Banks");
1255         PRINT_NXS(5, spd->addressing,
1256                 "addressing     SDRAM Addressing");
1257         PRINT_NXS(6, spd->module_vdd,
1258                 "module_vdd     Module Nominal Voltage, VDD");
1259         PRINT_NXS(7, spd->organization,
1260                 "organization   Module Organization");
1261         PRINT_NXS(8, spd->bus_width,
1262                 "bus_width      Module Memory Bus Width");
1263         PRINT_NXS(9, spd->ftb_div,
1264                 "ftb_div        Fine Timebase (FTB) Dividend / Divisor");
1265         PRINT_NXS(10, spd->mtb_dividend,
1266                 "mtb_dividend   Medium Timebase (MTB) Dividend");
1267         PRINT_NXS(11, spd->mtb_divisor,
1268                 "mtb_divisor    Medium Timebase (MTB) Divisor");
1269         PRINT_NXS(12, spd->tck_min,
1270                   "tck_min        SDRAM Minimum Cycle Time");
1271         PRINT_NXS(13, spd->res_13,
1272                 "res_13         Reserved");
1273         PRINT_NXS(14, spd->caslat_lsb,
1274                 "caslat_lsb     CAS Latencies Supported, LSB");
1275         PRINT_NXS(15, spd->caslat_msb,
1276                 "caslat_msb     CAS Latencies Supported, MSB");
1277         PRINT_NXS(16, spd->taa_min,
1278                   "taa_min        Min CAS Latency Time");
1279         PRINT_NXS(17, spd->twr_min,
1280                   "twr_min        Min Write REcovery Time");
1281         PRINT_NXS(18, spd->trcd_min,
1282                   "trcd_min       Min RAS# to CAS# Delay Time");
1283         PRINT_NXS(19, spd->trrd_min,
1284                   "trrd_min       Min Row Active to Row Active Delay Time");
1285         PRINT_NXS(20, spd->trp_min,
1286                   "trp_min        Min Row Precharge Delay Time");
1287         PRINT_NXS(21, spd->tras_trc_ext,
1288                   "tras_trc_ext   Upper Nibbles for tRAS and tRC");
1289         PRINT_NXS(22, spd->tras_min_lsb,
1290                   "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
1291         PRINT_NXS(23, spd->trc_min_lsb,
1292                   "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1293         PRINT_NXS(24, spd->trfc_min_lsb,
1294                   "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
1295         PRINT_NXS(25, spd->trfc_min_msb,
1296                   "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
1297         PRINT_NXS(26, spd->twtr_min,
1298                   "twtr_min Min Internal Write to Read Command Delay Time");
1299         PRINT_NXS(27, spd->trtp_min,
1300                   "trtp_min "
1301                   "Min Internal Read to Precharge Command Delay Time");
1302         PRINT_NXS(28, spd->tfaw_msb,
1303                   "tfaw_msb       Upper Nibble for tFAW");
1304         PRINT_NXS(29, spd->tfaw_min,
1305                   "tfaw_min       Min Four Activate Window Delay Time");
1306         PRINT_NXS(30, spd->opt_features,
1307                 "opt_features   SDRAM Optional Features");
1308         PRINT_NXS(31, spd->therm_ref_opt,
1309                 "therm_ref_opt  SDRAM Thermal and Refresh Opts");
1310         PRINT_NXS(32, spd->therm_sensor,
1311                 "therm_sensor  SDRAM Thermal Sensor");
1312         PRINT_NXS(33, spd->device_type,
1313                 "device_type  SDRAM Device Type");
1314         PRINT_NXS(34, spd->fine_tck_min,
1315                   "fine_tck_min  Fine offset for tCKmin");
1316         PRINT_NXS(35, spd->fine_taa_min,
1317                   "fine_taa_min  Fine offset for tAAmin");
1318         PRINT_NXS(36, spd->fine_trcd_min,
1319                   "fine_trcd_min Fine offset for tRCDmin");
1320         PRINT_NXS(37, spd->fine_trp_min,
1321                   "fine_trp_min  Fine offset for tRPmin");
1322         PRINT_NXS(38, spd->fine_trc_min,
1323                   "fine_trc_min  Fine offset for tRCmin");
1324
1325         printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
1326
1327         for (i = 39; i <= 59; i++)
1328                 printf("%02x ", spd->res_39_59[i - 39]);
1329
1330         puts("\n");
1331
1332         switch (spd->module_type) {
1333         case 0x02:  /* UDIMM */
1334         case 0x03:  /* SO-DIMM */
1335         case 0x04:  /* Micro-DIMM */
1336         case 0x06:  /* Mini-UDIMM */
1337                 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1338                         "mod_height    (Unbuffered) Module Nominal Height");
1339                 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1340                         "mod_thickness (Unbuffered) Module Maximum Thickness");
1341                 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1342                         "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1343                 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1344                         "addr_mapping  (Unbuffered) Address mapping from "
1345                         "Edge Connector to DRAM");
1346                 break;
1347         case 0x01:  /* RDIMM */
1348         case 0x05:  /* Mini-RDIMM */
1349                 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1350                         "mod_height    (Registered) Module Nominal Height");
1351                 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1352                         "mod_thickness (Registered) Module Maximum Thickness");
1353                 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1354                         "ref_raw_card  (Registered) Reference Raw Card Used");
1355                 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1356                         "modu_attr     (Registered) DIMM Module Attributes");
1357                 PRINT_NXS(64, spd->mod_section.registered.thermal,
1358                         "thermal       (Registered) Thermal Heat "
1359                         "Spreader Solution");
1360                 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1361                         "reg_id_lo     (Registered) Register Manufacturer ID "
1362                         "Code, LSB");
1363                 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1364                         "reg_id_hi     (Registered) Register Manufacturer ID "
1365                         "Code, MSB");
1366                 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1367                         "reg_rev       (Registered) Register "
1368                         "Revision Number");
1369                 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1370                         "reg_type      (Registered) Register Type");
1371                 for (i = 69; i <= 76; i++) {
1372                         printf("%-3d    : %02x rcw[%d]\n", i,
1373                                 spd->mod_section.registered.rcw[i-69], i-69);
1374                 }
1375                 break;
1376         default:
1377                 /* Module-specific Section, Unsupported Module Type */
1378                 printf("%-3d-%3d: ", 60, 116);
1379
1380                 for (i = 60; i <= 116; i++)
1381                         printf("%02x", spd->mod_section.uc[i - 60]);
1382
1383                 break;
1384         }
1385
1386         /* Unique Module ID: Bytes 117-125 */
1387         PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1388         PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1389         PRINT_NXS(119, spd->mloc,     "Mfg Location");
1390         PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1391
1392         printf("%-3d-%3d: ", 122, 125);
1393
1394         for (i = 122; i <= 125; i++)
1395                 printf("%02x ", spd->sernum[i - 122]);
1396         printf("   Module Serial Number\n");
1397
1398         /* CRC: Bytes 126-127 */
1399         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1400
1401         /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1402         printf("%-3d-%3d: ", 128, 145);
1403         for (i = 128; i <= 145; i++)
1404                 printf("%02x ", spd->mpart[i - 128]);
1405         printf("   Mfg's Module Part Number\n");
1406
1407         PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1408                 "Module Revision code");
1409
1410         PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1411         PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1412
1413         printf("%-3d-%3d: ", 150, 175);
1414         for (i = 150; i <= 175; i++)
1415                 printf("%02x ", spd->msd[i - 150]);
1416         printf("   Mfg's Specific Data\n");
1417
1418         printf("%-3d-%3d: ", 176, 255);
1419         for (i = 176; i <= 255; i++)
1420                 printf("%02x", spd->cust[i - 176]);
1421         printf("   Mfg's Specific Data\n");
1422
1423 }
1424 #endif
1425
1426 #ifdef CONFIG_SYS_FSL_DDR4
1427 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1428 {
1429         unsigned int i;
1430
1431         /* General Section: Bytes 0-127 */
1432
1433 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1434 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1435         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1436
1437         PRINT_NXS(0, spd->info_size_crc,
1438                   "info_size_crc  bytes written into serial memory, CRC coverage");
1439         PRINT_NXS(1, spd->spd_rev,
1440                   "spd_rev        SPD Revision");
1441         PRINT_NXS(2, spd->mem_type,
1442                   "mem_type       Key Byte / DRAM Device Type");
1443         PRINT_NXS(3, spd->module_type,
1444                   "module_type    Key Byte / Module Type");
1445         PRINT_NXS(4, spd->density_banks,
1446                   "density_banks  SDRAM Density and Banks");
1447         PRINT_NXS(5, spd->addressing,
1448                   "addressing     SDRAM Addressing");
1449         PRINT_NXS(6, spd->package_type,
1450                   "package_type   Package type");
1451         PRINT_NXS(7, spd->opt_feature,
1452                   "opt_feature    Optional features");
1453         PRINT_NXS(8, spd->thermal_ref,
1454                   "thermal_ref    Thermal and Refresh options");
1455         PRINT_NXS(9, spd->oth_opt_features,
1456                   "oth_opt_features Other SDRAM optional features");
1457         PRINT_NXS(10, spd->res_10,
1458                   "res_10         Reserved");
1459         PRINT_NXS(11, spd->module_vdd,
1460                   "module_vdd     Module Nominal Voltage, VDD");
1461         PRINT_NXS(12, spd->organization,
1462                   "organization Module Organization");
1463         PRINT_NXS(13, spd->bus_width,
1464                   "bus_width      Module Memory Bus Width");
1465         PRINT_NXS(14, spd->therm_sensor,
1466                   "therm_sensor   Module Thermal Sensor");
1467         PRINT_NXS(15, spd->ext_type,
1468                   "ext_type       Extended module type");
1469         PRINT_NXS(16, spd->res_16,
1470                   "res_16       Reserved");
1471         PRINT_NXS(17, spd->timebases,
1472                   "timebases    MTb and FTB");
1473         PRINT_NXS(18, spd->tck_min,
1474                   "tck_min      tCKAVGmin");
1475         PRINT_NXS(19, spd->tck_max,
1476                   "tck_max      TCKAVGmax");
1477         PRINT_NXS(20, spd->caslat_b1,
1478                   "caslat_b1    CAS latencies, 1st byte");
1479         PRINT_NXS(21, spd->caslat_b2,
1480                   "caslat_b2    CAS latencies, 2nd byte");
1481         PRINT_NXS(22, spd->caslat_b3,
1482                   "caslat_b3    CAS latencies, 3rd byte ");
1483         PRINT_NXS(23, spd->caslat_b4,
1484                   "caslat_b4    CAS latencies, 4th byte");
1485         PRINT_NXS(24, spd->taa_min,
1486                   "taa_min      Min CAS Latency Time");
1487         PRINT_NXS(25, spd->trcd_min,
1488                   "trcd_min     Min RAS# to CAS# Delay Time");
1489         PRINT_NXS(26, spd->trp_min,
1490                   "trp_min      Min Row Precharge Delay Time");
1491         PRINT_NXS(27, spd->tras_trc_ext,
1492                   "tras_trc_ext Upper Nibbles for tRAS and tRC");
1493         PRINT_NXS(28, spd->tras_min_lsb,
1494                   "tras_min_lsb tRASmin, lsb");
1495         PRINT_NXS(29, spd->trc_min_lsb,
1496                   "trc_min_lsb  tRCmin, lsb");
1497         PRINT_NXS(30, spd->trfc1_min_lsb,
1498                   "trfc1_min_lsb  Min Refresh Recovery Delay Time, LSB");
1499         PRINT_NXS(31, spd->trfc1_min_msb,
1500                   "trfc1_min_msb  Min Refresh Recovery Delay Time, MSB ");
1501         PRINT_NXS(32, spd->trfc2_min_lsb,
1502                   "trfc2_min_lsb  Min Refresh Recovery Delay Time, LSB");
1503         PRINT_NXS(33, spd->trfc2_min_msb,
1504                   "trfc2_min_msb  Min Refresh Recovery Delay Time, MSB");
1505         PRINT_NXS(34, spd->trfc4_min_lsb,
1506                   "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1507         PRINT_NXS(35, spd->trfc4_min_msb,
1508                   "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1509         PRINT_NXS(36, spd->tfaw_msb,
1510                   "tfaw_msb      Upper Nibble for tFAW");
1511         PRINT_NXS(37, spd->tfaw_min,
1512                   "tfaw_min      tFAW, lsb");
1513         PRINT_NXS(38, spd->trrds_min,
1514                   "trrds_min     tRRD_Smin, MTB");
1515         PRINT_NXS(39, spd->trrdl_min,
1516                   "trrdl_min     tRRD_Lmin, MTB");
1517         PRINT_NXS(40, spd->tccdl_min,
1518                   "tccdl_min     tCCS_Lmin, MTB");
1519
1520         printf("%-3d-%3d: ", 41, 59);  /* Reserved, General Section */
1521         for (i = 41; i <= 59; i++)
1522                 printf("%02x ", spd->res_41[i - 41]);
1523
1524         puts("\n");
1525         printf("%-3d-%3d: ", 60, 77);
1526         for (i = 60; i <= 77; i++)
1527                 printf("%02x ", spd->mapping[i - 60]);
1528         puts("   mapping[] Connector to SDRAM bit map\n");
1529
1530         PRINT_NXS(117, spd->fine_tccdl_min,
1531                   "fine_tccdl_min Fine offset for tCCD_Lmin");
1532         PRINT_NXS(118, spd->fine_trrdl_min,
1533                   "fine_trrdl_min Fine offset for tRRD_Lmin");
1534         PRINT_NXS(119, spd->fine_trrds_min,
1535                   "fine_trrds_min Fine offset for tRRD_Smin");
1536         PRINT_NXS(120, spd->fine_trc_min,
1537                   "fine_trc_min   Fine offset for tRCmin");
1538         PRINT_NXS(121, spd->fine_trp_min,
1539                   "fine_trp_min   Fine offset for tRPmin");
1540         PRINT_NXS(122, spd->fine_trcd_min,
1541                   "fine_trcd_min  Fine offset for tRCDmin");
1542         PRINT_NXS(123, spd->fine_taa_min,
1543                   "fine_taa_min   Fine offset for tAAmin");
1544         PRINT_NXS(124, spd->fine_tck_max,
1545                   "fine_tck_max   Fine offset for tCKAVGmax");
1546         PRINT_NXS(125, spd->fine_tck_min,
1547                   "fine_tck_min   Fine offset for tCKAVGmin");
1548
1549         /* CRC: Bytes 126-127 */
1550         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1551
1552         switch (spd->module_type) {
1553         case 0x02:  /* UDIMM */
1554         case 0x03:  /* SO-DIMM */
1555                 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1556                           "mod_height    (Unbuffered) Module Nominal Height");
1557                 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1558                           "mod_thickness (Unbuffered) Module Maximum Thickness");
1559                 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1560                           "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1561                 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1562                           "addr_mapping  (Unbuffered) Address mapping from Edge Connector to DRAM");
1563                 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1564                             spd->mod_section.unbuffered.crc[1], "  Module CRC");
1565                 break;
1566         case 0x01:  /* RDIMM */
1567                 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1568                           "mod_height    (Registered) Module Nominal Height");
1569                 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1570                           "mod_thickness (Registered) Module Maximum Thickness");
1571                 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1572                           "ref_raw_card  (Registered) Reference Raw Card Used");
1573                 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1574                           "modu_attr     (Registered) DIMM Module Attributes");
1575                 PRINT_NXS(132, spd->mod_section.registered.thermal,
1576                           "thermal       (Registered) Thermal Heat Spreader Solution");
1577                 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1578                           "reg_id_lo     (Registered) Register Manufacturer ID Code, LSB");
1579                 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1580                           "reg_id_hi     (Registered) Register Manufacturer ID Code, MSB");
1581                 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1582                           "reg_rev       (Registered) Register Revision Number");
1583                 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1584                           "reg_map       (Registered) Address mapping");
1585                 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1586                             spd->mod_section.registered.crc[1], "  Module CRC");
1587                 break;
1588         case 0x04:  /* LRDIMM */
1589                 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1590                           "mod_height    (Loadreduced) Module Nominal Height");
1591                 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1592                           "mod_thickness (Loadreduced) Module Maximum Thickness");
1593                 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1594                           "ref_raw_card  (Loadreduced) Reference Raw Card Used");
1595                 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1596                           "modu_attr     (Loadreduced) DIMM Module Attributes");
1597                 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1598                           "thermal       (Loadreduced) Thermal Heat Spreader Solution");
1599                 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1600                           "reg_id_lo     (Loadreduced) Register Manufacturer ID Code, LSB");
1601                 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1602                           "reg_id_hi     (Loadreduced) Register Manufacturer ID Code, MSB");
1603                 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1604                           "reg_rev       (Loadreduced) Register Revision Number");
1605                 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1606                           "reg_map       (Loadreduced) Address mapping");
1607                 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1608                           "reg_drv       (Loadreduced) Reg output drive strength");
1609                 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1610                           "reg_drv_ck    (Loadreduced) Reg output drive strength for CK");
1611                 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1612                           "data_buf_rev  (Loadreduced) Data Buffer Revision Numbe");
1613                 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1614                           "vrefqe_r0     (Loadreduced) DRAM VrefDQ for Package Rank 0");
1615                 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1616                           "vrefqe_r1     (Loadreduced) DRAM VrefDQ for Package Rank 1");
1617                 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1618                           "vrefqe_r2     (Loadreduced) DRAM VrefDQ for Package Rank 2");
1619                 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1620                           "vrefqe_r3     (Loadreduced) DRAM VrefDQ for Package Rank 3");
1621                 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1622                           "data_intf     (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1623                 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1624                           "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1625                 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1626                           "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1627                 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1628                           "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1629                 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1630                           "dram_drv      (Loadreduced) DRAM Drive Strength");
1631                 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1632                           "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1633                 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1634                           "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1635                 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1636                           "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1637                 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1638                           "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1639                 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1640                           "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1641                 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1642                           "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1643                 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1644                             spd->mod_section.loadreduced.crc[1],
1645                             "  Module CRC");
1646                 break;
1647         default:
1648                 /* Module-specific Section, Unsupported Module Type */
1649                 printf("%-3d-%3d: ", 128, 255);
1650
1651                 for (i = 128; i <= 255; i++)
1652                         printf("%02x", spd->mod_section.uc[i - 128]);
1653
1654                 break;
1655         }
1656
1657         /* Unique Module ID: Bytes 320-383 */
1658         PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1659         PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1660         PRINT_NXS(322, spd->mloc,     "Mfg Location");
1661         PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1662
1663         printf("%-3d-%3d: ", 325, 328);
1664
1665         for (i = 325; i <= 328; i++)
1666                 printf("%02x ", spd->sernum[i - 325]);
1667         printf("   Module Serial Number\n");
1668
1669         printf("%-3d-%3d: ", 329, 348);
1670         for (i = 329; i <= 348; i++)
1671                 printf("%02x ", spd->mpart[i - 329]);
1672         printf("   Mfg's Module Part Number\n");
1673
1674         PRINT_NXS(349, spd->mrev, "Module Revision code");
1675         PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1676         PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1677         PRINT_NXS(352, spd->stepping, "DRAM stepping");
1678
1679         printf("%-3d-%3d: ", 353, 381);
1680         for (i = 353; i <= 381; i++)
1681                 printf("%02x ", spd->msd[i - 353]);
1682         printf("   Mfg's Specific Data\n");
1683 }
1684 #endif
1685
1686 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1687 {
1688 #if defined(CONFIG_SYS_FSL_DDR1)
1689         ddr1_spd_dump(spd);
1690 #elif defined(CONFIG_SYS_FSL_DDR2)
1691         ddr2_spd_dump(spd);
1692 #elif defined(CONFIG_SYS_FSL_DDR3)
1693         ddr3_spd_dump(spd);
1694 #elif defined(CONFIG_SYS_FSL_DDR4)
1695         ddr4_spd_dump(spd);
1696 #endif
1697 }
1698
1699 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1700                         unsigned int ctrl_mask,
1701                         unsigned int dimm_mask,
1702                         unsigned int do_mask)
1703 {
1704         unsigned int i, j, retval;
1705
1706         /* STEP 1:  DIMM SPD data */
1707         if (do_mask & STEP_GET_SPD) {
1708                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1709                         if (!(ctrl_mask & (1 << i)))
1710                                 continue;
1711
1712                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1713                                 if (!(dimm_mask & (1 << j)))
1714                                         continue;
1715
1716                                 printf("SPD info:  Controller=%u "
1717                                                 "DIMM=%u\n", i, j);
1718                                 generic_spd_dump(
1719                                         &(pinfo->spd_installed_dimms[i][j]));
1720                                 printf("\n");
1721                         }
1722                         printf("\n");
1723                 }
1724                 printf("\n");
1725         }
1726
1727         /* STEP 2:  DIMM Parameters */
1728         if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1729                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1730                         if (!(ctrl_mask & (1 << i)))
1731                                 continue;
1732                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1733                                 if (!(dimm_mask & (1 << j)))
1734                                         continue;
1735                                 printf("DIMM parameters:  Controller=%u "
1736                                                 "DIMM=%u\n", i, j);
1737                                 print_dimm_parameters(
1738                                         &(pinfo->dimm_params[i][j]));
1739                                 printf("\n");
1740                         }
1741                         printf("\n");
1742                 }
1743                 printf("\n");
1744         }
1745
1746         /* STEP 3:  Common Parameters */
1747         if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1748                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1749                         if (!(ctrl_mask & (1 << i)))
1750                                 continue;
1751                         printf("\"lowest common\" DIMM parameters:  "
1752                                         "Controller=%u\n", i);
1753                         print_lowest_common_dimm_parameters(
1754                                 &pinfo->common_timing_params[i]);
1755                         printf("\n");
1756                 }
1757                 printf("\n");
1758         }
1759
1760         /* STEP 4:  User Configuration Options */
1761         if (do_mask & STEP_GATHER_OPTS) {
1762                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1763                         if (!(ctrl_mask & (1 << i)))
1764                                 continue;
1765                         printf("User Config Options: Controller=%u\n", i);
1766                         print_memctl_options(&pinfo->memctl_opts[i]);
1767                         printf("\n");
1768                 }
1769                 printf("\n");
1770         }
1771
1772         /* STEP 5:  Address assignment */
1773         if (do_mask & STEP_ASSIGN_ADDRESSES) {
1774                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1775                         if (!(ctrl_mask & (1 << i)))
1776                                 continue;
1777                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1778                                 printf("Address Assignment: Controller=%u "
1779                                                 "DIMM=%u\n", i, j);
1780                                 printf("Don't have this functionality yet\n");
1781                         }
1782                         printf("\n");
1783                 }
1784                 printf("\n");
1785         }
1786
1787         /* STEP 6:  computed controller register values */
1788         if (do_mask & STEP_COMPUTE_REGS) {
1789                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1790                         if (!(ctrl_mask & (1 << i)))
1791                                 continue;
1792                         printf("Computed Register Values: Controller=%u\n", i);
1793                         print_fsl_memctl_config_regs(
1794                                 &pinfo->fsl_ddr_config_reg[i]);
1795                         retval = check_fsl_memctl_config_regs(
1796                                 &pinfo->fsl_ddr_config_reg[i]);
1797                         if (retval) {
1798                                 printf("check_fsl_memctl_config_regs "
1799                                         "result = %u\n", retval);
1800                         }
1801                         printf("\n");
1802                 }
1803                 printf("\n");
1804         }
1805 }
1806
1807 struct data_strings {
1808         const char *data_name;
1809         unsigned int step_mask;
1810         unsigned int dimm_number_required;
1811 };
1812
1813 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1814
1815 static unsigned int fsl_ddr_parse_interactive_cmd(
1816         char **argv,
1817         int argc,
1818         unsigned int *pstep_mask,
1819         unsigned int *pctlr_mask,
1820         unsigned int *pdimm_mask,
1821         unsigned int *pdimm_number_required
1822          ) {
1823
1824         static const struct data_strings options[] = {
1825                 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1826                 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1827                 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1828                 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1829                 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1830                 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1831         };
1832         static const unsigned int n_opts = ARRAY_SIZE(options);
1833
1834         unsigned int i, j;
1835         unsigned int error = 0;
1836
1837         for (i = 1; i < argc; i++) {
1838                 unsigned int matched = 0;
1839
1840                 for (j = 0; j < n_opts; j++) {
1841                         if (strcmp(options[j].data_name, argv[i]) != 0)
1842                                 continue;
1843                         *pstep_mask |= options[j].step_mask;
1844                         *pdimm_number_required =
1845                                 options[j].dimm_number_required;
1846                         matched = 1;
1847                         break;
1848                 }
1849
1850                 if (matched)
1851                         continue;
1852
1853                 if (argv[i][0] == 'c') {
1854                         char c = argv[i][1];
1855                         if (isdigit(c))
1856                                 *pctlr_mask |= 1 << (c - '0');
1857                         continue;
1858                 }
1859
1860                 if (argv[i][0] == 'd') {
1861                         char c = argv[i][1];
1862                         if (isdigit(c))
1863                                 *pdimm_mask |= 1 << (c - '0');
1864                         continue;
1865                 }
1866
1867                 printf("unknown arg %s\n", argv[i]);
1868                 *pstep_mask = 0;
1869                 error = 1;
1870                 break;
1871         }
1872
1873         return error;
1874 }
1875
1876 int fsl_ddr_interactive_env_var_exists(void)
1877 {
1878         char buffer[CONFIG_SYS_CBSIZE];
1879
1880         if (env_get_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1881                 return 1;
1882
1883         return 0;
1884 }
1885
1886 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1887 {
1888         unsigned long long ddrsize;
1889         const char *prompt = "FSL DDR>";
1890         char buffer[CONFIG_SYS_CBSIZE];
1891         char buffer2[CONFIG_SYS_CBSIZE];
1892         char *p = NULL;
1893         char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
1894         int argc;
1895         unsigned int next_step = STEP_GET_SPD;
1896         const char *usage = {
1897                 "commands:\n"
1898                 "print      print SPD and intermediate computed data\n"
1899                 "reset      reboot machine\n"
1900                 "recompute  reload SPD and options to default and recompute regs\n"
1901                 "edit       modify spd, parameter, or option\n"
1902                 "compute    recompute registers from current next_step to end\n"
1903                 "copy       copy parameters\n"
1904                 "next_step  shows current next_step\n"
1905                 "help       this message\n"
1906                 "go         program the memory controller and continue with u-boot\n"
1907         };
1908
1909         if (var_is_set) {
1910                 if (env_get_f("ddr_interactive", buffer2,
1911                               CONFIG_SYS_CBSIZE) > 0)
1912                         p = buffer2;
1913                 else
1914                         var_is_set = 0;
1915         }
1916
1917         /*
1918          * The strategy for next_step is that it points to the next
1919          * step in the computation process that needs to be done.
1920          */
1921         while (1) {
1922                 if (var_is_set) {
1923                         char *pend = strchr(p, ';');
1924                         if (pend) {
1925                                 /* found command separator, copy sub-command */
1926                                 *pend = '\0';
1927                                 strcpy(buffer, p);
1928                                 p = pend + 1;
1929                         } else {
1930                                 /* separator not found, copy whole string */
1931                                 strcpy(buffer, p);
1932                                 p = NULL;
1933                                 var_is_set = 0;
1934                         }
1935                 } else {
1936                         /*
1937                          * No need to worry for buffer overflow here in
1938                          * this function;  cli_readline() maxes out at
1939                          * CFG_CBSIZE
1940                          */
1941                         cli_readline_into_buffer(prompt, buffer, 0);
1942                 }
1943                 argc = cli_simple_parse_line(buffer, argv);
1944                 if (argc == 0)
1945                         continue;
1946
1947
1948                 if (strcmp(argv[0], "help") == 0) {
1949                         puts(usage);
1950                         continue;
1951                 }
1952
1953                 if (strcmp(argv[0], "next_step") == 0) {
1954                         printf("next_step = 0x%02X (%s)\n",
1955                                next_step,
1956                                step_to_string(next_step));
1957                         continue;
1958                 }
1959
1960                 if (strcmp(argv[0], "copy") == 0) {
1961                         unsigned int error = 0;
1962                         unsigned int step_mask = 0;
1963                         unsigned int src_ctlr_mask = 0;
1964                         unsigned int src_dimm_mask = 0;
1965                         unsigned int dimm_number_required = 0;
1966                         unsigned int src_ctlr_num = 0;
1967                         unsigned int src_dimm_num = 0;
1968                         unsigned int dst_ctlr_num = -1;
1969                         unsigned int dst_dimm_num = -1;
1970                         unsigned int i, num_dest_parms;
1971
1972                         if (argc == 1) {
1973                                 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1974                                 continue;
1975                         }
1976
1977                         error = fsl_ddr_parse_interactive_cmd(
1978                                 argv, argc,
1979                                 &step_mask,
1980                                 &src_ctlr_mask,
1981                                 &src_dimm_mask,
1982                                 &dimm_number_required
1983                         );
1984
1985                         /* XXX: only dimm_number_required and step_mask will
1986                            be used by this function.  Parse the controller and
1987                            DIMM number separately because it is easier.  */
1988
1989                         if (error)
1990                                 continue;
1991
1992                         /* parse source destination controller / DIMM */
1993
1994                         num_dest_parms = dimm_number_required ? 2 : 1;
1995
1996                         for (i = 0; i < argc; i++) {
1997                                 if (argv[i][0] == 'c') {
1998                                         char c = argv[i][1];
1999                                         if (isdigit(c)) {
2000                                                 src_ctlr_num = (c - '0');
2001                                                 break;
2002                                         }
2003                                 }
2004                         }
2005
2006                         for (i = 0; i < argc; i++) {
2007                                 if (argv[i][0] == 'd') {
2008                                         char c = argv[i][1];
2009                                         if (isdigit(c)) {
2010                                                 src_dimm_num = (c - '0');
2011                                                 break;
2012                                         }
2013                                 }
2014                         }
2015
2016                         /* parse destination controller / DIMM */
2017
2018                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2019                                 if (argv[i][0] == 'c') {
2020                                         char c = argv[i][1];
2021                                         if (isdigit(c)) {
2022                                                 dst_ctlr_num = (c - '0');
2023                                                 break;
2024                                         }
2025                                 }
2026                         }
2027
2028                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2029                                 if (argv[i][0] == 'd') {
2030                                         char c = argv[i][1];
2031                                         if (isdigit(c)) {
2032                                                 dst_dimm_num = (c - '0');
2033                                                 break;
2034                                         }
2035                                 }
2036                         }
2037
2038                         /* TODO: validate inputs */
2039
2040                         debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
2041                                 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
2042
2043
2044                         switch (step_mask) {
2045
2046                         case STEP_GET_SPD:
2047                                 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
2048                                         &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
2049                                         sizeof(pinfo->spd_installed_dimms[0][0]));
2050                                 break;
2051
2052                         case STEP_COMPUTE_DIMM_PARMS:
2053                                 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
2054                                         &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
2055                                         sizeof(pinfo->dimm_params[0][0]));
2056                                 break;
2057
2058                         case STEP_COMPUTE_COMMON_PARMS:
2059                                 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
2060                                         &(pinfo->common_timing_params[src_ctlr_num]),
2061                                         sizeof(pinfo->common_timing_params[0]));
2062                                 break;
2063
2064                         case STEP_GATHER_OPTS:
2065                                 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
2066                                         &(pinfo->memctl_opts[src_ctlr_num]),
2067                                         sizeof(pinfo->memctl_opts[0]));
2068                                 break;
2069
2070                         /* someday be able to have addresses to copy addresses... */
2071
2072                         case STEP_COMPUTE_REGS:
2073                                 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2074                                         &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2075                                         sizeof(pinfo->memctl_opts[0]));
2076                                 break;
2077
2078                         default:
2079                                 printf("unexpected step_mask value\n");
2080                         }
2081
2082                         continue;
2083
2084                 }
2085
2086                 if (strcmp(argv[0], "edit") == 0) {
2087                         unsigned int error = 0;
2088                         unsigned int step_mask = 0;
2089                         unsigned int ctlr_mask = 0;
2090                         unsigned int dimm_mask = 0;
2091                         char *p_element = NULL;
2092                         char *p_value = NULL;
2093                         unsigned int dimm_number_required = 0;
2094                         unsigned int ctrl_num;
2095                         unsigned int dimm_num;
2096
2097                         if (argc == 1) {
2098                                 /* Only the element and value must be last */
2099                                 printf("edit <c#> <d#> "
2100                                         "<spd|dimmparms|commonparms|opts|"
2101                                         "addresses|regs> <element> <value>\n");
2102                                 printf("for spd, specify byte number for "
2103                                         "element\n");
2104                                 continue;
2105                         }
2106
2107                         error = fsl_ddr_parse_interactive_cmd(
2108                                 argv, argc - 2,
2109                                 &step_mask,
2110                                 &ctlr_mask,
2111                                 &dimm_mask,
2112                                 &dimm_number_required
2113                         );
2114
2115                         if (error)
2116                                 continue;
2117
2118
2119                         /* Check arguments */
2120
2121                         /* ERROR: If no steps were found */
2122                         if (step_mask == 0) {
2123                                 printf("Error: No valid steps were specified "
2124                                                 "in argument.\n");
2125                                 continue;
2126                         }
2127
2128                         /* ERROR: If multiple steps were found */
2129                         if (step_mask & (step_mask - 1)) {
2130                                 printf("Error: Multiple steps specified in "
2131                                                 "argument.\n");
2132                                 continue;
2133                         }
2134
2135                         /* ERROR: Controller not specified */
2136                         if (ctlr_mask == 0) {
2137                                 printf("Error: controller number not "
2138                                         "specified or no element and "
2139                                         "value specified\n");
2140                                 continue;
2141                         }
2142
2143                         if (ctlr_mask & (ctlr_mask - 1)) {
2144                                 printf("Error: multiple controllers "
2145                                                 "specified, %X\n", ctlr_mask);
2146                                 continue;
2147                         }
2148
2149                         /* ERROR: DIMM number not specified */
2150                         if (dimm_number_required && dimm_mask == 0) {
2151                                 printf("Error: DIMM number number not "
2152                                         "specified or no element and "
2153                                         "value specified\n");
2154                                 continue;
2155                         }
2156
2157                         if (dimm_mask & (dimm_mask - 1)) {
2158                                 printf("Error: multipled DIMMs specified\n");
2159                                 continue;
2160                         }
2161
2162                         p_element = argv[argc - 2];
2163                         p_value = argv[argc - 1];
2164
2165                         ctrl_num = __ilog2(ctlr_mask);
2166                         dimm_num = __ilog2(dimm_mask);
2167
2168                         switch (step_mask) {
2169                         case STEP_GET_SPD:
2170                                 {
2171                                         unsigned int element_num;
2172                                         unsigned int value;
2173
2174                                         element_num = simple_strtoul(p_element,
2175                                                                      NULL, 0);
2176                                         value = simple_strtoul(p_value,
2177                                                                NULL, 0);
2178                                         fsl_ddr_spd_edit(pinfo,
2179                                                                ctrl_num,
2180                                                                dimm_num,
2181                                                                element_num,
2182                                                                value);
2183                                         next_step = STEP_COMPUTE_DIMM_PARMS;
2184                                 }
2185                                 break;
2186
2187                         case STEP_COMPUTE_DIMM_PARMS:
2188                                 fsl_ddr_dimm_parameters_edit(
2189                                                  pinfo, ctrl_num, dimm_num,
2190                                                  p_element, p_value);
2191                                 next_step = STEP_COMPUTE_COMMON_PARMS;
2192                                 break;
2193
2194                         case STEP_COMPUTE_COMMON_PARMS:
2195                                 lowest_common_dimm_parameters_edit(pinfo,
2196                                                 ctrl_num, p_element, p_value);
2197                                 next_step = STEP_GATHER_OPTS;
2198                                 break;
2199
2200                         case STEP_GATHER_OPTS:
2201                                 fsl_ddr_options_edit(pinfo, ctrl_num,
2202                                                            p_element, p_value);
2203                                 next_step = STEP_ASSIGN_ADDRESSES;
2204                                 break;
2205
2206                         case STEP_ASSIGN_ADDRESSES:
2207                                 printf("editing of address assignment "
2208                                                 "not yet implemented\n");
2209                                 break;
2210
2211                         case STEP_COMPUTE_REGS:
2212                                 {
2213                                         fsl_ddr_regs_edit(pinfo,
2214                                                                 ctrl_num,
2215                                                                 p_element,
2216                                                                 p_value);
2217                                         next_step = STEP_PROGRAM_REGS;
2218                                 }
2219                                 break;
2220
2221                         default:
2222                                 printf("programming error\n");
2223                                 while (1)
2224                                         ;
2225                                 break;
2226                         }
2227                         continue;
2228                 }
2229
2230                 if (strcmp(argv[0], "reset") == 0) {
2231                         /*
2232                          * Reboot machine.
2233                          * Args don't seem to matter because this
2234                          * doesn't return
2235                          */
2236                         do_reset(NULL, 0, 0, NULL);
2237                         printf("Reset didn't work\n");
2238                 }
2239
2240                 if (strcmp(argv[0], "recompute") == 0) {
2241                         /*
2242                          * Recalculate everything, starting with
2243                          * loading SPD EEPROM from DIMMs
2244                          */
2245                         next_step = STEP_GET_SPD;
2246                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2247                         continue;
2248                 }
2249
2250                 if (strcmp(argv[0], "compute") == 0) {
2251                         /*
2252                          * Compute rest of steps starting at
2253                          * the current next_step/
2254                          */
2255                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2256                         continue;
2257                 }
2258
2259                 if (strcmp(argv[0], "print") == 0) {
2260                         unsigned int error = 0;
2261                         unsigned int step_mask = 0;
2262                         unsigned int ctlr_mask = 0;
2263                         unsigned int dimm_mask = 0;
2264                         unsigned int dimm_number_required = 0;
2265
2266                         if (argc == 1) {
2267                                 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2268                                   "[commonparms] [opts] [addresses] [regs]\n");
2269                                 continue;
2270                         }
2271
2272                         error = fsl_ddr_parse_interactive_cmd(
2273                                 argv, argc,
2274                                 &step_mask,
2275                                 &ctlr_mask,
2276                                 &dimm_mask,
2277                                 &dimm_number_required
2278                         );
2279
2280                         if (error)
2281                                 continue;
2282
2283                         /* If no particular controller was found, print all */
2284                         if (ctlr_mask == 0)
2285                                 ctlr_mask = 0xFF;
2286
2287                         /* If no particular dimm was found, print all dimms. */
2288                         if (dimm_mask == 0)
2289                                 dimm_mask = 0xFF;
2290
2291                         /* If no steps were found, print all steps. */
2292                         if (step_mask == 0)
2293                                 step_mask = STEP_ALL;
2294
2295                         fsl_ddr_printinfo(pinfo, ctlr_mask,
2296                                                 dimm_mask, step_mask);
2297                         continue;
2298                 }
2299
2300                 if (strcmp(argv[0], "go") == 0) {
2301                         if (next_step)
2302                                 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2303                         break;
2304                 }
2305
2306                 printf("unknown command %s\n", argv[0]);
2307         }
2308
2309         debug("end of memory = %llu\n", (u64)ddrsize);
2310
2311         return ddrsize;
2312 }