drivers/ddr/fsl/fsl_mmdc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
   8  */
   9
  10 #include <common.h>
  11 #include <fsl_mmdc.h>
  12 #include <asm/io.h>
  13 #include <linux/delay.h>
  14
  15 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  16 {
  17         int timeout = 1000;
  18
  19         out_be32(ptr, value);
  20
  21         while (in_be32(ptr) & bits) {
  22                 udelay(100);
  23                 timeout--;
  24         }
  25         if (timeout <= 0)
  26                 printf("Error: %p wait for clear timeout.\n", ptr);
  27 }
  28
  29 void mmdc_init(const struct fsl_mmdc_info *priv)
  30 {
  31         struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
  32         unsigned int tmp;
  33
  34         /* 1. set configuration request */
  35         out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
  36
  37         /* 2. configure the desired timing parameters */
  38         out_be32(&mmdc->mdotc, priv->mdotc);
  39         out_be32(&mmdc->mdcfg0, priv->mdcfg0);
  40         out_be32(&mmdc->mdcfg1, priv->mdcfg1);
  41         out_be32(&mmdc->mdcfg2, priv->mdcfg2);
  42
  43         /* 3. configure DDR type and other miscellaneous parameters */
  44         out_be32(&mmdc->mdmisc, priv->mdmisc);
  45         out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
  46         out_be32(&mmdc->mdrwd, priv->mdrwd);
  47         out_be32(&mmdc->mpodtctrl, priv->mpodtctrl);
  48
  49         /* 4. configure the required delay while leaving reset */
  50         out_be32(&mmdc->mdor, priv->mdor);
  51
  52         /* 5. configure DDR physical parameters */
  53         /* set row/column address width, burst length, data bus width */
  54         tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
  55         out_be32(&mmdc->mdctl, tmp);
  56         /* configure address space partition */
  57         out_be32(&mmdc->mdasp, priv->mdasp);
  58
  59         /* 6. perform a ZQ calibration - not needed here, doing in #8b */
  60
  61         /* 7. enable MMDC with the desired chip select */
  62 #if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
  63                 out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
  64 #elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
  65                 out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
  66 #endif
  67
  68         /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
  69         out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
  70                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
  71
  72         out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
  73                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
  74
  75         out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
  76                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
  77
  78         out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x19) |
  79                                 CMD_ADDR_LSB_MR_ADDR(0x30) |
  80                                 MDSCR_ENABLE_CON_REQ |
  81                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
  82
  83         /* 8b. ZQ calibration */
  84         out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
  85                                 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
  86
  87         set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
  88                                 MPZQHWCTRL_ZQ_HW_FORCE);
  89
  90         /* 9a. calibrations now, wr lvl */
  91         out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) |
  92                                 MDSCR_ENABLE_CON_REQ |
  93                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
  94
  95         out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
  96                                 CMD_NORMAL);
  97
  98         set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
  99                                 MPWLGCR_HW_WL_EN);
 100
 101         mdelay(1);
 102
 103         out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
 104                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
 105         out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
 106
 107         mdelay(1);
 108
 109         /* 9b. read DQS gating calibration */
 110         out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
 111                                 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
 112
 113         out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
 114                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
 115
 116         out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
 117
 118         /* set absolute read delay offset */
 119         if (priv->mprddlctl)
 120                 out_be32(&mmdc->mprddlctl, priv->mprddlctl);
 121         else
 122                 out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
 123
 124         set_wait_for_bits_clear(&mmdc->mpdgctrl0,
 125                                 AUTO_RD_DQS_GATING_CALIBRATION_EN,
 126                                 AUTO_RD_DQS_GATING_CALIBRATION_EN);
 127
 128         out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
 129                                 CMD_BANK_ADDR_3);
 130
 131         /* 9c. read calibration */
 132         out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
 133                                 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
 134         out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
 135                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
 136         out_be32(&mmdc->mppdcmpr2,  MPPDCMPR2_MPR_COMPARE_EN);
 137         set_wait_for_bits_clear(&mmdc->mprddlhwctl,
 138                                 MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
 139                                 MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
 140
 141         out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
 142                                 CMD_BANK_ADDR_3);
 143
 144         /* 10. configure power-down, self-refresh entry, exit parameters */
 145         out_be32(&mmdc->mdpdc, priv->mdpdc);
 146         out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
 147
 148         /* 11. ZQ config again? do nothing here */
 149
 150         /* 12. refresh scheme */
 151         set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
 152                                 MDREF_START_REFRESH);
 153
 154         /* 13. disable CON_REQ */
 155         out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
 156 }