drivers/ddr/fsl/fsl_ddr_gen4.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <env.h>
   8 #include <log.h>
   9 #include <asm/io.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <asm/processor.h>
  12 #include <fsl_immap.h>
  13 #include <fsl_ddr.h>
  14 #include <fsl_errata.h>
  15 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  16         defined(CONFIG_ARM)
  17 #include <asm/arch/clock.h>
  18 #endif
  19 #include <linux/delay.h>
  20
  21 #define CTLR_INTLV_MASK 0x20000000
  22
  23 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  24         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  25 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  26 {
  27         int timeout = 1000;
  28
  29         ddr_out32(ptr, value);
  30
  31         while (ddr_in32(ptr) & bits) {
  32                 udelay(100);
  33                 timeout--;
  34         }
  35         if (timeout <= 0)
  36                 puts("Error: wait for clear timeout.\n");
  37 }
  38 #endif
  39
  40 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  41 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  42 #endif
  43
  44 /*
  45  * regs has the to-be-set values for DDR controller registers
  46  * ctrl_num is the DDR controller number
  47  * step: 0 goes through the initialization in one pass
  48  *       1 sets registers and returns before enabling controller
  49  *       2 resumes from step 1 and continues to initialize
  50  * Dividing the initialization to two steps to deassert DDR reset signal
  51  * to comply with JEDEC specs for RDIMMs.
  52  */
  53 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  54                              unsigned int ctrl_num, int step)
  55 {
  56         unsigned int i, bus_width;
  57         struct ccsr_ddr __iomem *ddr;
  58         u32 temp32;
  59         u32 total_gb_size_per_controller;
  60         int timeout;
  61         int mod_bnds = 0;
  62
  63 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  64         u32 mr6;
  65         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  66         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  67         u32 *vref_seq = vref_seq1;
  68 #endif
  69 #ifdef CONFIG_FSL_DDR_BIST
  70         u32 mtcr, err_detect, err_sbe;
  71         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  72 #endif
  73 #ifdef CONFIG_FSL_DDR_BIST
  74         char buffer[CONFIG_SYS_CBSIZE];
  75 #endif
  76         switch (ctrl_num) {
  77         case 0:
  78                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  79                 break;
  80 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  81         case 1:
  82                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  83                 break;
  84 #endif
  85 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  86         case 2:
  87                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  88                 break;
  89 #endif
  90 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  91         case 3:
  92                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  93                 break;
  94 #endif
  95         default:
  96                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  97                 return;
  98         }
  99         mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
 100
 101         if (step == 2)
 102                 goto step2;
 103
 104         /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
 105         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 106
 107         if (regs->ddr_eor)
 108                 ddr_out32(&ddr->eor, regs->ddr_eor);
 109
 110         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 111         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 112                 if (i == 0) {
 113                         if (mod_bnds) {
 114                                 debug("modified bnds\n");
 115                                 ddr_out32(&ddr->cs0_bnds,
 116                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 117                                 ddr_out32(&ddr->cs0_config,
 118                                           (regs->cs[i].config &
 119                                            ~CTLR_INTLV_MASK));
 120                         } else {
 121                                 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 122                                 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 123                         }
 124                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 125
 126                 } else if (i == 1) {
 127                         if (mod_bnds) {
 128                                 ddr_out32(&ddr->cs1_bnds,
 129                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 130                         } else {
 131                                 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 132                         }
 133                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 134                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 135
 136                 } else if (i == 2) {
 137                         if (mod_bnds) {
 138                                 ddr_out32(&ddr->cs2_bnds,
 139                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 140                         } else {
 141                                 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 142                         }
 143                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 144                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 145
 146                 } else if (i == 3) {
 147                         if (mod_bnds) {
 148                                 ddr_out32(&ddr->cs3_bnds,
 149                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 150                         } else {
 151                                 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 152                         }
 153                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 154                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 155                 }
 156         }
 157
 158         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 159         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 160         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 161         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 162         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 163         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 164         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 165         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 166         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 167         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 168         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 169         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 170         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 171         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 172         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 173         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 174         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 175         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 176         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 177         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 178         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 179         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 180         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 181         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 182         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 183         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 184         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 185         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 186         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 187         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 188         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 189         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 190         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 191 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 192         ddr_out32(&ddr->sdram_interval,
 193                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 194 #else
 195         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 196 #endif
 197         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 198         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 199 #ifndef CONFIG_SYS_FSL_DDR_EMU
 200         /*
 201          * Skip these two registers if running on emulator
 202          * because emulator doesn't have skew between bytes.
 203          */
 204
 205         if (regs->ddr_wrlvl_cntl_2)
 206                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 207         if (regs->ddr_wrlvl_cntl_3)
 208                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 209 #endif
 210
 211         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 212         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 213         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 214         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 215         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 216         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 217         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 218 #ifdef CONFIG_DEEP_SLEEP
 219         if (is_warm_boot()) {
 220                 ddr_out32(&ddr->sdram_cfg_2,
 221                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 222                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 223                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 224
 225                 /* DRAM VRef will not be trained */
 226                 ddr_out32(&ddr->ddr_cdr2,
 227                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 228         } else
 229 #endif
 230         {
 231                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 232                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 233                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 234                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 235         }
 236
 237 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 238         /* part 1 of 2 */
 239         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 240                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
 241                         ddr_out32(&ddr->ddr_sdram_rcw_2,
 242                                   regs->ddr_sdram_rcw_2 & ~0xf0);
 243                 }
 244                 ddr_out32(&ddr->err_disable, regs->err_disable |
 245                           DDR_ERR_DISABLE_APED);
 246         }
 247 #else
 248         ddr_out32(&ddr->err_disable, regs->err_disable);
 249 #endif
 250         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 251         for (i = 0; i < 64; i++) {
 252                 if (regs->debug[i]) {
 253                         debug("Write to debug_%d as %08x\n",
 254                               i+1, regs->debug[i]);
 255                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 256                 }
 257         }
 258
 259 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 260         /* Part 1 of 2 */
 261         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 262                 /* Disable DRAM VRef training */
 263                 ddr_out32(&ddr->ddr_cdr2,
 264                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 265                 /* disable transmit bit deskew */
 266                 temp32 = ddr_in32(&ddr->debug[28]);
 267                 temp32 |= DDR_TX_BD_DIS;
 268                 ddr_out32(&ddr->debug[28], temp32);
 269                 ddr_out32(&ddr->debug[25], 0x9000);
 270         } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
 271                 /* Output enable forced off */
 272                 ddr_out32(&ddr->debug[37], 1 << 31);
 273                 /* Enable Vref training */
 274                 ddr_out32(&ddr->ddr_cdr2,
 275                           regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
 276         } else {
 277                 debug("Erratum A008511 doesn't apply.\n");
 278         }
 279 #endif
 280
 281 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
 282         defined(CONFIG_SYS_FSL_ERRATUM_A008511)
 283         /* Disable D_INIT */
 284         ddr_out32(&ddr->sdram_cfg_2,
 285                   regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 286 #endif
 287
 288 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 289         temp32 = ddr_in32(&ddr->debug[25]);
 290         temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
 291         temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
 292         ddr_out32(&ddr->debug[25], temp32);
 293 #endif
 294
 295 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
 296         temp32 = get_ddr_freq(ctrl_num) / 1000000;
 297         if ((temp32 > 1900) && (temp32 < 2300)) {
 298                 temp32 = ddr_in32(&ddr->debug[28]);
 299                 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
 300         }
 301 #endif
 302         /*
 303          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 304          * deasserted. Clocks start when any chip select is enabled and clock
 305          * control register is set. Because all DDR components are connected to
 306          * one reset signal, this needs to be done in two steps. Step 1 is to
 307          * get the clocks started. Step 2 resumes after reset signal is
 308          * deasserted.
 309          */
 310         if (step == 1) {
 311                 udelay(200);
 312                 return;
 313         }
 314
 315 step2:
 316         /* Set, but do not enable the memory */
 317         temp32 = regs->ddr_sdram_cfg;
 318         temp32 &= ~(SDRAM_CFG_MEM_EN);
 319         ddr_out32(&ddr->sdram_cfg, temp32);
 320
 321         /*
 322          * 500 painful micro-seconds must elapse between
 323          * the DDR clock setup and the DDR config enable.
 324          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 325          * we choose the max, that is 500 us for all of case.
 326          */
 327         udelay(500);
 328         mb();
 329         isb();
 330
 331 #ifdef CONFIG_DEEP_SLEEP
 332         if (is_warm_boot()) {
 333                 /* enter self-refresh */
 334                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 335                 temp32 |= SDRAM_CFG2_FRC_SR;
 336                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 337                 /* do board specific memory setup */
 338                 board_mem_sleep_setup();
 339
 340                 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 341         } else
 342 #endif
 343                 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 344         /* Let the controller go */
 345         ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
 346         mb();
 347         isb();
 348
 349 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 350         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 351         /* Part 2 of 2 */
 352         timeout = 40;
 353         /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
 354         while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 355                (timeout > 0)) {
 356                 udelay(1000);
 357                 timeout--;
 358         }
 359         if (timeout <= 0) {
 360                 printf("Controler %d timeout, debug_2 = %x\n",
 361                        ctrl_num, ddr_in32(&ddr->debug[1]));
 362         }
 363
 364 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 365         /* This erraum only applies to verion 5.2.0 */
 366         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 367                 /* The vref setting sequence is different for range 2 */
 368                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 369                         vref_seq = vref_seq2;
 370
 371                 /* Set VREF */
 372                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 373                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 374                                 continue;
 375
 376                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 377                                  MD_CNTL_MD_EN                          |
 378                                  MD_CNTL_CS_SEL(i)                      |
 379                                  MD_CNTL_MD_SEL(6)                      |
 380                                  0x00200000;
 381                         temp32 = mr6 | vref_seq[0];
 382                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 383                                                 temp32, MD_CNTL_MD_EN);
 384                         udelay(1);
 385                         debug("MR6 = 0x%08x\n", temp32);
 386                         temp32 = mr6 | vref_seq[1];
 387                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 388                                                 temp32, MD_CNTL_MD_EN);
 389                         udelay(1);
 390                         debug("MR6 = 0x%08x\n", temp32);
 391                         temp32 = mr6 | vref_seq[2];
 392                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 393                                                 temp32, MD_CNTL_MD_EN);
 394                         udelay(1);
 395                         debug("MR6 = 0x%08x\n", temp32);
 396                 }
 397                 ddr_out32(&ddr->sdram_md_cntl, 0);
 398                 temp32 = ddr_in32(&ddr->debug[28]);
 399                 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
 400                 ddr_out32(&ddr->debug[28], temp32);
 401                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 402                 /* wait for idle */
 403                 timeout = 40;
 404                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 405                        (timeout > 0)) {
 406                         udelay(1000);
 407                         timeout--;
 408                 }
 409                 if (timeout <= 0) {
 410                         printf("Controler %d timeout, debug_2 = %x\n",
 411                                ctrl_num, ddr_in32(&ddr->debug[1]));
 412                 }
 413         }
 414 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 415
 416 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 417         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 418                 /* if it's RDIMM */
 419                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
 420                         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 421                                 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 422                                         continue;
 423                                 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 424                                                         MD_CNTL_MD_EN |
 425                                                         MD_CNTL_CS_SEL(i) |
 426                                                         0x070000ed,
 427                                                         MD_CNTL_MD_EN);
 428                                 udelay(1);
 429                         }
 430                 }
 431
 432                 ddr_out32(&ddr->err_disable,
 433                           regs->err_disable & ~DDR_ERR_DISABLE_APED);
 434         }
 435 #endif
 436         /* Restore D_INIT */
 437         ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 438 #endif
 439
 440         total_gb_size_per_controller = 0;
 441         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 442                 if (!(regs->cs[i].config & 0x80000000))
 443                         continue;
 444                 total_gb_size_per_controller += 1 << (
 445                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 446                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 447                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 448                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 449                         ((regs->ddr_sdram_cfg_3 >> 4) & 0x3) +
 450                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 451                         26);                    /* minus 26 (count of 64M) */
 452         }
 453         /*
 454          * total memory / bus width = transactions needed
 455          * transactions needed / data rate = seconds
 456          * to add plenty of buffer, double the time
 457          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 458          * Let's wait for 800ms
 459          */
 460         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 461                         >> SDRAM_CFG_DBW_SHIFT);
 462         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 463                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 464         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 465         debug("total %d GB\n", total_gb_size_per_controller);
 466         debug("Need to wait up to %d * 10ms\n", timeout);
 467
 468         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 469         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 470                 (timeout >= 0)) {
 471                 udelay(10000);          /* throttle polling rate */
 472                 timeout--;
 473         }
 474
 475         if (timeout <= 0)
 476                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 477
 478         if (mod_bnds) {
 479                 debug("Reset to original bnds\n");
 480                 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
 481 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 482                 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
 483 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 484                 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
 485 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 486                 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
 487 #endif
 488 #endif
 489 #endif
 490                 ddr_out32(&ddr->cs0_config, regs->cs[0].config);
 491         }
 492
 493 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 494         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 495 #endif
 496
 497 #ifdef CONFIG_DEEP_SLEEP
 498         if (is_warm_boot()) {
 499                 /* exit self-refresh */
 500                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 501                 temp32 &= ~SDRAM_CFG2_FRC_SR;
 502                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 503         }
 504 #endif
 505
 506 #ifdef CONFIG_FSL_DDR_BIST
 507 #define BIST_PATTERN1   0xFFFFFFFF
 508 #define BIST_PATTERN2   0x0
 509 #define BIST_CR         0x80010000
 510 #define BIST_CR_EN      0x80000000
 511 #define BIST_CR_STAT    0x00000001
 512         /* Perform build-in test on memory. Three-way interleaving is not yet
 513          * supported by this code. */
 514         if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 515                 puts("Running BIST test. This will take a while...");
 516                 cs0_config = ddr_in32(&ddr->cs0_config);
 517                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 518                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 519                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 520                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 521                 if (cs0_config & CTLR_INTLV_MASK) {
 522                         /* set bnds to non-interleaving */
 523                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 524                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 525                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 526                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 527                 }
 528                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 529                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 530                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 531                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 532                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 533                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 534                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 535                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 536                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 537                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 538                 mtcr = BIST_CR;
 539                 ddr_out32(&ddr->mtcr, mtcr);
 540                 timeout = 100;
 541                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 542                         mdelay(1000);
 543                         timeout--;
 544                         mtcr = ddr_in32(&ddr->mtcr);
 545                 }
 546                 if (timeout <= 0)
 547                         puts("Timeout\n");
 548                 else
 549                         puts("Done\n");
 550                 err_detect = ddr_in32(&ddr->err_detect);
 551                 err_sbe = ddr_in32(&ddr->err_sbe);
 552                 if (mtcr & BIST_CR_STAT) {
 553                         printf("BIST test failed on controller %d.\n",
 554                                ctrl_num);
 555                 }
 556                 if (err_detect || (err_sbe & 0xffff)) {
 557                         printf("ECC error detected on controller %d.\n",
 558                                ctrl_num);
 559                 }
 560
 561                 if (cs0_config & CTLR_INTLV_MASK) {
 562                         /* restore bnds registers */
 563                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 564                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 565                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 566                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 567                 }
 568         }
 569 #endif
 570 }