drivers/ddr/fsl/fsl_ddr_gen4.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <env.h>
   8 #include <log.h>
   9 #include <asm/io.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <asm/processor.h>
  12 #include <fsl_immap.h>
  13 #include <fsl_ddr.h>
  14 #include <fsl_errata.h>
  15 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  16         defined(CONFIG_ARM)
  17 #include <asm/arch/clock.h>
  18 #endif
  19
  20 #define CTLR_INTLV_MASK 0x20000000
  21
  22 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  23         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  24 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  25 {
  26         int timeout = 1000;
  27
  28         ddr_out32(ptr, value);
  29
  30         while (ddr_in32(ptr) & bits) {
  31                 udelay(100);
  32                 timeout--;
  33         }
  34         if (timeout <= 0)
  35                 puts("Error: wait for clear timeout.\n");
  36 }
  37 #endif
  38
  39 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  40 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  41 #endif
  42
  43 /*
  44  * regs has the to-be-set values for DDR controller registers
  45  * ctrl_num is the DDR controller number
  46  * step: 0 goes through the initialization in one pass
  47  *       1 sets registers and returns before enabling controller
  48  *       2 resumes from step 1 and continues to initialize
  49  * Dividing the initialization to two steps to deassert DDR reset signal
  50  * to comply with JEDEC specs for RDIMMs.
  51  */
  52 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  53                              unsigned int ctrl_num, int step)
  54 {
  55         unsigned int i, bus_width;
  56         struct ccsr_ddr __iomem *ddr;
  57         u32 temp32;
  58         u32 total_gb_size_per_controller;
  59         int timeout;
  60         int mod_bnds = 0;
  61
  62 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  63         u32 mr6;
  64         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  65         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  66         u32 *vref_seq = vref_seq1;
  67 #endif
  68 #ifdef CONFIG_FSL_DDR_BIST
  69         u32 mtcr, err_detect, err_sbe;
  70         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  71 #endif
  72 #ifdef CONFIG_FSL_DDR_BIST
  73         char buffer[CONFIG_SYS_CBSIZE];
  74 #endif
  75         switch (ctrl_num) {
  76         case 0:
  77                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  78                 break;
  79 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  80         case 1:
  81                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  82                 break;
  83 #endif
  84 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  85         case 2:
  86                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  87                 break;
  88 #endif
  89 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  90         case 3:
  91                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  92                 break;
  93 #endif
  94         default:
  95                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  96                 return;
  97         }
  98         mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
  99
 100         if (step == 2)
 101                 goto step2;
 102
 103         /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
 104         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 105
 106         if (regs->ddr_eor)
 107                 ddr_out32(&ddr->eor, regs->ddr_eor);
 108
 109         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 110         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 111                 if (i == 0) {
 112                         if (mod_bnds) {
 113                                 debug("modified bnds\n");
 114                                 ddr_out32(&ddr->cs0_bnds,
 115                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 116                                 ddr_out32(&ddr->cs0_config,
 117                                           (regs->cs[i].config &
 118                                            ~CTLR_INTLV_MASK));
 119                         } else {
 120                                 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 121                                 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 122                         }
 123                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 124
 125                 } else if (i == 1) {
 126                         if (mod_bnds) {
 127                                 ddr_out32(&ddr->cs1_bnds,
 128                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 129                         } else {
 130                                 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 131                         }
 132                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 133                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 134
 135                 } else if (i == 2) {
 136                         if (mod_bnds) {
 137                                 ddr_out32(&ddr->cs2_bnds,
 138                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 139                         } else {
 140                                 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 141                         }
 142                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 143                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 144
 145                 } else if (i == 3) {
 146                         if (mod_bnds) {
 147                                 ddr_out32(&ddr->cs3_bnds,
 148                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 149                         } else {
 150                                 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 151                         }
 152                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 153                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 154                 }
 155         }
 156
 157         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 158         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 159         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 160         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 161         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 162         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 163         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 164         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 165         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 166         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 167         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 168         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 169         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 170         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 171         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 172         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 173         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 174         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 175         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 176         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 177         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 178         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 179         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 180         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 181         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 182         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 183         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 184         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 185         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 186         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 187         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 188         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 189         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 190 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 191         ddr_out32(&ddr->sdram_interval,
 192                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 193 #else
 194         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 195 #endif
 196         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 197         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 198 #ifndef CONFIG_SYS_FSL_DDR_EMU
 199         /*
 200          * Skip these two registers if running on emulator
 201          * because emulator doesn't have skew between bytes.
 202          */
 203
 204         if (regs->ddr_wrlvl_cntl_2)
 205                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 206         if (regs->ddr_wrlvl_cntl_3)
 207                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 208 #endif
 209
 210         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 211         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 212         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 213         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 214         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 215         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 216         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 217 #ifdef CONFIG_DEEP_SLEEP
 218         if (is_warm_boot()) {
 219                 ddr_out32(&ddr->sdram_cfg_2,
 220                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 221                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 222                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 223
 224                 /* DRAM VRef will not be trained */
 225                 ddr_out32(&ddr->ddr_cdr2,
 226                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 227         } else
 228 #endif
 229         {
 230                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 231                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 232                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 233                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 234         }
 235
 236 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 237         /* part 1 of 2 */
 238         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 239                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
 240                         ddr_out32(&ddr->ddr_sdram_rcw_2,
 241                                   regs->ddr_sdram_rcw_2 & ~0xf0);
 242                 }
 243                 ddr_out32(&ddr->err_disable, regs->err_disable |
 244                           DDR_ERR_DISABLE_APED);
 245         }
 246 #else
 247         ddr_out32(&ddr->err_disable, regs->err_disable);
 248 #endif
 249         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 250         for (i = 0; i < 64; i++) {
 251                 if (regs->debug[i]) {
 252                         debug("Write to debug_%d as %08x\n",
 253                               i+1, regs->debug[i]);
 254                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 255                 }
 256         }
 257
 258 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 259         /* Part 1 of 2 */
 260         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 261                 /* Disable DRAM VRef training */
 262                 ddr_out32(&ddr->ddr_cdr2,
 263                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 264                 /* disable transmit bit deskew */
 265                 temp32 = ddr_in32(&ddr->debug[28]);
 266                 temp32 |= DDR_TX_BD_DIS;
 267                 ddr_out32(&ddr->debug[28], temp32);
 268                 ddr_out32(&ddr->debug[25], 0x9000);
 269         } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
 270                 /* Output enable forced off */
 271                 ddr_out32(&ddr->debug[37], 1 << 31);
 272                 /* Enable Vref training */
 273                 ddr_out32(&ddr->ddr_cdr2,
 274                           regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
 275         } else {
 276                 debug("Erratum A008511 doesn't apply.\n");
 277         }
 278 #endif
 279
 280 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
 281         defined(CONFIG_SYS_FSL_ERRATUM_A008511)
 282         /* Disable D_INIT */
 283         ddr_out32(&ddr->sdram_cfg_2,
 284                   regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 285 #endif
 286
 287 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 288         temp32 = ddr_in32(&ddr->debug[25]);
 289         temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
 290         temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
 291         ddr_out32(&ddr->debug[25], temp32);
 292 #endif
 293
 294 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
 295         temp32 = get_ddr_freq(ctrl_num) / 1000000;
 296         if ((temp32 > 1900) && (temp32 < 2300)) {
 297                 temp32 = ddr_in32(&ddr->debug[28]);
 298                 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
 299         }
 300 #endif
 301         /*
 302          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 303          * deasserted. Clocks start when any chip select is enabled and clock
 304          * control register is set. Because all DDR components are connected to
 305          * one reset signal, this needs to be done in two steps. Step 1 is to
 306          * get the clocks started. Step 2 resumes after reset signal is
 307          * deasserted.
 308          */
 309         if (step == 1) {
 310                 udelay(200);
 311                 return;
 312         }
 313
 314 step2:
 315         /* Set, but do not enable the memory */
 316         temp32 = regs->ddr_sdram_cfg;
 317         temp32 &= ~(SDRAM_CFG_MEM_EN);
 318         ddr_out32(&ddr->sdram_cfg, temp32);
 319
 320         /*
 321          * 500 painful micro-seconds must elapse between
 322          * the DDR clock setup and the DDR config enable.
 323          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 324          * we choose the max, that is 500 us for all of case.
 325          */
 326         udelay(500);
 327         mb();
 328         isb();
 329
 330 #ifdef CONFIG_DEEP_SLEEP
 331         if (is_warm_boot()) {
 332                 /* enter self-refresh */
 333                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 334                 temp32 |= SDRAM_CFG2_FRC_SR;
 335                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 336                 /* do board specific memory setup */
 337                 board_mem_sleep_setup();
 338
 339                 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 340         } else
 341 #endif
 342                 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 343         /* Let the controller go */
 344         ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
 345         mb();
 346         isb();
 347
 348 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 349         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 350         /* Part 2 of 2 */
 351         timeout = 40;
 352         /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
 353         while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 354                (timeout > 0)) {
 355                 udelay(1000);
 356                 timeout--;
 357         }
 358         if (timeout <= 0) {
 359                 printf("Controler %d timeout, debug_2 = %x\n",
 360                        ctrl_num, ddr_in32(&ddr->debug[1]));
 361         }
 362
 363 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 364         /* This erraum only applies to verion 5.2.0 */
 365         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 366                 /* The vref setting sequence is different for range 2 */
 367                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 368                         vref_seq = vref_seq2;
 369
 370                 /* Set VREF */
 371                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 372                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 373                                 continue;
 374
 375                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 376                                  MD_CNTL_MD_EN                          |
 377                                  MD_CNTL_CS_SEL(i)                      |
 378                                  MD_CNTL_MD_SEL(6)                      |
 379                                  0x00200000;
 380                         temp32 = mr6 | vref_seq[0];
 381                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 382                                                 temp32, MD_CNTL_MD_EN);
 383                         udelay(1);
 384                         debug("MR6 = 0x%08x\n", temp32);
 385                         temp32 = mr6 | vref_seq[1];
 386                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 387                                                 temp32, MD_CNTL_MD_EN);
 388                         udelay(1);
 389                         debug("MR6 = 0x%08x\n", temp32);
 390                         temp32 = mr6 | vref_seq[2];
 391                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 392                                                 temp32, MD_CNTL_MD_EN);
 393                         udelay(1);
 394                         debug("MR6 = 0x%08x\n", temp32);
 395                 }
 396                 ddr_out32(&ddr->sdram_md_cntl, 0);
 397                 temp32 = ddr_in32(&ddr->debug[28]);
 398                 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
 399                 ddr_out32(&ddr->debug[28], temp32);
 400                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 401                 /* wait for idle */
 402                 timeout = 40;
 403                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 404                        (timeout > 0)) {
 405                         udelay(1000);
 406                         timeout--;
 407                 }
 408                 if (timeout <= 0) {
 409                         printf("Controler %d timeout, debug_2 = %x\n",
 410                                ctrl_num, ddr_in32(&ddr->debug[1]));
 411                 }
 412         }
 413 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 414
 415 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 416         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 417                 /* if it's RDIMM */
 418                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
 419                         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 420                                 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 421                                         continue;
 422                                 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 423                                                         MD_CNTL_MD_EN |
 424                                                         MD_CNTL_CS_SEL(i) |
 425                                                         0x070000ed,
 426                                                         MD_CNTL_MD_EN);
 427                                 udelay(1);
 428                         }
 429                 }
 430
 431                 ddr_out32(&ddr->err_disable,
 432                           regs->err_disable & ~DDR_ERR_DISABLE_APED);
 433         }
 434 #endif
 435         /* Restore D_INIT */
 436         ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 437 #endif
 438
 439         total_gb_size_per_controller = 0;
 440         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 441                 if (!(regs->cs[i].config & 0x80000000))
 442                         continue;
 443                 total_gb_size_per_controller += 1 << (
 444                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 445                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 446                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 447                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 448                         ((regs->ddr_sdram_cfg_3 >> 4) & 0x3) +
 449                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 450                         26);                    /* minus 26 (count of 64M) */
 451         }
 452         /*
 453          * total memory / bus width = transactions needed
 454          * transactions needed / data rate = seconds
 455          * to add plenty of buffer, double the time
 456          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 457          * Let's wait for 800ms
 458          */
 459         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 460                         >> SDRAM_CFG_DBW_SHIFT);
 461         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 462                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 463         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 464         debug("total %d GB\n", total_gb_size_per_controller);
 465         debug("Need to wait up to %d * 10ms\n", timeout);
 466
 467         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 468         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 469                 (timeout >= 0)) {
 470                 udelay(10000);          /* throttle polling rate */
 471                 timeout--;
 472         }
 473
 474         if (timeout <= 0)
 475                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 476
 477         if (mod_bnds) {
 478                 debug("Reset to original bnds\n");
 479                 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
 480 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 481                 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
 482 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 483                 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
 484 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 485                 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
 486 #endif
 487 #endif
 488 #endif
 489                 ddr_out32(&ddr->cs0_config, regs->cs[0].config);
 490         }
 491
 492 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 493         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 494 #endif
 495
 496 #ifdef CONFIG_DEEP_SLEEP
 497         if (is_warm_boot()) {
 498                 /* exit self-refresh */
 499                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 500                 temp32 &= ~SDRAM_CFG2_FRC_SR;
 501                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 502         }
 503 #endif
 504
 505 #ifdef CONFIG_FSL_DDR_BIST
 506 #define BIST_PATTERN1   0xFFFFFFFF
 507 #define BIST_PATTERN2   0x0
 508 #define BIST_CR         0x80010000
 509 #define BIST_CR_EN      0x80000000
 510 #define BIST_CR_STAT    0x00000001
 511         /* Perform build-in test on memory. Three-way interleaving is not yet
 512          * supported by this code. */
 513         if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 514                 puts("Running BIST test. This will take a while...");
 515                 cs0_config = ddr_in32(&ddr->cs0_config);
 516                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 517                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 518                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 519                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 520                 if (cs0_config & CTLR_INTLV_MASK) {
 521                         /* set bnds to non-interleaving */
 522                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 523                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 524                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 525                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 526                 }
 527                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 528                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 529                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 530                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 531                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 532                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 533                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 534                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 535                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 536                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 537                 mtcr = BIST_CR;
 538                 ddr_out32(&ddr->mtcr, mtcr);
 539                 timeout = 100;
 540                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 541                         mdelay(1000);
 542                         timeout--;
 543                         mtcr = ddr_in32(&ddr->mtcr);
 544                 }
 545                 if (timeout <= 0)
 546                         puts("Timeout\n");
 547                 else
 548                         puts("Done\n");
 549                 err_detect = ddr_in32(&ddr->err_detect);
 550                 err_sbe = ddr_in32(&ddr->err_sbe);
 551                 if (mtcr & BIST_CR_STAT) {
 552                         printf("BIST test failed on controller %d.\n",
 553                                ctrl_num);
 554                 }
 555                 if (err_detect || (err_sbe & 0xffff)) {
 556                         printf("ECC error detected on controller %d.\n",
 557                                ctrl_num);
 558                 }
 559
 560                 if (cs0_config & CTLR_INTLV_MASK) {
 561                         /* restore bnds registers */
 562                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 563                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 564                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 565                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 566                 }
 567         }
 568 #endif
 569 }